decoder.isa revision 11877
16691Stjones1@inf.ed.ac.uk// -*- mode:c++ -*- 26691Stjones1@inf.ed.ac.uk 36691Stjones1@inf.ed.ac.uk// Copyright (c) 2009 The University of Edinburgh 46691Stjones1@inf.ed.ac.uk// All rights reserved. 56691Stjones1@inf.ed.ac.uk// 66691Stjones1@inf.ed.ac.uk// Redistribution and use in source and binary forms, with or without 76691Stjones1@inf.ed.ac.uk// modification, are permitted provided that the following conditions are 86691Stjones1@inf.ed.ac.uk// met: redistributions of source code must retain the above copyright 96691Stjones1@inf.ed.ac.uk// notice, this list of conditions and the following disclaimer; 106691Stjones1@inf.ed.ac.uk// redistributions in binary form must reproduce the above copyright 116691Stjones1@inf.ed.ac.uk// notice, this list of conditions and the following disclaimer in the 126691Stjones1@inf.ed.ac.uk// documentation and/or other materials provided with the distribution; 136691Stjones1@inf.ed.ac.uk// neither the name of the copyright holders nor the names of its 146691Stjones1@inf.ed.ac.uk// contributors may be used to endorse or promote products derived from 156691Stjones1@inf.ed.ac.uk// this software without specific prior written permission. 166691Stjones1@inf.ed.ac.uk// 176691Stjones1@inf.ed.ac.uk// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186691Stjones1@inf.ed.ac.uk// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196691Stjones1@inf.ed.ac.uk// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206691Stjones1@inf.ed.ac.uk// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216691Stjones1@inf.ed.ac.uk// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226691Stjones1@inf.ed.ac.uk// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236691Stjones1@inf.ed.ac.uk// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246691Stjones1@inf.ed.ac.uk// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256691Stjones1@inf.ed.ac.uk// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266691Stjones1@inf.ed.ac.uk// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276691Stjones1@inf.ed.ac.uk// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286691Stjones1@inf.ed.ac.uk// 296691Stjones1@inf.ed.ac.uk// Authors: Timothy M. Jones 306691Stjones1@inf.ed.ac.uk 316691Stjones1@inf.ed.ac.uk//////////////////////////////////////////////////////////////////// 326691Stjones1@inf.ed.ac.uk// 336691Stjones1@inf.ed.ac.uk// The actual Power ISA decoder 346691Stjones1@inf.ed.ac.uk// ------------------------------ 356691Stjones1@inf.ed.ac.uk// 366691Stjones1@inf.ed.ac.uk// I've used the Power ISA Book I v2.06 for instruction formats, 376691Stjones1@inf.ed.ac.uk// opcode numbers, register names, etc. 386691Stjones1@inf.ed.ac.uk// 396691Stjones1@inf.ed.ac.ukdecode OPCODE default Unknown::unknown() { 406691Stjones1@inf.ed.ac.uk 416691Stjones1@inf.ed.ac.uk format IntImmOp { 426691Stjones1@inf.ed.ac.uk 10: cmpli({{ 436691Stjones1@inf.ed.ac.uk Xer xer = XER; 446691Stjones1@inf.ed.ac.uk uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so); 456691Stjones1@inf.ed.ac.uk CR = insertCRField(CR, BF, cr); 466691Stjones1@inf.ed.ac.uk }}); 476691Stjones1@inf.ed.ac.uk 11: cmpi({{ 486691Stjones1@inf.ed.ac.uk Xer xer = XER; 498588Sgblack@eecs.umich.edu uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so); 506691Stjones1@inf.ed.ac.uk CR = insertCRField(CR, BF, cr); 516691Stjones1@inf.ed.ac.uk }}); 526691Stjones1@inf.ed.ac.uk } 536691Stjones1@inf.ed.ac.uk 546691Stjones1@inf.ed.ac.uk // Some instructions use bits 21 - 30, others 22 - 30. We have to use 556691Stjones1@inf.ed.ac.uk // the larger size to account for all opcodes. For those that use the 566691Stjones1@inf.ed.ac.uk // smaller value, the OE bit is bit 21. Therefore, we have two versions 576691Stjones1@inf.ed.ac.uk // of each instruction: 1 with OE set, the other without. For an 586691Stjones1@inf.ed.ac.uk // example see 'add' and 'addo'. 596691Stjones1@inf.ed.ac.uk 31: decode XO_XO { 606691Stjones1@inf.ed.ac.uk 616691Stjones1@inf.ed.ac.uk // These instructions can all be reduced to the form 626691Stjones1@inf.ed.ac.uk // Rt = src1 + src2 [+ CA], therefore we just give src1 and src2 636691Stjones1@inf.ed.ac.uk // (and, if necessary, CA) definitions and let the python script 646691Stjones1@inf.ed.ac.uk // deal with setting things up correctly. We also give flags to 656691Stjones1@inf.ed.ac.uk // say which control registers to set. 666691Stjones1@inf.ed.ac.uk format IntSumOp { 676691Stjones1@inf.ed.ac.uk 266: add({{ Ra }}, {{ Rb }}); 686691Stjones1@inf.ed.ac.uk 40: subf({{ ~Ra }}, {{ Rb }}, {{ 1 }}); 696691Stjones1@inf.ed.ac.uk 10: addc({{ Ra }}, {{ Rb }}, 706691Stjones1@inf.ed.ac.uk computeCA = true); 716691Stjones1@inf.ed.ac.uk 8: subfc({{ ~Ra }}, {{ Rb }}, {{ 1 }}, 726691Stjones1@inf.ed.ac.uk true); 736691Stjones1@inf.ed.ac.uk 104: neg({{ ~Ra }}, {{ 1 }}); 746691Stjones1@inf.ed.ac.uk 138: adde({{ Ra }}, {{ Rb }}, {{ xer.ca }}, 756691Stjones1@inf.ed.ac.uk true); 766691Stjones1@inf.ed.ac.uk 234: addme({{ Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }}, 776691Stjones1@inf.ed.ac.uk true); 786691Stjones1@inf.ed.ac.uk 136: subfe({{ ~Ra }}, {{ Rb }}, {{ xer.ca }}, 796691Stjones1@inf.ed.ac.uk true); 806691Stjones1@inf.ed.ac.uk 232: subfme({{ ~Ra }}, {{ (uint32_t)-1 }}, {{ xer.ca }}, 816691Stjones1@inf.ed.ac.uk true); 826691Stjones1@inf.ed.ac.uk 202: addze({{ Ra }}, {{ xer.ca }}, 836691Stjones1@inf.ed.ac.uk computeCA = true); 846691Stjones1@inf.ed.ac.uk 200: subfze({{ ~Ra }}, {{ xer.ca }}, 856691Stjones1@inf.ed.ac.uk computeCA = true); 866691Stjones1@inf.ed.ac.uk } 876691Stjones1@inf.ed.ac.uk 886691Stjones1@inf.ed.ac.uk // Arithmetic instructions all use source registers Ra and Rb, 896691Stjones1@inf.ed.ac.uk // with destination register Rt. 906691Stjones1@inf.ed.ac.uk format IntArithOp { 918588Sgblack@eecs.umich.edu 75: mulhw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod >> 32; }}); 928588Sgblack@eecs.umich.edu 11: mulhwu({{ uint64_t prod = Ra_uq * Rb_uq; Rt = prod >> 32; }}); 938588Sgblack@eecs.umich.edu 235: mullw({{ int64_t prod = Ra_sq * Rb_sq; Rt = prod; }}); 948588Sgblack@eecs.umich.edu 747: mullwo({{ int64_t src1 = Ra_sq; int64_t src2 = Rb; int64_t prod = src1 * src2; Rt = prod; }}, 956691Stjones1@inf.ed.ac.uk true); 966691Stjones1@inf.ed.ac.uk 976691Stjones1@inf.ed.ac.uk 491: divw({{ 988588Sgblack@eecs.umich.edu int32_t src1 = Ra_sw; 998588Sgblack@eecs.umich.edu int32_t src2 = Rb_sw; 1006691Stjones1@inf.ed.ac.uk if ((src1 != 0x80000000 || src2 != 0xffffffff) 1016691Stjones1@inf.ed.ac.uk && src2 != 0) { 1026691Stjones1@inf.ed.ac.uk Rt = src1 / src2; 1036691Stjones1@inf.ed.ac.uk } else { 1046691Stjones1@inf.ed.ac.uk Rt = 0; 1056691Stjones1@inf.ed.ac.uk } 1066691Stjones1@inf.ed.ac.uk }}); 1076691Stjones1@inf.ed.ac.uk 1086691Stjones1@inf.ed.ac.uk 1003: divwo({{ 1098588Sgblack@eecs.umich.edu int32_t src1 = Ra_sw; 1108588Sgblack@eecs.umich.edu int32_t src2 = Rb_sw; 1116691Stjones1@inf.ed.ac.uk if ((src1 != 0x80000000 || src2 != 0xffffffff) 1126691Stjones1@inf.ed.ac.uk && src2 != 0) { 1136691Stjones1@inf.ed.ac.uk Rt = src1 / src2; 1146691Stjones1@inf.ed.ac.uk } else { 1156691Stjones1@inf.ed.ac.uk Rt = 0; 1166691Stjones1@inf.ed.ac.uk divSetOV = true; 1176691Stjones1@inf.ed.ac.uk } 1186691Stjones1@inf.ed.ac.uk }}, 1196691Stjones1@inf.ed.ac.uk true); 1206691Stjones1@inf.ed.ac.uk 1216691Stjones1@inf.ed.ac.uk 459: divwu({{ 1228588Sgblack@eecs.umich.edu uint32_t src1 = Ra_sw; 1238588Sgblack@eecs.umich.edu uint32_t src2 = Rb_sw; 1246691Stjones1@inf.ed.ac.uk if (src2 != 0) { 1256691Stjones1@inf.ed.ac.uk Rt = src1 / src2; 1266691Stjones1@inf.ed.ac.uk } else { 1276691Stjones1@inf.ed.ac.uk Rt = 0; 1286691Stjones1@inf.ed.ac.uk } 1296691Stjones1@inf.ed.ac.uk }}); 1306691Stjones1@inf.ed.ac.uk 1316691Stjones1@inf.ed.ac.uk 971: divwuo({{ 1328588Sgblack@eecs.umich.edu uint32_t src1 = Ra_sw; 1338588Sgblack@eecs.umich.edu uint32_t src2 = Rb_sw; 1346691Stjones1@inf.ed.ac.uk if (src2 != 0) { 1356691Stjones1@inf.ed.ac.uk Rt = src1 / src2; 1366691Stjones1@inf.ed.ac.uk } else { 1376691Stjones1@inf.ed.ac.uk Rt = 0; 1386691Stjones1@inf.ed.ac.uk divSetOV = true; 1396691Stjones1@inf.ed.ac.uk } 1406691Stjones1@inf.ed.ac.uk }}, 1416691Stjones1@inf.ed.ac.uk true); 1426691Stjones1@inf.ed.ac.uk } 1436691Stjones1@inf.ed.ac.uk 1446691Stjones1@inf.ed.ac.uk // Integer logic instructions use source registers Rs and Rb, 1456691Stjones1@inf.ed.ac.uk // with destination register Ra. 1466691Stjones1@inf.ed.ac.uk format IntLogicOp { 1476691Stjones1@inf.ed.ac.uk 28: and({{ Ra = Rs & Rb; }}); 1486691Stjones1@inf.ed.ac.uk 316: xor({{ Ra = Rs ^ Rb; }}); 1496691Stjones1@inf.ed.ac.uk 476: nand({{ Ra = ~(Rs & Rb); }}); 1506691Stjones1@inf.ed.ac.uk 444: or({{ Ra = Rs | Rb; }}); 1516691Stjones1@inf.ed.ac.uk 124: nor({{ Ra = ~(Rs | Rb); }}); 1526691Stjones1@inf.ed.ac.uk 60: andc({{ Ra = Rs & ~Rb; }}); 1536691Stjones1@inf.ed.ac.uk 954: extsb({{ Ra = sext<8>(Rs); }}); 1546691Stjones1@inf.ed.ac.uk 284: eqv({{ Ra = ~(Rs ^ Rb); }}); 1556691Stjones1@inf.ed.ac.uk 412: orc({{ Ra = Rs | ~Rb; }}); 1566691Stjones1@inf.ed.ac.uk 922: extsh({{ Ra = sext<16>(Rs); }}); 1576691Stjones1@inf.ed.ac.uk 26: cntlzw({{ Ra = Rs == 0 ? 32 : 31 - findMsbSet(Rs); }}); 1586691Stjones1@inf.ed.ac.uk 508: cmpb({{ 1596691Stjones1@inf.ed.ac.uk uint32_t val = 0; 1606691Stjones1@inf.ed.ac.uk for (int n = 0; n < 32; n += 8) { 1616691Stjones1@inf.ed.ac.uk if(bits(Rs, n, n+7) == bits(Rb, n, n+7)) { 1626691Stjones1@inf.ed.ac.uk val = insertBits(val, n, n+7, 0xff); 1636691Stjones1@inf.ed.ac.uk } 1646691Stjones1@inf.ed.ac.uk } 1656691Stjones1@inf.ed.ac.uk Ra = val; 1666691Stjones1@inf.ed.ac.uk }}); 1676691Stjones1@inf.ed.ac.uk 1686691Stjones1@inf.ed.ac.uk 24: slw({{ 1696691Stjones1@inf.ed.ac.uk if (Rb & 0x20) { 1706691Stjones1@inf.ed.ac.uk Ra = 0; 1716691Stjones1@inf.ed.ac.uk } else { 1726691Stjones1@inf.ed.ac.uk Ra = Rs << (Rb & 0x1f); 1736691Stjones1@inf.ed.ac.uk } 1746691Stjones1@inf.ed.ac.uk }}); 1756691Stjones1@inf.ed.ac.uk 1766691Stjones1@inf.ed.ac.uk 536: srw({{ 1776691Stjones1@inf.ed.ac.uk if (Rb & 0x20) { 1786691Stjones1@inf.ed.ac.uk Ra = 0; 1796691Stjones1@inf.ed.ac.uk } else { 1806691Stjones1@inf.ed.ac.uk Ra = Rs >> (Rb & 0x1f); 1816691Stjones1@inf.ed.ac.uk } 1826691Stjones1@inf.ed.ac.uk }}); 1836691Stjones1@inf.ed.ac.uk 1846691Stjones1@inf.ed.ac.uk 792: sraw({{ 1856691Stjones1@inf.ed.ac.uk bool shiftSetCA = false; 1866691Stjones1@inf.ed.ac.uk int32_t s = Rs; 1876691Stjones1@inf.ed.ac.uk if (Rb == 0) { 1886691Stjones1@inf.ed.ac.uk Ra = Rs; 1896691Stjones1@inf.ed.ac.uk shiftSetCA = true; 1906691Stjones1@inf.ed.ac.uk } else if (Rb & 0x20) { 1916691Stjones1@inf.ed.ac.uk if (s < 0) { 1926691Stjones1@inf.ed.ac.uk Ra = (uint32_t)-1; 1936691Stjones1@inf.ed.ac.uk if (s & 0x7fffffff) { 1946691Stjones1@inf.ed.ac.uk shiftSetCA = true; 1956691Stjones1@inf.ed.ac.uk } else { 1966691Stjones1@inf.ed.ac.uk shiftSetCA = false; 1976691Stjones1@inf.ed.ac.uk } 1986691Stjones1@inf.ed.ac.uk } else { 1996691Stjones1@inf.ed.ac.uk Ra = 0; 2006691Stjones1@inf.ed.ac.uk shiftSetCA = false; 2016691Stjones1@inf.ed.ac.uk } 2026691Stjones1@inf.ed.ac.uk } else { 2036691Stjones1@inf.ed.ac.uk Ra = s >> (Rb & 0x1f); 2046691Stjones1@inf.ed.ac.uk if (s < 0 && (s << (32 - (Rb & 0x1f))) != 0) { 2056691Stjones1@inf.ed.ac.uk shiftSetCA = true; 2066691Stjones1@inf.ed.ac.uk } else { 2076691Stjones1@inf.ed.ac.uk shiftSetCA = false; 2086691Stjones1@inf.ed.ac.uk } 2096691Stjones1@inf.ed.ac.uk } 2106691Stjones1@inf.ed.ac.uk Xer xer1 = XER; 2116691Stjones1@inf.ed.ac.uk if (shiftSetCA) { 2126691Stjones1@inf.ed.ac.uk xer1.ca = 1; 2136691Stjones1@inf.ed.ac.uk } else { 2146691Stjones1@inf.ed.ac.uk xer1.ca = 0; 2156691Stjones1@inf.ed.ac.uk } 2166691Stjones1@inf.ed.ac.uk XER = xer1; 2176691Stjones1@inf.ed.ac.uk }}); 2186691Stjones1@inf.ed.ac.uk } 2196691Stjones1@inf.ed.ac.uk 2206691Stjones1@inf.ed.ac.uk // Integer logic instructions with a shift value. 2216691Stjones1@inf.ed.ac.uk format IntShiftOp { 2226691Stjones1@inf.ed.ac.uk 824: srawi({{ 2236691Stjones1@inf.ed.ac.uk bool shiftSetCA = false; 2246691Stjones1@inf.ed.ac.uk if (sh == 0) { 2256691Stjones1@inf.ed.ac.uk Ra = Rs; 2266691Stjones1@inf.ed.ac.uk shiftSetCA = false; 2276691Stjones1@inf.ed.ac.uk } else { 2286691Stjones1@inf.ed.ac.uk int32_t s = Rs; 2296691Stjones1@inf.ed.ac.uk Ra = s >> sh; 2306691Stjones1@inf.ed.ac.uk if (s < 0 && (s << (32 - sh)) != 0) { 2316691Stjones1@inf.ed.ac.uk shiftSetCA = true; 2326691Stjones1@inf.ed.ac.uk } else { 2336691Stjones1@inf.ed.ac.uk shiftSetCA = false; 2346691Stjones1@inf.ed.ac.uk } 2356691Stjones1@inf.ed.ac.uk } 2366691Stjones1@inf.ed.ac.uk Xer xer1 = XER; 2376691Stjones1@inf.ed.ac.uk if (shiftSetCA) { 2386691Stjones1@inf.ed.ac.uk xer1.ca = 1; 2396691Stjones1@inf.ed.ac.uk } else { 2406691Stjones1@inf.ed.ac.uk xer1.ca = 0; 2416691Stjones1@inf.ed.ac.uk } 2426691Stjones1@inf.ed.ac.uk XER = xer1; 2436691Stjones1@inf.ed.ac.uk }}); 2446691Stjones1@inf.ed.ac.uk } 2456691Stjones1@inf.ed.ac.uk 2466691Stjones1@inf.ed.ac.uk // Generic integer format instructions. 2476691Stjones1@inf.ed.ac.uk format IntOp { 2486691Stjones1@inf.ed.ac.uk 0: cmp({{ 2496691Stjones1@inf.ed.ac.uk Xer xer = XER; 2508588Sgblack@eecs.umich.edu uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so); 2516691Stjones1@inf.ed.ac.uk CR = insertCRField(CR, BF, cr); 2526691Stjones1@inf.ed.ac.uk }}); 2536691Stjones1@inf.ed.ac.uk 32: cmpl({{ 2546691Stjones1@inf.ed.ac.uk Xer xer = XER; 2556691Stjones1@inf.ed.ac.uk uint32_t cr = makeCRField(Ra, Rb, xer.so); 2566691Stjones1@inf.ed.ac.uk CR = insertCRField(CR, BF, cr); 2576691Stjones1@inf.ed.ac.uk }}); 2586691Stjones1@inf.ed.ac.uk 144: mtcrf({{ 2596691Stjones1@inf.ed.ac.uk uint32_t mask = 0; 2606691Stjones1@inf.ed.ac.uk for (int i = 0; i < 8; ++i) { 2616691Stjones1@inf.ed.ac.uk if (((FXM >> i) & 0x1) == 0x1) { 2626691Stjones1@inf.ed.ac.uk mask |= 0xf << (4 * i); 2636691Stjones1@inf.ed.ac.uk } 2646691Stjones1@inf.ed.ac.uk } 2656691Stjones1@inf.ed.ac.uk CR = (Rs & mask) | (CR & ~mask); 2666691Stjones1@inf.ed.ac.uk }}); 2676691Stjones1@inf.ed.ac.uk 19: mfcr({{ Rt = CR; }}); 2686691Stjones1@inf.ed.ac.uk 339: decode SPR { 2696691Stjones1@inf.ed.ac.uk 0x20: mfxer({{ Rt = XER; }}); 2706691Stjones1@inf.ed.ac.uk 0x100: mflr({{ Rt = LR; }}); 2716691Stjones1@inf.ed.ac.uk 0x120: mfctr({{ Rt = CTR; }}); 2726691Stjones1@inf.ed.ac.uk } 2736691Stjones1@inf.ed.ac.uk 467: decode SPR { 2746691Stjones1@inf.ed.ac.uk 0x20: mtxer({{ XER = Rs; }}); 2756691Stjones1@inf.ed.ac.uk 0x100: mtlr({{ LR = Rs; }}); 2766691Stjones1@inf.ed.ac.uk 0x120: mtctr({{ CTR = Rs; }}); 2776691Stjones1@inf.ed.ac.uk } 2786691Stjones1@inf.ed.ac.uk } 2796691Stjones1@inf.ed.ac.uk 2806691Stjones1@inf.ed.ac.uk // All loads with an index register. The non-update versions 2816691Stjones1@inf.ed.ac.uk // all use the value 0 if Ra == R0, not the value contained in 2826691Stjones1@inf.ed.ac.uk // R0. Others update Ra with the effective address. In all cases, 2836691Stjones1@inf.ed.ac.uk // Ra and Rb are source registers, Rt is the destintation. 2846691Stjones1@inf.ed.ac.uk format LoadIndexOp { 2858588Sgblack@eecs.umich.edu 87: lbzx({{ Rt = Mem_ub; }}); 2868588Sgblack@eecs.umich.edu 279: lhzx({{ Rt = Mem_uh; }}); 2878588Sgblack@eecs.umich.edu 343: lhax({{ Rt = Mem_sh; }}); 2886691Stjones1@inf.ed.ac.uk 23: lwzx({{ Rt = Mem; }}); 2898588Sgblack@eecs.umich.edu 341: lwax({{ Rt = Mem_sw; }}); 2908588Sgblack@eecs.umich.edu 20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }}); 2918588Sgblack@eecs.umich.edu 535: lfsx({{ Ft_sf = Mem_sf; }}); 2928588Sgblack@eecs.umich.edu 599: lfdx({{ Ft = Mem_df; }}); 2938588Sgblack@eecs.umich.edu 855: lfiwax({{ Ft_uw = Mem; }}); 2946691Stjones1@inf.ed.ac.uk } 2956691Stjones1@inf.ed.ac.uk 2966691Stjones1@inf.ed.ac.uk format LoadIndexUpdateOp { 2978588Sgblack@eecs.umich.edu 119: lbzux({{ Rt = Mem_ub; }}); 2988588Sgblack@eecs.umich.edu 311: lhzux({{ Rt = Mem_uh; }}); 2998588Sgblack@eecs.umich.edu 375: lhaux({{ Rt = Mem_sh; }}); 3006691Stjones1@inf.ed.ac.uk 55: lwzux({{ Rt = Mem; }}); 3018588Sgblack@eecs.umich.edu 373: lwaux({{ Rt = Mem_sw; }}); 3028588Sgblack@eecs.umich.edu 567: lfsux({{ Ft_sf = Mem_sf; }}); 3038588Sgblack@eecs.umich.edu 631: lfdux({{ Ft = Mem_df; }}); 3046691Stjones1@inf.ed.ac.uk } 3056691Stjones1@inf.ed.ac.uk 3066691Stjones1@inf.ed.ac.uk format StoreIndexOp { 3078588Sgblack@eecs.umich.edu 215: stbx({{ Mem_ub = Rs_ub; }}); 3088588Sgblack@eecs.umich.edu 407: sthx({{ Mem_uh = Rs_uh; }}); 3096691Stjones1@inf.ed.ac.uk 151: stwx({{ Mem = Rs; }}); 3106691Stjones1@inf.ed.ac.uk 150: stwcx({{ 3116691Stjones1@inf.ed.ac.uk bool store_performed = false; 31211327Ssteve.reinhardt@amd.com Mem = Rs; 3136691Stjones1@inf.ed.ac.uk if (Rsv) { 3146691Stjones1@inf.ed.ac.uk if (RsvLen == 4) { 3156691Stjones1@inf.ed.ac.uk if (RsvAddr == EA) { 3166691Stjones1@inf.ed.ac.uk store_performed = true; 3176691Stjones1@inf.ed.ac.uk } 3186691Stjones1@inf.ed.ac.uk } 3196691Stjones1@inf.ed.ac.uk } 3206691Stjones1@inf.ed.ac.uk Xer xer = XER; 3216691Stjones1@inf.ed.ac.uk Cr cr = CR; 3226691Stjones1@inf.ed.ac.uk cr.cr0 = ((store_performed ? 0x2 : 0x0) | xer.so); 3236691Stjones1@inf.ed.ac.uk CR = cr; 3246691Stjones1@inf.ed.ac.uk Rsv = 0; 3256691Stjones1@inf.ed.ac.uk }}); 3268588Sgblack@eecs.umich.edu 663: stfsx({{ Mem_sf = Fs_sf; }}); 3278588Sgblack@eecs.umich.edu 727: stfdx({{ Mem_df = Fs; }}); 3288588Sgblack@eecs.umich.edu 983: stfiwx({{ Mem = Fs_uw; }}); 3296691Stjones1@inf.ed.ac.uk } 3306691Stjones1@inf.ed.ac.uk 3316691Stjones1@inf.ed.ac.uk format StoreIndexUpdateOp { 3328588Sgblack@eecs.umich.edu 247: stbux({{ Mem_ub = Rs_ub; }}); 3338588Sgblack@eecs.umich.edu 439: sthux({{ Mem_uh = Rs_uh; }}); 3346691Stjones1@inf.ed.ac.uk 183: stwux({{ Mem = Rs; }}); 3358588Sgblack@eecs.umich.edu 695: stfsux({{ Mem_sf = Fs_sf; }}); 3368588Sgblack@eecs.umich.edu 759: stfdux({{ Mem_df = Fs; }}); 3376691Stjones1@inf.ed.ac.uk } 3386691Stjones1@inf.ed.ac.uk 3396691Stjones1@inf.ed.ac.uk // These instructions all provide data cache hints 3406691Stjones1@inf.ed.ac.uk format MiscOp { 3416691Stjones1@inf.ed.ac.uk 278: dcbt({{ }}); 3426691Stjones1@inf.ed.ac.uk 246: dcbtst({{ }}); 3436691Stjones1@inf.ed.ac.uk 598: sync({{ }}, [ IsMemBarrier ]); 3446691Stjones1@inf.ed.ac.uk 854: eieio({{ }}, [ IsMemBarrier ]); 3456691Stjones1@inf.ed.ac.uk } 3466691Stjones1@inf.ed.ac.uk } 3476691Stjones1@inf.ed.ac.uk 3486691Stjones1@inf.ed.ac.uk format IntImmArithCheckRaOp { 3496691Stjones1@inf.ed.ac.uk 14: addi({{ Rt = Ra + imm; }}, 3506691Stjones1@inf.ed.ac.uk {{ Rt = imm }}); 3516691Stjones1@inf.ed.ac.uk 15: addis({{ Rt = Ra + (imm << 16); }}, 3526691Stjones1@inf.ed.ac.uk {{ Rt = imm << 16; }}); 3536691Stjones1@inf.ed.ac.uk } 3546691Stjones1@inf.ed.ac.uk 3556691Stjones1@inf.ed.ac.uk format IntImmArithOp { 3566691Stjones1@inf.ed.ac.uk 12: addic({{ uint32_t src = Ra; Rt = src + imm; }}, 3576691Stjones1@inf.ed.ac.uk [computeCA]); 3586691Stjones1@inf.ed.ac.uk 13: addic_({{ uint32_t src = Ra; Rt = src + imm; }}, 3596691Stjones1@inf.ed.ac.uk [computeCA, computeCR0]); 3606691Stjones1@inf.ed.ac.uk 8: subfic({{ int32_t src = ~Ra; Rt = src + imm + 1; }}, 3616691Stjones1@inf.ed.ac.uk [computeCA]); 3626691Stjones1@inf.ed.ac.uk 7: mulli({{ 3638588Sgblack@eecs.umich.edu int32_t src = Ra_sw; 3646691Stjones1@inf.ed.ac.uk int64_t prod = src * imm; 3656691Stjones1@inf.ed.ac.uk Rt = (uint32_t)prod; 3666691Stjones1@inf.ed.ac.uk }}); 3676691Stjones1@inf.ed.ac.uk } 3686691Stjones1@inf.ed.ac.uk 3696691Stjones1@inf.ed.ac.uk format IntImmLogicOp { 3706691Stjones1@inf.ed.ac.uk 24: ori({{ Ra = Rs | uimm; }}); 3716691Stjones1@inf.ed.ac.uk 25: oris({{ Ra = Rs | (uimm << 16); }}); 3726691Stjones1@inf.ed.ac.uk 26: xori({{ Ra = Rs ^ uimm; }}); 3736691Stjones1@inf.ed.ac.uk 27: xoris({{ Ra = Rs ^ (uimm << 16); }}); 3746691Stjones1@inf.ed.ac.uk 28: andi_({{ Ra = Rs & uimm; }}, 3756691Stjones1@inf.ed.ac.uk true); 3766691Stjones1@inf.ed.ac.uk 29: andis_({{ Ra = Rs & (uimm << 16); }}, 3776691Stjones1@inf.ed.ac.uk true); 3786691Stjones1@inf.ed.ac.uk } 3796691Stjones1@inf.ed.ac.uk 3806691Stjones1@inf.ed.ac.uk 16: decode AA { 3816691Stjones1@inf.ed.ac.uk 3826691Stjones1@inf.ed.ac.uk // Conditionally branch relative to PC based on CR and CTR. 3836691Stjones1@inf.ed.ac.uk format BranchPCRelCondCtr { 3847791Sgblack@eecs.umich.edu 0: bc({{ NPC = (uint32_t)(PC + disp); }}); 3856691Stjones1@inf.ed.ac.uk } 3866691Stjones1@inf.ed.ac.uk 3876691Stjones1@inf.ed.ac.uk // Conditionally branch to fixed address based on CR and CTR. 3886691Stjones1@inf.ed.ac.uk format BranchNonPCRelCondCtr { 3897791Sgblack@eecs.umich.edu 1: bca({{ NPC = targetAddr; }}); 3906691Stjones1@inf.ed.ac.uk } 3916691Stjones1@inf.ed.ac.uk } 3926691Stjones1@inf.ed.ac.uk 3936691Stjones1@inf.ed.ac.uk 18: decode AA { 3946691Stjones1@inf.ed.ac.uk 3956691Stjones1@inf.ed.ac.uk // Unconditionally branch relative to PC. 3966691Stjones1@inf.ed.ac.uk format BranchPCRel { 3977791Sgblack@eecs.umich.edu 0: b({{ NPC = (uint32_t)(PC + disp); }}); 3986691Stjones1@inf.ed.ac.uk } 3996691Stjones1@inf.ed.ac.uk 4006691Stjones1@inf.ed.ac.uk // Unconditionally branch to fixed address. 4016691Stjones1@inf.ed.ac.uk format BranchNonPCRel { 4027791Sgblack@eecs.umich.edu 1: ba({{ NPC = targetAddr; }}); 4036691Stjones1@inf.ed.ac.uk } 4046691Stjones1@inf.ed.ac.uk } 4056691Stjones1@inf.ed.ac.uk 4066691Stjones1@inf.ed.ac.uk 19: decode XO_XO { 4076691Stjones1@inf.ed.ac.uk 4086691Stjones1@inf.ed.ac.uk // Conditionally branch to address in LR based on CR and CTR. 4096691Stjones1@inf.ed.ac.uk format BranchLrCondCtr { 4107791Sgblack@eecs.umich.edu 16: bclr({{ NPC = LR & 0xfffffffc; }}); 4116691Stjones1@inf.ed.ac.uk } 4126691Stjones1@inf.ed.ac.uk 4136691Stjones1@inf.ed.ac.uk // Conditionally branch to address in CTR based on CR. 4146691Stjones1@inf.ed.ac.uk format BranchCtrCond { 4157791Sgblack@eecs.umich.edu 528: bcctr({{ NPC = CTR & 0xfffffffc; }}); 4166691Stjones1@inf.ed.ac.uk } 4176691Stjones1@inf.ed.ac.uk 4186691Stjones1@inf.ed.ac.uk // Condition register manipulation instructions. 4196691Stjones1@inf.ed.ac.uk format CondLogicOp { 4206691Stjones1@inf.ed.ac.uk 257: crand({{ 4216691Stjones1@inf.ed.ac.uk uint32_t crBa = bits(CR, 31 - ba); 4226691Stjones1@inf.ed.ac.uk uint32_t crBb = bits(CR, 31 - bb); 4236691Stjones1@inf.ed.ac.uk CR = insertBits(CR, 31 - bt, crBa & crBb); 4246691Stjones1@inf.ed.ac.uk }}); 4256691Stjones1@inf.ed.ac.uk 449: cror({{ 4266691Stjones1@inf.ed.ac.uk uint32_t crBa = bits(CR, 31 - ba); 4276691Stjones1@inf.ed.ac.uk uint32_t crBb = bits(CR, 31 - bb); 4286691Stjones1@inf.ed.ac.uk CR = insertBits(CR, 31 - bt, crBa | crBb); 4296691Stjones1@inf.ed.ac.uk }}); 4306691Stjones1@inf.ed.ac.uk 255: crnand({{ 4316691Stjones1@inf.ed.ac.uk uint32_t crBa = bits(CR, 31 - ba); 4326691Stjones1@inf.ed.ac.uk uint32_t crBb = bits(CR, 31 - bb); 4336691Stjones1@inf.ed.ac.uk CR = insertBits(CR, 31 - bt, !(crBa & crBb)); 4346691Stjones1@inf.ed.ac.uk }}); 4356691Stjones1@inf.ed.ac.uk 193: crxor({{ 4366691Stjones1@inf.ed.ac.uk uint32_t crBa = bits(CR, 31 - ba); 4376691Stjones1@inf.ed.ac.uk uint32_t crBb = bits(CR, 31 - bb); 4386691Stjones1@inf.ed.ac.uk CR = insertBits(CR, 31 - bt, crBa ^ crBb); 4396691Stjones1@inf.ed.ac.uk }}); 4406691Stjones1@inf.ed.ac.uk 33: crnor({{ 4416691Stjones1@inf.ed.ac.uk uint32_t crBa = bits(CR, 31 - ba); 4426691Stjones1@inf.ed.ac.uk uint32_t crBb = bits(CR, 31 - bb); 4436691Stjones1@inf.ed.ac.uk CR = insertBits(CR, 31 - bt, !(crBa | crBb)); 4446691Stjones1@inf.ed.ac.uk }}); 4456691Stjones1@inf.ed.ac.uk 289: creqv({{ 4466691Stjones1@inf.ed.ac.uk uint32_t crBa = bits(CR, 31 - ba); 4476691Stjones1@inf.ed.ac.uk uint32_t crBb = bits(CR, 31 - bb); 4486691Stjones1@inf.ed.ac.uk CR = insertBits(CR, 31 - bt, crBa == crBb); 4496691Stjones1@inf.ed.ac.uk }}); 4506691Stjones1@inf.ed.ac.uk 129: crandc({{ 4516691Stjones1@inf.ed.ac.uk uint32_t crBa = bits(CR, 31 - ba); 4526691Stjones1@inf.ed.ac.uk uint32_t crBb = bits(CR, 31 - bb); 4536691Stjones1@inf.ed.ac.uk CR = insertBits(CR, 31 - bt, crBa & !crBb); 4546691Stjones1@inf.ed.ac.uk }}); 4556691Stjones1@inf.ed.ac.uk 417: crorc({{ 4566691Stjones1@inf.ed.ac.uk uint32_t crBa = bits(CR, 31 - ba); 4576691Stjones1@inf.ed.ac.uk uint32_t crBb = bits(CR, 31 - bb); 4586691Stjones1@inf.ed.ac.uk CR = insertBits(CR, 31 - bt, crBa | !crBb); 4596691Stjones1@inf.ed.ac.uk }}); 4606691Stjones1@inf.ed.ac.uk } 4616691Stjones1@inf.ed.ac.uk format CondMoveOp { 4626691Stjones1@inf.ed.ac.uk 0: mcrf({{ 4636691Stjones1@inf.ed.ac.uk uint32_t crBfa = bits(CR, 31 - bfa*4, 28 - bfa*4); 4646691Stjones1@inf.ed.ac.uk CR = insertBits(CR, 31 - bf*4, 28 - bf*4, crBfa); 4656691Stjones1@inf.ed.ac.uk }}); 4666691Stjones1@inf.ed.ac.uk } 4676691Stjones1@inf.ed.ac.uk format MiscOp { 4686691Stjones1@inf.ed.ac.uk 150: isync({{ }}, [ IsSerializeAfter ]); 4696691Stjones1@inf.ed.ac.uk } 4706691Stjones1@inf.ed.ac.uk } 4716691Stjones1@inf.ed.ac.uk 4726691Stjones1@inf.ed.ac.uk format IntRotateOp { 4736691Stjones1@inf.ed.ac.uk 21: rlwinm({{ Ra = rotateValue(Rs, sh) & fullMask; }}); 4746691Stjones1@inf.ed.ac.uk 23: rlwnm({{ Ra = rotateValue(Rs, Rb) & fullMask; }}); 4756691Stjones1@inf.ed.ac.uk 20: rlwimi({{ Ra = (rotateValue(Rs, sh) & fullMask) | (Ra & ~fullMask); }}); 4766691Stjones1@inf.ed.ac.uk } 4776691Stjones1@inf.ed.ac.uk 4786691Stjones1@inf.ed.ac.uk format LoadDispOp { 4798588Sgblack@eecs.umich.edu 34: lbz({{ Rt = Mem_ub; }}); 4808588Sgblack@eecs.umich.edu 40: lhz({{ Rt = Mem_uh; }}); 4818588Sgblack@eecs.umich.edu 42: lha({{ Rt = Mem_sh; }}); 4826691Stjones1@inf.ed.ac.uk 32: lwz({{ Rt = Mem; }}); 4838588Sgblack@eecs.umich.edu 58: lwa({{ Rt = Mem_sw; }}, 4846691Stjones1@inf.ed.ac.uk {{ EA = Ra + (disp & 0xfffffffc); }}, 4856691Stjones1@inf.ed.ac.uk {{ EA = disp & 0xfffffffc; }}); 4868588Sgblack@eecs.umich.edu 48: lfs({{ Ft_sf = Mem_sf; }}); 4878588Sgblack@eecs.umich.edu 50: lfd({{ Ft = Mem_df; }}); 4886691Stjones1@inf.ed.ac.uk } 4896691Stjones1@inf.ed.ac.uk 4906691Stjones1@inf.ed.ac.uk format LoadDispUpdateOp { 4918588Sgblack@eecs.umich.edu 35: lbzu({{ Rt = Mem_ub; }}); 4928588Sgblack@eecs.umich.edu 41: lhzu({{ Rt = Mem_uh; }}); 4938588Sgblack@eecs.umich.edu 43: lhau({{ Rt = Mem_sh; }}); 4946691Stjones1@inf.ed.ac.uk 33: lwzu({{ Rt = Mem; }}); 4958588Sgblack@eecs.umich.edu 49: lfsu({{ Ft_sf = Mem_sf; }}); 4968588Sgblack@eecs.umich.edu 51: lfdu({{ Ft = Mem_df; }}); 4976691Stjones1@inf.ed.ac.uk } 4986691Stjones1@inf.ed.ac.uk 4996691Stjones1@inf.ed.ac.uk format StoreDispOp { 5008588Sgblack@eecs.umich.edu 38: stb({{ Mem_ub = Rs_ub; }}); 5018588Sgblack@eecs.umich.edu 44: sth({{ Mem_uh = Rs_uh; }}); 5026691Stjones1@inf.ed.ac.uk 36: stw({{ Mem = Rs; }}); 5038588Sgblack@eecs.umich.edu 52: stfs({{ Mem_sf = Fs_sf; }}); 5048588Sgblack@eecs.umich.edu 54: stfd({{ Mem_df = Fs; }}); 5056691Stjones1@inf.ed.ac.uk } 5066691Stjones1@inf.ed.ac.uk 5076691Stjones1@inf.ed.ac.uk format StoreDispUpdateOp { 5088588Sgblack@eecs.umich.edu 39: stbu({{ Mem_ub = Rs_ub; }}); 5098588Sgblack@eecs.umich.edu 45: sthu({{ Mem_uh = Rs_uh; }}); 5106691Stjones1@inf.ed.ac.uk 37: stwu({{ Mem = Rs; }}); 5118588Sgblack@eecs.umich.edu 53: stfsu({{ Mem_sf = Fs_sf; }}); 5128588Sgblack@eecs.umich.edu 55: stfdu({{ Mem_df = Fs; }}); 5136691Stjones1@inf.ed.ac.uk } 5146691Stjones1@inf.ed.ac.uk 51511877Sbrandon.potter@amd.com 17: IntOp::sc({{ xc->syscall(R0, &fault); }}, 5166691Stjones1@inf.ed.ac.uk [ IsSyscall, IsNonSpeculative, IsSerializeAfter ]); 5176691Stjones1@inf.ed.ac.uk 5186691Stjones1@inf.ed.ac.uk format FloatArithOp { 5196691Stjones1@inf.ed.ac.uk 59: decode A_XO { 5206691Stjones1@inf.ed.ac.uk 21: fadds({{ Ft = Fa + Fb; }}); 5216691Stjones1@inf.ed.ac.uk 20: fsubs({{ Ft = Fa - Fb; }}); 5226691Stjones1@inf.ed.ac.uk 25: fmuls({{ Ft = Fa * Fc; }}); 5236691Stjones1@inf.ed.ac.uk 18: fdivs({{ Ft = Fa / Fb; }}); 5246691Stjones1@inf.ed.ac.uk 29: fmadds({{ Ft = (Fa * Fc) + Fb; }}); 5256691Stjones1@inf.ed.ac.uk 28: fmsubs({{ Ft = (Fa * Fc) - Fb; }}); 5266691Stjones1@inf.ed.ac.uk 31: fnmadds({{ Ft = -((Fa * Fc) + Fb); }}); 5276691Stjones1@inf.ed.ac.uk 30: fnmsubs({{ Ft = -((Fa * Fc) - Fb); }}); 5286691Stjones1@inf.ed.ac.uk } 5296691Stjones1@inf.ed.ac.uk } 5306691Stjones1@inf.ed.ac.uk 5316691Stjones1@inf.ed.ac.uk 63: decode A_XO { 5326691Stjones1@inf.ed.ac.uk format FloatArithOp { 5336691Stjones1@inf.ed.ac.uk 21: fadd({{ Ft = Fa + Fb; }}); 5346691Stjones1@inf.ed.ac.uk 20: fsub({{ Ft = Fa - Fb; }}); 5356691Stjones1@inf.ed.ac.uk 25: fmul({{ Ft = Fa * Fc; }}); 5366691Stjones1@inf.ed.ac.uk 18: fdiv({{ Ft = Fa / Fb; }}); 5376691Stjones1@inf.ed.ac.uk 29: fmadd({{ Ft = (Fa * Fc) + Fb; }}); 5386691Stjones1@inf.ed.ac.uk 28: fmsub({{ Ft = (Fa * Fc) - Fb; }}); 5396691Stjones1@inf.ed.ac.uk 31: fnmadd({{ Ft = -((Fa * Fc) + Fb); }}); 5406691Stjones1@inf.ed.ac.uk 30: fnmsub({{ Ft = -((Fa * Fc) - Fb); }}); 5416691Stjones1@inf.ed.ac.uk } 5426691Stjones1@inf.ed.ac.uk 5436691Stjones1@inf.ed.ac.uk default: decode XO_XO { 5446691Stjones1@inf.ed.ac.uk format FloatConvertOp { 5458588Sgblack@eecs.umich.edu 12: frsp({{ Ft_sf = Fb; }}); 5468588Sgblack@eecs.umich.edu 15: fctiwz({{ Ft_sw = (int32_t)trunc(Fb); }}); 5476691Stjones1@inf.ed.ac.uk } 5486691Stjones1@inf.ed.ac.uk 5496691Stjones1@inf.ed.ac.uk format FloatOp { 5506691Stjones1@inf.ed.ac.uk 0: fcmpu({{ 5516691Stjones1@inf.ed.ac.uk uint32_t c = makeCRField(Fa, Fb); 5526691Stjones1@inf.ed.ac.uk Fpscr fpscr = FPSCR; 5536691Stjones1@inf.ed.ac.uk fpscr.fprf.fpcc = c; 5546691Stjones1@inf.ed.ac.uk FPSCR = fpscr; 5556691Stjones1@inf.ed.ac.uk CR = insertCRField(CR, BF, c); 5566691Stjones1@inf.ed.ac.uk }}); 5576691Stjones1@inf.ed.ac.uk } 5586691Stjones1@inf.ed.ac.uk 5596691Stjones1@inf.ed.ac.uk format FloatRCCheckOp { 5606691Stjones1@inf.ed.ac.uk 72: fmr({{ Ft = Fb; }}); 5616691Stjones1@inf.ed.ac.uk 264: fabs({{ 5628588Sgblack@eecs.umich.edu Ft_uq = Fb_uq; 5638588Sgblack@eecs.umich.edu Ft_uq = insertBits(Ft_uq, 63, 0); }}); 5646691Stjones1@inf.ed.ac.uk 136: fnabs({{ 5658588Sgblack@eecs.umich.edu Ft_uq = Fb_uq; 5668588Sgblack@eecs.umich.edu Ft_uq = insertBits(Ft_uq, 63, 1); }}); 5676691Stjones1@inf.ed.ac.uk 40: fneg({{ Ft = -Fb; }}); 5686691Stjones1@inf.ed.ac.uk 8: fcpsgn({{ 5698588Sgblack@eecs.umich.edu Ft_uq = Fb_uq; 5708588Sgblack@eecs.umich.edu Ft_uq = insertBits(Ft_uq, 63, Fa_uq<63:63>); 5716691Stjones1@inf.ed.ac.uk }}); 5728588Sgblack@eecs.umich.edu 583: mffs({{ Ft_uq = FPSCR; }}); 5736691Stjones1@inf.ed.ac.uk 134: mtfsfi({{ 5748917Sandreas.hansson@arm.com FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)), 5758917Sandreas.hansson@arm.com U_FIELD); 5766691Stjones1@inf.ed.ac.uk }}); 5776691Stjones1@inf.ed.ac.uk 711: mtfsf({{ 5788917Sandreas.hansson@arm.com if (L_FIELD == 1) { FPSCR = Fb_uq; } 5796691Stjones1@inf.ed.ac.uk else { 5806691Stjones1@inf.ed.ac.uk for (int i = 0; i < 8; ++i) { 5816691Stjones1@inf.ed.ac.uk if (bits(FLM, i) == 1) { 5828917Sandreas.hansson@arm.com int k = 4 * (i + (8 * (1 - W_FIELD))); 5836691Stjones1@inf.ed.ac.uk FPSCR = insertBits(FPSCR, k, k + 3, 5848588Sgblack@eecs.umich.edu bits(Fb_uq, k, k + 3)); 5856691Stjones1@inf.ed.ac.uk } 5866691Stjones1@inf.ed.ac.uk } 5876691Stjones1@inf.ed.ac.uk } 5886691Stjones1@inf.ed.ac.uk }}); 5896691Stjones1@inf.ed.ac.uk 70: mtfsb0({{ FPSCR = insertBits(FPSCR, 31 - BT, 0); }}); 5906691Stjones1@inf.ed.ac.uk 38: mtfsb1({{ FPSCR = insertBits(FPSCR, 31 - BT, 1); }}); 5916691Stjones1@inf.ed.ac.uk } 5926691Stjones1@inf.ed.ac.uk } 5936691Stjones1@inf.ed.ac.uk } 5946691Stjones1@inf.ed.ac.uk} 595