xref: /gem5/src/arch/power/isa/bitfields.isa

// -*- mode:c++ -*-

// Copyright (c) 2009 The University of Edinburgh
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// Authors: Timothy M. Jones

////////////////////////////////////////////////////////////////////
//
// Bitfield definitions.
//
// The endianness is the opposite to what's used here, so things
// are reversed sometimes. Not sure of a fix to this though...

// Opcode fields
def bitfield OPCODE        <31:26>;
def bitfield X_XO          <10:0>;
def bitfield XO_XO         <10:1>;
def bitfield A_XO          <5:1>;

// Register fields
def bitfield RA            <20:16>;
def bitfield RB            <15:11>;
def bitfield RS            <25:21>;
def bitfield RT            <25:21>;
def bitfield FRA           <20:16>;
def bitfield FRB           <15:11>;
def bitfield FRC           <10:6>;
def bitfield FRS           <25:21>;
def bitfield FRT           <25:21>;

// The record bit can be in two positions
// Used to enable setting of the condition register
def bitfield RC31          <0>;
def bitfield RC21          <10>;

// Used to enable setting of the overflow flags
def bitfield OE            <10>;

// SPR field for mtspr instruction
def bitfield SPR           <20:11>;

// FXM field for mtcrf instruction
def bitfield FXM           <19:12>;

// Branch fields
def bitfield LK            <0>;
def bitfield AA            <1>;

// Specifies a CR or FPSCR field
def bitfield BF            <25:23>;

// Fields for FPSCR manipulation instructions
def bitfield FLM           <24:17>;
def bitfield L             <25>;
def bitfield W             <16>;
// Named so to avoid conflicts with range.hh
def bitfield U_FIELD       <15:12>;

// Field for specifying a bit in CR or FPSCR
def bitfield BT            <25:21>;