interrupts.hh revision 8745:575cab0db076
15083Sgblack@eecs.umich.edu/* 25083Sgblack@eecs.umich.edu * Copyright (c) 2011 Google 35083Sgblack@eecs.umich.edu * All rights reserved. 45083Sgblack@eecs.umich.edu * 57087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 67087Snate@binkert.org * modification, are permitted provided that the following conditions are 77087Snate@binkert.org * met: redistributions of source code must retain the above copyright 87087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 97087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 107087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 117087Snate@binkert.org * documentation and/or other materials provided with the distribution; 127087Snate@binkert.org * neither the name of the copyright holders nor the names of its 135083Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147087Snate@binkert.org * this software without specific prior written permission. 157087Snate@binkert.org * 167087Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177087Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187087Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197087Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207087Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217087Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225083Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237087Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245083Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255083Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265083Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275083Sgblack@eecs.umich.edu * 285083Sgblack@eecs.umich.edu * Authors: Gabe Black 295083Sgblack@eecs.umich.edu */ 305083Sgblack@eecs.umich.edu 315083Sgblack@eecs.umich.edu#ifndef __ARCH_POWER_INTERRUPT_HH__ 325083Sgblack@eecs.umich.edu#define __ARCH_POWER_INTERRUPT_HH__ 335083Sgblack@eecs.umich.edu 345083Sgblack@eecs.umich.edu#include "base/misc.hh" 355083Sgblack@eecs.umich.edu#include "params/PowerInterrupts.hh" 365083Sgblack@eecs.umich.edu#include "sim/sim_object.hh" 375083Sgblack@eecs.umich.edu 385083Sgblack@eecs.umich.educlass ThreadContext; 395083Sgblack@eecs.umich.edu 405083Sgblack@eecs.umich.edunamespace PowerISA { 415083Sgblack@eecs.umich.edu 425083Sgblack@eecs.umich.educlass Interrupts : public SimObject 435083Sgblack@eecs.umich.edu{ 445083Sgblack@eecs.umich.edu private: 455083Sgblack@eecs.umich.edu BaseCPU * cpu; 465083Sgblack@eecs.umich.edu 475083Sgblack@eecs.umich.edu public: 485083Sgblack@eecs.umich.edu typedef PowerInterruptsParams Params; 495083Sgblack@eecs.umich.edu 505083Sgblack@eecs.umich.edu const Params * 515083Sgblack@eecs.umich.edu params() const 525083Sgblack@eecs.umich.edu { 535083Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 545083Sgblack@eecs.umich.edu } 555083Sgblack@eecs.umich.edu 565083Sgblack@eecs.umich.edu Interrupts(Params * p) : SimObject(p), cpu(NULL) 575083Sgblack@eecs.umich.edu {} 585083Sgblack@eecs.umich.edu 595083Sgblack@eecs.umich.edu void 605083Sgblack@eecs.umich.edu setCPU(BaseCPU * _cpu) 615083Sgblack@eecs.umich.edu { 625083Sgblack@eecs.umich.edu cpu = _cpu; 635083Sgblack@eecs.umich.edu } 645083Sgblack@eecs.umich.edu 656345Sgblack@eecs.umich.edu void 665083Sgblack@eecs.umich.edu post(int int_num, int index) 675083Sgblack@eecs.umich.edu { 685083Sgblack@eecs.umich.edu panic("Interrupts::post not implemented.\n"); 695083Sgblack@eecs.umich.edu } 705083Sgblack@eecs.umich.edu 716345Sgblack@eecs.umich.edu void 725083Sgblack@eecs.umich.edu clear(int int_num, int index) 735083Sgblack@eecs.umich.edu { 745083Sgblack@eecs.umich.edu panic("Interrupts::clear not implemented.\n"); 755083Sgblack@eecs.umich.edu } 765083Sgblack@eecs.umich.edu 775083Sgblack@eecs.umich.edu void 785083Sgblack@eecs.umich.edu clearAll() 795083Sgblack@eecs.umich.edu { 805083Sgblack@eecs.umich.edu panic("Interrupts::clearAll not implemented.\n"); 815083Sgblack@eecs.umich.edu } 825083Sgblack@eecs.umich.edu 835083Sgblack@eecs.umich.edu bool 845083Sgblack@eecs.umich.edu checkInterrupts(ThreadContext *tc) const 855083Sgblack@eecs.umich.edu { 865083Sgblack@eecs.umich.edu panic("Interrupts::checkInterrupts not implemented.\n"); 87 } 88 89 Fault 90 getInterrupt(ThreadContext *tc) 91 { 92 panic("Interrupts::getInterrupt not implemented.\n"); 93 } 94 95 void 96 updateIntrInfo(ThreadContext *tc) 97 { 98 panic("Interrupts::updateIntrInfo not implemented.\n"); 99 } 100}; 101 102} // namespace PowerISA 103 104#endif // __ARCH_POWER_INTERRUPT_HH__ 105 106