interrupts.hh revision 8745
11689SN/A/*
27783SGiacomo.Gabrielli@arm.com * Copyright (c) 2011 Google
37783SGiacomo.Gabrielli@arm.com * All rights reserved.
47783SGiacomo.Gabrielli@arm.com *
57783SGiacomo.Gabrielli@arm.com * Redistribution and use in source and binary forms, with or without
67783SGiacomo.Gabrielli@arm.com * modification, are permitted provided that the following conditions are
77783SGiacomo.Gabrielli@arm.com * met: redistributions of source code must retain the above copyright
87783SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer;
97783SGiacomo.Gabrielli@arm.com * redistributions in binary form must reproduce the above copyright
107783SGiacomo.Gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the
117783SGiacomo.Gabrielli@arm.com * documentation and/or other materials provided with the distribution;
127783SGiacomo.Gabrielli@arm.com * neither the name of the copyright holders nor the names of its
137783SGiacomo.Gabrielli@arm.com * contributors may be used to endorse or promote products derived from
142316SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
271689SN/A *
281689SN/A * Authors: Gabe Black
291689SN/A */
301689SN/A
311689SN/A#ifndef __ARCH_POWER_INTERRUPT_HH__
321689SN/A#define __ARCH_POWER_INTERRUPT_HH__
331689SN/A
341689SN/A#include "base/misc.hh"
351689SN/A#include "params/PowerInterrupts.hh"
361689SN/A#include "sim/sim_object.hh"
371689SN/A
381689SN/Aclass ThreadContext;
392665SN/A
402665SN/Anamespace PowerISA {
411689SN/A
421061SN/Aclass Interrupts : public SimObject
435953Ssaidi@eecs.umich.edu{
445596Sgblack@eecs.umich.edu  private:
451061SN/A    BaseCPU * cpu;
461061SN/A
475596Sgblack@eecs.umich.edu  public:
487720Sgblack@eecs.umich.edu    typedef PowerInterruptsParams Params;
495596Sgblack@eecs.umich.edu
507720Sgblack@eecs.umich.edu    const Params *
514637SN/A    params() const
524637SN/A    {
534637SN/A        return dynamic_cast<const Params *>(_params);
544637SN/A    }
554637SN/A
565596Sgblack@eecs.umich.edu    Interrupts(Params * p) : SimObject(p), cpu(NULL)
577720Sgblack@eecs.umich.edu    {}
585596Sgblack@eecs.umich.edu
597720Sgblack@eecs.umich.edu    void
601061SN/A    setCPU(BaseCPU * _cpu)
612292SN/A    {
621061SN/A        cpu = _cpu;
631061SN/A    }
641061SN/A
655596Sgblack@eecs.umich.edu    void
661464SN/A    post(int int_num, int index)
671061SN/A    {
682292SN/A        panic("Interrupts::post not implemented.\n");
692292SN/A    }
702292SN/A
712292SN/A    void
722292SN/A    clear(int int_num, int index)
735596Sgblack@eecs.umich.edu    {
742292SN/A        panic("Interrupts::clear not implemented.\n");
751464SN/A    }
761464SN/A
771464SN/A    void
782292SN/A    clearAll()
793782SN/A    {
801464SN/A        panic("Interrupts::clearAll not implemented.\n");
811464SN/A    }
822292SN/A
833782SN/A    bool
842292SN/A    checkInterrupts(ThreadContext *tc) const
851464SN/A    {
867783SGiacomo.Gabrielli@arm.com        panic("Interrupts::checkInterrupts not implemented.\n");
877783SGiacomo.Gabrielli@arm.com    }
881061SN/A
891061SN/A    Fault
902292SN/A    getInterrupt(ThreadContext *tc)
912292SN/A    {
925596Sgblack@eecs.umich.edu        panic("Interrupts::getInterrupt not implemented.\n");
932292SN/A    }
942348SN/A
952680SN/A    void
962348SN/A    updateIntrInfo(ThreadContext *tc)
972680SN/A    {
982292SN/A        panic("Interrupts::updateIntrInfo not implemented.\n");
992292SN/A    }
1002292SN/A};
1012292SN/A
1022292SN/A} // namespace PowerISA
1032292SN/A
1042292SN/A#endif // __ARCH_POWER_INTERRUPT_HH__
1052292SN/A
1062292SN/A