static_inst.cc revision 9920 
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281142Shsul@eecs.umich.edu *
291142Shsul@eecs.umich.edu * Authors: Timothy M. Jones
301142Shsul@eecs.umich.edu */
311175Sbinkertn@umich.edu
321142Shsul@eecs.umich.edu#include "arch/power/insts/static_inst.hh"
331142Shsul@eecs.umich.edu#include "cpu/reg_class.hh"
341142Shsul@eecs.umich.edu
351142Shsul@eecs.umich.eduusing namespace PowerISA;
361142Shsul@eecs.umich.edu
371142Shsul@eecs.umich.eduvoid
381142Shsul@eecs.umich.eduPowerStaticInst::printReg(std::ostream &os, int reg) const
391142Shsul@eecs.umich.edu{
401177Sbinkertn@umich.edu    RegIndex rel_reg;
411142Shsul@eecs.umich.edu
421142Shsul@eecs.umich.edu    switch (regIdxToClass(reg, &rel_reg)) {
431142Shsul@eecs.umich.edu      case IntRegClass:
441142Shsul@eecs.umich.edu        ccprintf(os, "r%d", rel_reg);
451142Shsul@eecs.umich.edu        break;
461142Shsul@eecs.umich.edu      case FloatRegClass:
471142Shsul@eecs.umich.edu        ccprintf(os, "f%d", rel_reg);
48        break;
49      case MiscRegClass:
50        switch (rel_reg) {
51          case 0: ccprintf(os, "cr"); break;
52          case 1: ccprintf(os, "xer"); break;
53          case 2: ccprintf(os, "lr"); break;
54          case 3: ccprintf(os, "ctr"); break;
55          default: ccprintf(os, "unknown_reg");
56            break;
57        }
58      case CCRegClass:
59        panic("printReg: POWER does not implement CCRegClass\n");
60    }
61}
62
63std::string
64PowerStaticInst::generateDisassembly(Addr pc,
65                                       const SymbolTable *symtab) const
66{
67    std::stringstream ss;
68
69    ccprintf(ss, "%-10s ", mnemonic);
70
71    return ss.str();
72}
73