utility.hh revision 8229:78bf55f23338 
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 *          Steve Reinhardt
31 *          Korey Sewell
32 */
33
34#ifndef __ARCH_MIPS_UTILITY_HH__
35#define __ARCH_MIPS_UTILITY_HH__
36#include "arch/mips/isa_traits.hh"
37#include "arch/mips/types.hh"
38#include "base/misc.hh"
39#include "base/types.hh"
40#include "config/full_system.hh"
41#include "cpu/static_inst.hh"
42#include "cpu/thread_context.hh"
43
44class ThreadContext;
45
46namespace MipsISA {
47
48inline PCState
49buildRetPC(const PCState &curPC, const PCState &callPC)
50{
51    PCState ret = callPC;
52    ret.advance();
53    ret.pc(curPC.npc());
54    return ret;
55}
56
57uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
58
59////////////////////////////////////////////////////////////////////////
60//
61// Floating Point Utility Functions
62//
63uint64_t fpConvert(ConvertType cvt_type, double fp_val);
64double roundFP(double val, int digits);
65double truncFP(double val);
66
67bool getCondCode(uint32_t fcsr, int cc);
68uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
69uint32_t genInvalidVector(uint32_t fcsr);
70
71bool isNan(void *val_ptr, int size);
72bool isQnan(void *val_ptr, int size);
73bool isSnan(void *val_ptr, int size);
74
75static inline bool
76inUserMode(ThreadContext *tc)
77{
78    MiscReg Stat = tc->readMiscReg(MISCREG_STATUS);
79    MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG);
80
81    if ((Stat & 0x10000006) == 0 &&  // EXL, ERL or CU0 set, CP0 accessible
82        (Dbg & 0x40000000) == 0 &&   // DM bit set, CP0 accessible
83        (Stat & 0x00000018) != 0) {  // KSU = 0, kernel mode is base mode
84        // Unable to use Status_CU0, etc directly, using bitfields & masks
85        return true;
86    } else {
87        return false;
88    }
89}
90
91template <class CPU>
92void zeroRegisters(CPU *cpu);
93
94////////////////////////////////////////////////////////////////////////
95//
96//  Translation stuff
97//
98inline Addr
99TruncPage(Addr addr)
100{ return addr & ~(PageBytes - 1); }
101
102inline Addr
103RoundPage(Addr addr)
104{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
105
106////////////////////////////////////////////////////////////////////////
107//
108// CPU Utility
109//
110void startupCPU(ThreadContext *tc, int cpuId);
111
112void copyRegs(ThreadContext *src, ThreadContext *dest);
113void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
114
115void skipFunction(ThreadContext *tc);
116
117inline void
118advancePC(PCState &pc, const StaticInstPtr inst)
119{
120    pc.advance();
121}
122
123};
124
125
126#endif
127