utility.hh revision 4836:404719c5ed86
17861Sgblack@eecs.umich.edu/* 28332Snate@binkert.org * Copyright (c) 2003-2005 The Regents of The University of Michigan 37861Sgblack@eecs.umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 47861Sgblack@eecs.umich.edu * All rights reserved. 57861Sgblack@eecs.umich.edu * 67861Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 77861Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 87861Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 97861Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 107861Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 117861Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 127861Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 137861Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 147861Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 157861Sgblack@eecs.umich.edu * this software without specific prior written permission. 167861Sgblack@eecs.umich.edu * 177861Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 187861Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 197861Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 207861Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 217861Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 227861Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 237861Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 247861Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 257861Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 267861Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 277861Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 287861Sgblack@eecs.umich.edu * 297861Sgblack@eecs.umich.edu * Authors: Nathan Binkert 307861Sgblack@eecs.umich.edu * Steve Reinhardt 317861Sgblack@eecs.umich.edu * Korey Sewell 327861Sgblack@eecs.umich.edu */ 337861Sgblack@eecs.umich.edu 347861Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_UTILITY_HH__ 357861Sgblack@eecs.umich.edu#define __ARCH_MIPS_UTILITY_HH__ 367861Sgblack@eecs.umich.edu 377861Sgblack@eecs.umich.edu#include "arch/mips/types.hh" 387861Sgblack@eecs.umich.edu#include "arch/mips/isa_traits.hh" 397861Sgblack@eecs.umich.edu#include "base/misc.hh" 407861Sgblack@eecs.umich.edu#include "config/full_system.hh" 417861Sgblack@eecs.umich.edu//XXX This is needed for size_t. We should use something other than size_t 427861Sgblack@eecs.umich.edu//#include "kern/linux/linux.hh" 437861Sgblack@eecs.umich.edu#include "sim/host.hh" 447861Sgblack@eecs.umich.edu 457861Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 467861Sgblack@eecs.umich.edu 477861Sgblack@eecs.umich.educlass ThreadContext; 487861Sgblack@eecs.umich.edu 497861Sgblack@eecs.umich.edunamespace MipsISA { 507861Sgblack@eecs.umich.edu 517861Sgblack@eecs.umich.edu uint64_t getArgument(ThreadContext *tc, bool fp) { 527861Sgblack@eecs.umich.edu panic("getArgument() not implemented for MIPS\n"); 537861Sgblack@eecs.umich.edu } 547861Sgblack@eecs.umich.edu 557861Sgblack@eecs.umich.edu //Floating Point Utility Functions 567861Sgblack@eecs.umich.edu uint64_t fpConvert(ConvertType cvt_type, double fp_val); 577861Sgblack@eecs.umich.edu double roundFP(double val, int digits); 587861Sgblack@eecs.umich.edu double truncFP(double val); 597861Sgblack@eecs.umich.edu 607861Sgblack@eecs.umich.edu bool getCondCode(uint32_t fcsr, int cc); 617861Sgblack@eecs.umich.edu uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 627861Sgblack@eecs.umich.edu uint32_t genInvalidVector(uint32_t fcsr); 6312088Sspwilson2@wisc.edu 647861Sgblack@eecs.umich.edu bool isNan(void *val_ptr, int size); 657861Sgblack@eecs.umich.edu bool isQnan(void *val_ptr, int size); 667861Sgblack@eecs.umich.edu bool isSnan(void *val_ptr, int size); 677861Sgblack@eecs.umich.edu 687861Sgblack@eecs.umich.edu /** 697861Sgblack@eecs.umich.edu * Function to insure ISA semantics about 0 registers. 707861Sgblack@eecs.umich.edu * @param tc The thread context. 717861Sgblack@eecs.umich.edu */ 727861Sgblack@eecs.umich.edu template <class TC> 737861Sgblack@eecs.umich.edu void zeroRegisters(TC *tc); 747861Sgblack@eecs.umich.edu 757861Sgblack@eecs.umich.edu void startupCPU(ThreadContext *tc, int cpuId); 767861Sgblack@eecs.umich.edu 777861Sgblack@eecs.umich.edu // Instruction address compression hooks 787861Sgblack@eecs.umich.edu static inline Addr realPCToFetchPC(const Addr &addr) { 797861Sgblack@eecs.umich.edu return addr; 807861Sgblack@eecs.umich.edu } 817861Sgblack@eecs.umich.edu 827861Sgblack@eecs.umich.edu static inline Addr fetchPCToRealPC(const Addr &addr) { 837861Sgblack@eecs.umich.edu return addr; 847861Sgblack@eecs.umich.edu } 857861Sgblack@eecs.umich.edu 867861Sgblack@eecs.umich.edu // the size of "fetched" instructions (not necessarily the size 877861Sgblack@eecs.umich.edu // of real instructions for PISA) 887861Sgblack@eecs.umich.edu static inline size_t fetchInstSize() { 897861Sgblack@eecs.umich.edu return sizeof(MachInst); 907861Sgblack@eecs.umich.edu } 917861Sgblack@eecs.umich.edu 927861Sgblack@eecs.umich.edu static inline MachInst makeRegisterCopy(int dest, int src) { 937861Sgblack@eecs.umich.edu panic("makeRegisterCopy not implemented"); 947861Sgblack@eecs.umich.edu return 0; 957861Sgblack@eecs.umich.edu } 967861Sgblack@eecs.umich.edu 977942SAli.Saidi@ARM.com static inline ExtMachInst 987942SAli.Saidi@ARM.com makeExtMI(MachInst inst, ThreadContext * xc) { 997942SAli.Saidi@ARM.com#if FULL_SYSTEM 1007942SAli.Saidi@ARM.com ExtMachInst ext_inst = inst; 1017942SAli.Saidi@ARM.com if (xc->readPC() && 0x1) 1027942SAli.Saidi@ARM.com return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32); 1037942SAli.Saidi@ARM.com else 1047942SAli.Saidi@ARM.com return ext_inst; 1057942SAli.Saidi@ARM.com#else 1067942SAli.Saidi@ARM.com return ExtMachInst(inst); 1077942SAli.Saidi@ARM.com#endif 10811168Sandreas.hansson@arm.com } 1097942SAli.Saidi@ARM.com}; 1107942SAli.Saidi@ARM.com 1117942SAli.Saidi@ARM.com 11211169Sandreas.hansson@arm.com#endif 1139048SAli.Saidi@ARM.com