utility.hh revision 3120
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 32#ifndef __ARCH_MIPS_UTILITY_HH__ 33#define __ARCH_MIPS_UTILITY_HH__ 34 35#include "arch/mips/types.hh" 36#include "base/misc.hh" 37#include "config/full_system.hh" 38#include "cpu/thread_context.hh" 39//XXX This is needed for size_t. We should use something other than size_t 40//#include "kern/linux/linux.hh" 41#include "sim/host.hh" 42 43class ThreadContext; 44 45namespace MipsISA { 46 47 //Floating Point Utility Functions 48 uint64_t fpConvert(ConvertType cvt_type, double fp_val); 49 double roundFP(double val, int digits); 50 double truncFP(double val); 51 52 bool getCondCode(uint32_t fcsr, int cc); 53 uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 54 uint32_t genInvalidVector(uint32_t fcsr); 55 56 bool isNan(void *val_ptr, int size); 57 bool isQnan(void *val_ptr, int size); 58 bool isSnan(void *val_ptr, int size); 59 60 /** 61 * Function to insure ISA semantics about 0 registers. 62 * @param tc The thread context. 63 */ 64 template <class TC> 65 void zeroRegisters(TC *tc); 66 67 void copyRegs(ThreadContext *src, ThreadContext *dest); 68 69 // Instruction address compression hooks 70 static inline Addr realPCToFetchPC(const Addr &addr) { 71 return addr; 72 } 73 74 static inline Addr fetchPCToRealPC(const Addr &addr) { 75 return addr; 76 } 77 78 // the size of "fetched" instructions (not necessarily the size 79 // of real instructions for PISA) 80 static inline size_t fetchInstSize() { 81 return sizeof(MachInst); 82 } 83 84 static inline MachInst makeRegisterCopy(int dest, int src) { 85 panic("makeRegisterCopy not implemented"); 86 return 0; 87 } 88 89 static inline ExtMachInst 90 makeExtMI(MachInst inst, ThreadContext * xc) { 91#if FULL_SYSTEM 92 ExtMachInst ext_inst = inst; 93 if (xc->readPC() && 0x1) 94 return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32); 95 else 96 return ext_inst; 97#else 98 return ExtMachInst(inst); 99#endif 100 } 101}; 102 103 104#endif 105