utility.hh revision 8229
12447SN/A/* 25254Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 45254Sksewell@umich.edu * All rights reserved. 52447SN/A * 65254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 75254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 85254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 95254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 105254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 115254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 125254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 135254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 145254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 155254Sksewell@umich.edu * this software without specific prior written permission. 162447SN/A * 175254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282632Sstever@eecs.umich.edu * 295254Sksewell@umich.edu * Authors: Nathan Binkert 305254Sksewell@umich.edu * Steve Reinhardt 315254Sksewell@umich.edu * Korey Sewell 322447SN/A */ 332447SN/A 342447SN/A#ifndef __ARCH_MIPS_UTILITY_HH__ 352447SN/A#define __ARCH_MIPS_UTILITY_HH__ 368229Snate@binkert.org#include "arch/mips/isa_traits.hh" 372597SN/A#include "arch/mips/types.hh" 382597SN/A#include "base/misc.hh" 396216Snate@binkert.org#include "base/types.hh" 402980Sgblack@eecs.umich.edu#include "config/full_system.hh" 417720Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 424661Sksewell@umich.edu#include "cpu/thread_context.hh" 434661Sksewell@umich.edu 442980Sgblack@eecs.umich.educlass ThreadContext; 452980Sgblack@eecs.umich.edu 462597SN/Anamespace MipsISA { 472597SN/A 487720Sgblack@eecs.umich.eduinline PCState 497720Sgblack@eecs.umich.edubuildRetPC(const PCState &curPC, const PCState &callPC) 507720Sgblack@eecs.umich.edu{ 517720Sgblack@eecs.umich.edu PCState ret = callPC; 527720Sgblack@eecs.umich.edu ret.advance(); 537720Sgblack@eecs.umich.edu ret.pc(curPC.npc()); 547720Sgblack@eecs.umich.edu return ret; 557720Sgblack@eecs.umich.edu} 567720Sgblack@eecs.umich.edu 577707Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 584826Ssaidi@eecs.umich.edu 596378Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////// 606378Sgblack@eecs.umich.edu// 616378Sgblack@eecs.umich.edu// Floating Point Utility Functions 626378Sgblack@eecs.umich.edu// 636378Sgblack@eecs.umich.eduuint64_t fpConvert(ConvertType cvt_type, double fp_val); 646378Sgblack@eecs.umich.edudouble roundFP(double val, int digits); 656378Sgblack@eecs.umich.edudouble truncFP(double val); 662686Sksewell@umich.edu 676378Sgblack@eecs.umich.edubool getCondCode(uint32_t fcsr, int cc); 686378Sgblack@eecs.umich.eduuint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 696378Sgblack@eecs.umich.eduuint32_t genInvalidVector(uint32_t fcsr); 702686Sksewell@umich.edu 716378Sgblack@eecs.umich.edubool isNan(void *val_ptr, int size); 726378Sgblack@eecs.umich.edubool isQnan(void *val_ptr, int size); 736378Sgblack@eecs.umich.edubool isSnan(void *val_ptr, int size); 742972Sgblack@eecs.umich.edu 756378Sgblack@eecs.umich.edustatic inline bool 766378Sgblack@eecs.umich.eduinUserMode(ThreadContext *tc) 776378Sgblack@eecs.umich.edu{ 786383Sgblack@eecs.umich.edu MiscReg Stat = tc->readMiscReg(MISCREG_STATUS); 796383Sgblack@eecs.umich.edu MiscReg Dbg = tc->readMiscReg(MISCREG_DEBUG); 805222Sksewell@umich.edu 816378Sgblack@eecs.umich.edu if ((Stat & 0x10000006) == 0 && // EXL, ERL or CU0 set, CP0 accessible 826378Sgblack@eecs.umich.edu (Dbg & 0x40000000) == 0 && // DM bit set, CP0 accessible 836378Sgblack@eecs.umich.edu (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode 846378Sgblack@eecs.umich.edu // Unable to use Status_CU0, etc directly, using bitfields & masks 856378Sgblack@eecs.umich.edu return true; 866378Sgblack@eecs.umich.edu } else { 876378Sgblack@eecs.umich.edu return false; 885222Sksewell@umich.edu } 896378Sgblack@eecs.umich.edu} 904661Sksewell@umich.edu 916378Sgblack@eecs.umich.edutemplate <class CPU> 926378Sgblack@eecs.umich.eduvoid zeroRegisters(CPU *cpu); 935222Sksewell@umich.edu 946378Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////// 956378Sgblack@eecs.umich.edu// 966378Sgblack@eecs.umich.edu// Translation stuff 976378Sgblack@eecs.umich.edu// 986378Sgblack@eecs.umich.eduinline Addr 996378Sgblack@eecs.umich.eduTruncPage(Addr addr) 1006378Sgblack@eecs.umich.edu{ return addr & ~(PageBytes - 1); } 1015222Sksewell@umich.edu 1026378Sgblack@eecs.umich.eduinline Addr 1036378Sgblack@eecs.umich.eduRoundPage(Addr addr) 1046378Sgblack@eecs.umich.edu{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 1055222Sksewell@umich.edu 1066378Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////// 1076378Sgblack@eecs.umich.edu// 1086378Sgblack@eecs.umich.edu// CPU Utility 1096378Sgblack@eecs.umich.edu// 1106378Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId); 1116329Sgblack@eecs.umich.edu 1126378Sgblack@eecs.umich.eduvoid copyRegs(ThreadContext *src, ThreadContext *dest); 1136378Sgblack@eecs.umich.eduvoid copyMiscRegs(ThreadContext *src, ThreadContext *dest); 1146378Sgblack@eecs.umich.edu 1157693SAli.Saidi@ARM.comvoid skipFunction(ThreadContext *tc); 1167693SAli.Saidi@ARM.com 1177720Sgblack@eecs.umich.eduinline void 1187720Sgblack@eecs.umich.eduadvancePC(PCState &pc, const StaticInstPtr inst) 1197720Sgblack@eecs.umich.edu{ 1207720Sgblack@eecs.umich.edu pc.advance(); 1217720Sgblack@eecs.umich.edu} 1227720Sgblack@eecs.umich.edu 1232597SN/A}; 1242447SN/A 1252686Sksewell@umich.edu 1262447SN/A#endif 127