utility.hh revision 5222
12447SN/A/* 25222Sksewell@umich.edu * Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved 32447SN/A * 45222Sksewell@umich.edu * This software is part of the M5 simulator. 52447SN/A * 65222Sksewell@umich.edu * THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING 75222Sksewell@umich.edu * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING 85222Sksewell@umich.edu * TO THESE TERMS AND CONDITIONS. 92632Sstever@eecs.umich.edu * 105222Sksewell@umich.edu * Permission is granted to use, copy, create derivative works and 115222Sksewell@umich.edu * distribute this software and such derivative works for any purpose, 125222Sksewell@umich.edu * so long as (1) the copyright notice above, this grant of permission, 135222Sksewell@umich.edu * and the disclaimer below appear in all copies and derivative works 145222Sksewell@umich.edu * made, (2) the copyright notice above is augmented as appropriate to 155222Sksewell@umich.edu * reflect the addition of any new copyrightable work in a derivative 165222Sksewell@umich.edu * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3) 175222Sksewell@umich.edu * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any 185222Sksewell@umich.edu * advertising or publicity pertaining to the use or distribution of 195222Sksewell@umich.edu * this software without specific, written prior authorization. 205222Sksewell@umich.edu * 215222Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND 225222Sksewell@umich.edu * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR 235222Sksewell@umich.edu * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 245222Sksewell@umich.edu * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND 255222Sksewell@umich.edu * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE. 265222Sksewell@umich.edu * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT, 275222Sksewell@umich.edu * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF 285222Sksewell@umich.edu * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT, 295222Sksewell@umich.edu * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY 305222Sksewell@umich.edu * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR 315222Sksewell@umich.edu * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE 325222Sksewell@umich.edu * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE. 335222Sksewell@umich.edu * 345222Sksewell@umich.edu * Authors: Korey L. Sewell 352447SN/A */ 362447SN/A 372447SN/A#ifndef __ARCH_MIPS_UTILITY_HH__ 382447SN/A#define __ARCH_MIPS_UTILITY_HH__ 395222Sksewell@umich.edu#include "config/full_system.hh" 402597SN/A#include "arch/mips/types.hh" 414661Sksewell@umich.edu#include "arch/mips/isa_traits.hh" 422597SN/A#include "base/misc.hh" 432980Sgblack@eecs.umich.edu#include "config/full_system.hh" 442972Sgblack@eecs.umich.edu//XXX This is needed for size_t. We should use something other than size_t 452980Sgblack@eecs.umich.edu//#include "kern/linux/linux.hh" 462597SN/A#include "sim/host.hh" 472597SN/A 484661Sksewell@umich.edu#include "cpu/thread_context.hh" 494661Sksewell@umich.edu 502980Sgblack@eecs.umich.educlass ThreadContext; 512980Sgblack@eecs.umich.edu 522597SN/Anamespace MipsISA { 532597SN/A 545222Sksewell@umich.edu uint64_t getArgument(ThreadContext *tc, int number, bool fp); 554826Ssaidi@eecs.umich.edu 562686Sksewell@umich.edu //Floating Point Utility Functions 572686Sksewell@umich.edu uint64_t fpConvert(ConvertType cvt_type, double fp_val); 582686Sksewell@umich.edu double roundFP(double val, int digits); 592686Sksewell@umich.edu double truncFP(double val); 602686Sksewell@umich.edu 612686Sksewell@umich.edu bool getCondCode(uint32_t fcsr, int cc); 622686Sksewell@umich.edu uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 632686Sksewell@umich.edu uint32_t genInvalidVector(uint32_t fcsr); 642686Sksewell@umich.edu 652686Sksewell@umich.edu bool isNan(void *val_ptr, int size); 662686Sksewell@umich.edu bool isQnan(void *val_ptr, int size); 672686Sksewell@umich.edu bool isSnan(void *val_ptr, int size); 682972Sgblack@eecs.umich.edu 695222Sksewell@umich.edu void startupCPU(ThreadContext *tc, int cpuId); 702972Sgblack@eecs.umich.edu 715222Sksewell@umich.edu static inline bool 725222Sksewell@umich.edu inUserMode(ThreadContext *tc) 735222Sksewell@umich.edu { 745222Sksewell@umich.edu MiscReg Stat = tc->readMiscReg(MipsISA::Status); 755222Sksewell@umich.edu MiscReg Dbg = tc->readMiscReg(MipsISA::Debug); 765222Sksewell@umich.edu 775222Sksewell@umich.edu if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible 785222Sksewell@umich.edu && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible 795222Sksewell@umich.edu && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode 805222Sksewell@umich.edu // Unable to use Status_CU0, etc directly, using bitfields & masks 815222Sksewell@umich.edu return true; 825222Sksewell@umich.edu } else { 835222Sksewell@umich.edu return false; 845222Sksewell@umich.edu } 855222Sksewell@umich.edu } 864661Sksewell@umich.edu 872972Sgblack@eecs.umich.edu // Instruction address compression hooks 882972Sgblack@eecs.umich.edu static inline Addr realPCToFetchPC(const Addr &addr) { 892972Sgblack@eecs.umich.edu return addr; 902972Sgblack@eecs.umich.edu } 912972Sgblack@eecs.umich.edu 922972Sgblack@eecs.umich.edu static inline Addr fetchPCToRealPC(const Addr &addr) { 932972Sgblack@eecs.umich.edu return addr; 942972Sgblack@eecs.umich.edu } 952972Sgblack@eecs.umich.edu 962972Sgblack@eecs.umich.edu // the size of "fetched" instructions (not necessarily the size 972972Sgblack@eecs.umich.edu // of real instructions for PISA) 982972Sgblack@eecs.umich.edu static inline size_t fetchInstSize() { 992972Sgblack@eecs.umich.edu return sizeof(MachInst); 1002972Sgblack@eecs.umich.edu } 1012972Sgblack@eecs.umich.edu 1022972Sgblack@eecs.umich.edu static inline MachInst makeRegisterCopy(int dest, int src) { 1032972Sgblack@eecs.umich.edu panic("makeRegisterCopy not implemented"); 1042972Sgblack@eecs.umich.edu return 0; 1052972Sgblack@eecs.umich.edu } 1063120Sgblack@eecs.umich.edu 1075222Sksewell@umich.edu static inline int flattenFloatIndex(ThreadContext * tc, int reg) 1085222Sksewell@umich.edu { 1095222Sksewell@umich.edu return reg; 1104194Ssaidi@eecs.umich.edu } 1115222Sksewell@umich.edu 1125222Sksewell@umich.edu int flattenIntIndex(ThreadContext * tc, int reg); 1135222Sksewell@umich.edu 1145222Sksewell@umich.edu void copyRegs(ThreadContext *src, ThreadContext *dest); 1155222Sksewell@umich.edu 1165222Sksewell@umich.edu void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 1175222Sksewell@umich.edu 1185222Sksewell@umich.edu 1195222Sksewell@umich.edu template <class CPU> 1205222Sksewell@umich.edu void zeroRegisters(CPU *cpu); 1215222Sksewell@umich.edu 1225222Sksewell@umich.edu //////////////////////////////////////////////////////////////////////// 1235222Sksewell@umich.edu // 1245222Sksewell@umich.edu // Translation stuff 1255222Sksewell@umich.edu // 1265222Sksewell@umich.edu 1275222Sksewell@umich.edu inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 1285222Sksewell@umich.edu 1295222Sksewell@umich.edu // User Virtual 1305222Sksewell@umich.edu inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 1315222Sksewell@umich.edu 1325222Sksewell@umich.edu inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; } 1335222Sksewell@umich.edu 1345222Sksewell@umich.edu inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; } 1355222Sksewell@umich.edu 1365222Sksewell@umich.edu inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; } 1375222Sksewell@umich.edu 1385222Sksewell@umich.edu inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; } 1395222Sksewell@umich.edu 1405222Sksewell@umich.edu inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; } 1415222Sksewell@umich.edu 1425222Sksewell@umich.edu inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; } 1435222Sksewell@umich.edu 1445222Sksewell@umich.edu inline Addr 1455222Sksewell@umich.edu TruncPage(Addr addr) 1465222Sksewell@umich.edu { return addr & ~(PageBytes - 1); } 1475222Sksewell@umich.edu 1485222Sksewell@umich.edu inline Addr 1495222Sksewell@umich.edu RoundPage(Addr addr) 1505222Sksewell@umich.edu { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 1515222Sksewell@umich.edu 1525222Sksewell@umich.edu void initCPU(ThreadContext *tc, int cpuId); 1535222Sksewell@umich.edu void initIPRs(ThreadContext *tc, int cpuId); 1545222Sksewell@umich.edu 1555222Sksewell@umich.edu /** 1565222Sksewell@umich.edu * Function to check for and process any interrupts. 1575222Sksewell@umich.edu * @param tc The thread context. 1585222Sksewell@umich.edu */ 1595222Sksewell@umich.edu template <class TC> 1605222Sksewell@umich.edu void processInterrupts(TC *tc); 1615222Sksewell@umich.edu 1622597SN/A}; 1632447SN/A 1642686Sksewell@umich.edu 1652447SN/A#endif 166