utility.hh revision 4826
17405SAli.Saidi@ARM.com/* 212667Schuan.zhu@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 37405SAli.Saidi@ARM.com * Copyright (c) 2007 MIPS Technologies, Inc. 47405SAli.Saidi@ARM.com * All rights reserved. 57405SAli.Saidi@ARM.com * 67405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 77405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 87405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 97405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 107405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 117405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 127405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 137405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 147405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 157405SAli.Saidi@ARM.com * this software without specific prior written permission. 167405SAli.Saidi@ARM.com * 177405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 187405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 197405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 207405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 217405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 227405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 237405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 247405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 257405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 267405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 277405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 287405SAli.Saidi@ARM.com * 297405SAli.Saidi@ARM.com * Authors: Nathan Binkert 307405SAli.Saidi@ARM.com * Steve Reinhardt 317405SAli.Saidi@ARM.com * Korey Sewell 327405SAli.Saidi@ARM.com */ 337405SAli.Saidi@ARM.com 347405SAli.Saidi@ARM.com#ifndef __ARCH_MIPS_UTILITY_HH__ 357405SAli.Saidi@ARM.com#define __ARCH_MIPS_UTILITY_HH__ 367405SAli.Saidi@ARM.com 377405SAli.Saidi@ARM.com#include "arch/mips/types.hh" 387405SAli.Saidi@ARM.com#include "arch/mips/isa_traits.hh" 397405SAli.Saidi@ARM.com#include "base/misc.hh" 407405SAli.Saidi@ARM.com#include "config/full_system.hh" 417405SAli.Saidi@ARM.com//XXX This is needed for size_t. We should use something other than size_t 4210461SAndreas.Sandberg@ARM.com//#include "kern/linux/linux.hh" 439050Schander.sudanthi@arm.com#include "sim/host.hh" 4412406Sgabeblack@google.com 4512605Sgiacomo.travaglini@arm.com#include "cpu/thread_context.hh" 4611793Sbrandon.potter@amd.com 478887Sgeoffrey.blake@arm.comclass ThreadContext; 488232Snate@binkert.org 498232Snate@binkert.orgnamespace MipsISA { 5010844Sandreas.sandberg@arm.com 519384SAndreas.Sandberg@arm.com uint64_t getArgument(ThreadContext *tc, bool fp) { 527678Sgblack@eecs.umich.edu panic("getArgument() not implemented for MIPS\n"); 538059SAli.Saidi@ARM.com } 548284SAli.Saidi@ARM.com 557405SAli.Saidi@ARM.com //Floating Point Utility Functions 567405SAli.Saidi@ARM.com uint64_t fpConvert(ConvertType cvt_type, double fp_val); 577405SAli.Saidi@ARM.com double roundFP(double val, int digits); 587405SAli.Saidi@ARM.com double truncFP(double val); 599384SAndreas.Sandberg@arm.com 6010461SAndreas.Sandberg@ARM.com bool getCondCode(uint32_t fcsr, int cc); 6110461SAndreas.Sandberg@ARM.com uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val); 6211165SRekai.GonzalezAlberquilla@arm.com uint32_t genInvalidVector(uint32_t fcsr); 6312109SRekai.GonzalezAlberquilla@arm.com 6412714Sgiacomo.travaglini@arm.com bool isNan(void *val_ptr, int size); 6512714Sgiacomo.travaglini@arm.com bool isQnan(void *val_ptr, int size); 669384SAndreas.Sandberg@arm.com bool isSnan(void *val_ptr, int size); 6711770SCurtis.Dunham@arm.com 6810037SARM gem5 Developers /** 6910461SAndreas.Sandberg@ARM.com * Function to insure ISA semantics about 0 registers. 7010461SAndreas.Sandberg@ARM.com * @param tc The thread context. 7110461SAndreas.Sandberg@ARM.com */ 7210461SAndreas.Sandberg@ARM.com template <class TC> 7310461SAndreas.Sandberg@ARM.com void zeroRegisters(TC *tc); 7410461SAndreas.Sandberg@ARM.com 7510609Sandreas.sandberg@arm.com void startupCPU(ThreadContext *tc, int cpuId); 7610609Sandreas.sandberg@arm.com 7710609Sandreas.sandberg@arm.com void copyRegs(ThreadContext *src, ThreadContext *dest); 7810037SARM gem5 Developers 7910037SARM gem5 Developers // Instruction address compression hooks 8010037SARM gem5 Developers static inline Addr realPCToFetchPC(const Addr &addr) { 8110037SARM gem5 Developers return addr; 8211771SCurtis.Dunham@arm.com } 8310037SARM gem5 Developers 8410037SARM gem5 Developers static inline Addr fetchPCToRealPC(const Addr &addr) { 8513173Sgiacomo.travaglini@arm.com return addr; 8610037SARM gem5 Developers } 8710037SARM gem5 Developers 8813114Sgiacomo.travaglini@arm.com // the size of "fetched" instructions (not necessarily the size 8910037SARM gem5 Developers // of real instructions for PISA) 9011771SCurtis.Dunham@arm.com static inline size_t fetchInstSize() { 9110037SARM gem5 Developers return sizeof(MachInst); 9213173Sgiacomo.travaglini@arm.com } 9310037SARM gem5 Developers 9413114Sgiacomo.travaglini@arm.com static inline MachInst makeRegisterCopy(int dest, int src) { 9510037SARM gem5 Developers panic("makeRegisterCopy not implemented"); 9610037SARM gem5 Developers return 0; 9712477SCurtis.Dunham@arm.com } 9810037SARM gem5 Developers 9910037SARM gem5 Developers static inline ExtMachInst 1009384SAndreas.Sandberg@arm.com makeExtMI(MachInst inst, ThreadContext * xc) { 1019384SAndreas.Sandberg@arm.com#if FULL_SYSTEM 1029384SAndreas.Sandberg@arm.com ExtMachInst ext_inst = inst; 10312479SCurtis.Dunham@arm.com if (xc->readPC() && 0x1) 10412479SCurtis.Dunham@arm.com return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32); 1059384SAndreas.Sandberg@arm.com else 1069384SAndreas.Sandberg@arm.com return ext_inst; 1079384SAndreas.Sandberg@arm.com#else 1089384SAndreas.Sandberg@arm.com return ExtMachInst(inst); 1099384SAndreas.Sandberg@arm.com#endif 1109384SAndreas.Sandberg@arm.com } 1117427Sgblack@eecs.umich.edu}; 1127427Sgblack@eecs.umich.edu 1137427Sgblack@eecs.umich.edu 1149385SAndreas.Sandberg@arm.com#endif 1159385SAndreas.Sandberg@arm.com