utility.hh revision 4826
12447SN/A/*
22447SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
34181Sgblack@eecs.umich.edu * Copyright (c) 2007 MIPS Technologies, Inc.
42447SN/A * All rights reserved.
52447SN/A *
62447SN/A * Redistribution and use in source and binary forms, with or without
72447SN/A * modification, are permitted provided that the following conditions are
82447SN/A * met: redistributions of source code must retain the above copyright
92447SN/A * notice, this list of conditions and the following disclaimer;
102447SN/A * redistributions in binary form must reproduce the above copyright
112447SN/A * notice, this list of conditions and the following disclaimer in the
122447SN/A * documentation and/or other materials provided with the distribution;
132447SN/A * neither the name of the copyright holders nor the names of its
142447SN/A * contributors may be used to endorse or promote products derived from
152447SN/A * this software without specific prior written permission.
162447SN/A *
172447SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
182447SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
192447SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
202447SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
212447SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
222447SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
232447SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
242447SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
252447SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
262447SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
272447SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
282632Sstever@eecs.umich.edu *
292632Sstever@eecs.umich.edu * Authors: Nathan Binkert
302632Sstever@eecs.umich.edu *          Steve Reinhardt
314181Sgblack@eecs.umich.edu *          Korey Sewell
322447SN/A */
332447SN/A
342447SN/A#ifndef __ARCH_MIPS_UTILITY_HH__
352447SN/A#define __ARCH_MIPS_UTILITY_HH__
362447SN/A
372597SN/A#include "arch/mips/types.hh"
384661Sksewell@umich.edu#include "arch/mips/isa_traits.hh"
392597SN/A#include "base/misc.hh"
402980Sgblack@eecs.umich.edu#include "config/full_system.hh"
412972Sgblack@eecs.umich.edu//XXX This is needed for size_t. We should use something other than size_t
422980Sgblack@eecs.umich.edu//#include "kern/linux/linux.hh"
432597SN/A#include "sim/host.hh"
442597SN/A
454661Sksewell@umich.edu#include "cpu/thread_context.hh"
464661Sksewell@umich.edu
472980Sgblack@eecs.umich.educlass ThreadContext;
482980Sgblack@eecs.umich.edu
492597SN/Anamespace MipsISA {
502597SN/A
514826Ssaidi@eecs.umich.edu    uint64_t getArgument(ThreadContext *tc, bool fp) {
524826Ssaidi@eecs.umich.edu        panic("getArgument() not implemented for MIPS\n");
534826Ssaidi@eecs.umich.edu    }
544826Ssaidi@eecs.umich.edu
552686Sksewell@umich.edu    //Floating Point Utility Functions
562686Sksewell@umich.edu    uint64_t fpConvert(ConvertType cvt_type, double fp_val);
572686Sksewell@umich.edu    double roundFP(double val, int digits);
582686Sksewell@umich.edu    double truncFP(double val);
592686Sksewell@umich.edu
602686Sksewell@umich.edu    bool getCondCode(uint32_t fcsr, int cc);
612686Sksewell@umich.edu    uint32_t genCCVector(uint32_t fcsr, int num, uint32_t cc_val);
622686Sksewell@umich.edu    uint32_t genInvalidVector(uint32_t fcsr);
632686Sksewell@umich.edu
642686Sksewell@umich.edu    bool isNan(void *val_ptr, int size);
652686Sksewell@umich.edu    bool isQnan(void *val_ptr, int size);
662686Sksewell@umich.edu    bool isSnan(void *val_ptr, int size);
672972Sgblack@eecs.umich.edu
682972Sgblack@eecs.umich.edu    /**
692972Sgblack@eecs.umich.edu     * Function to insure ISA semantics about 0 registers.
702972Sgblack@eecs.umich.edu     * @param tc The thread context.
712972Sgblack@eecs.umich.edu     */
722972Sgblack@eecs.umich.edu    template <class TC>
732972Sgblack@eecs.umich.edu    void zeroRegisters(TC *tc);
742972Sgblack@eecs.umich.edu
754661Sksewell@umich.edu    void startupCPU(ThreadContext *tc, int cpuId);
764661Sksewell@umich.edu
772972Sgblack@eecs.umich.edu    void copyRegs(ThreadContext *src, ThreadContext *dest);
782972Sgblack@eecs.umich.edu
792972Sgblack@eecs.umich.edu    // Instruction address compression hooks
802972Sgblack@eecs.umich.edu    static inline Addr realPCToFetchPC(const Addr &addr) {
812972Sgblack@eecs.umich.edu        return addr;
822972Sgblack@eecs.umich.edu    }
832972Sgblack@eecs.umich.edu
842972Sgblack@eecs.umich.edu    static inline Addr fetchPCToRealPC(const Addr &addr) {
852972Sgblack@eecs.umich.edu        return addr;
862972Sgblack@eecs.umich.edu    }
872972Sgblack@eecs.umich.edu
882972Sgblack@eecs.umich.edu    // the size of "fetched" instructions (not necessarily the size
892972Sgblack@eecs.umich.edu    // of real instructions for PISA)
902972Sgblack@eecs.umich.edu    static inline size_t fetchInstSize() {
912972Sgblack@eecs.umich.edu        return sizeof(MachInst);
922972Sgblack@eecs.umich.edu    }
932972Sgblack@eecs.umich.edu
942972Sgblack@eecs.umich.edu    static inline MachInst makeRegisterCopy(int dest, int src) {
952972Sgblack@eecs.umich.edu        panic("makeRegisterCopy not implemented");
962972Sgblack@eecs.umich.edu        return 0;
972972Sgblack@eecs.umich.edu    }
983120Sgblack@eecs.umich.edu
994661Sksewell@umich.edu    static inline ExtMachInst
1004661Sksewell@umich.edu    makeExtMI(MachInst inst, ThreadContext * xc) {
1014661Sksewell@umich.edu#if FULL_SYSTEM
1024661Sksewell@umich.edu        ExtMachInst ext_inst = inst;
1034661Sksewell@umich.edu        if (xc->readPC() && 0x1)
1044661Sksewell@umich.edu            return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32);
1054661Sksewell@umich.edu        else
1064661Sksewell@umich.edu            return ext_inst;
1074661Sksewell@umich.edu#else
1084661Sksewell@umich.edu        return ExtMachInst(inst);
1094661Sksewell@umich.edu#endif
1104194Ssaidi@eecs.umich.edu    }
1112597SN/A};
1122447SN/A
1132686Sksewell@umich.edu
1142447SN/A#endif
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