utility.cc revision 5135
17199Sgblack@eecs.umich.edu/* 27199Sgblack@eecs.umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 312504Snikos.nikoleris@arm.com * All rights reserved. 47199Sgblack@eecs.umich.edu * 57199Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67199Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77199Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87199Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97199Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107199Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117199Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127199Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137199Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147199Sgblack@eecs.umich.edu * this software without specific prior written permission. 157199Sgblack@eecs.umich.edu * 167199Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177199Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187199Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197199Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207199Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217199Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227199Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237199Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247199Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257199Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267199Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277199Sgblack@eecs.umich.edu * 287199Sgblack@eecs.umich.edu * Authors: Korey Sewell 297199Sgblack@eecs.umich.edu */ 307199Sgblack@eecs.umich.edu 317199Sgblack@eecs.umich.edu#include "arch/mips/isa_traits.hh" 327199Sgblack@eecs.umich.edu#include "arch/mips/utility.hh" 337199Sgblack@eecs.umich.edu#include "arch/mips/constants.hh" 347199Sgblack@eecs.umich.edu#include "config/full_system.hh" 357199Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 367199Sgblack@eecs.umich.edu#include "cpu/static_inst.hh" 377199Sgblack@eecs.umich.edu#include "sim/serialize.hh" 387199Sgblack@eecs.umich.edu#include "base/bitfield.hh" 397199Sgblack@eecs.umich.edu#include "base/misc.hh" 407199Sgblack@eecs.umich.edu 417199Sgblack@eecs.umich.eduusing namespace MipsISA; 427199Sgblack@eecs.umich.eduusing namespace std; 4312541Sgiacomo.travaglini@arm.com 4412541Sgiacomo.travaglini@arm.comuint64_t 4512541Sgiacomo.travaglini@arm.comMipsISA::fpConvert(ConvertType cvt_type, double fp_val) 4612541Sgiacomo.travaglini@arm.com{ 4712541Sgiacomo.travaglini@arm.com 4812541Sgiacomo.travaglini@arm.com switch (cvt_type) 4912541Sgiacomo.travaglini@arm.com { 5012541Sgiacomo.travaglini@arm.com case SINGLE_TO_DOUBLE: 5112541Sgiacomo.travaglini@arm.com { 5210037SARM gem5 Developers double sdouble_val = fp_val; 5310037SARM gem5 Developers void *sdouble_ptr = &sdouble_val; 5410037SARM gem5 Developers uint64_t sdp_bits = *(uint64_t *) sdouble_ptr; 5510037SARM gem5 Developers return sdp_bits; 5612541Sgiacomo.travaglini@arm.com } 5712541Sgiacomo.travaglini@arm.com 5812541Sgiacomo.travaglini@arm.com case SINGLE_TO_WORD: 5912541Sgiacomo.travaglini@arm.com { 6012541Sgiacomo.travaglini@arm.com int32_t sword_val = (int32_t) fp_val; 6110037SARM gem5 Developers void *sword_ptr = &sword_val; 6212541Sgiacomo.travaglini@arm.com uint64_t sword_bits= *(uint32_t *) sword_ptr; 6310037SARM gem5 Developers return sword_bits; 6410037SARM gem5 Developers } 6512542Sgiacomo.travaglini@arm.com 6612542Sgiacomo.travaglini@arm.com case WORD_TO_SINGLE: 6712542Sgiacomo.travaglini@arm.com { 6812542Sgiacomo.travaglini@arm.com float wfloat_val = fp_val; 6912542Sgiacomo.travaglini@arm.com void *wfloat_ptr = &wfloat_val; 7012542Sgiacomo.travaglini@arm.com uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr; 7112542Sgiacomo.travaglini@arm.com return wfloat_bits; 7212542Sgiacomo.travaglini@arm.com } 7312542Sgiacomo.travaglini@arm.com 7412542Sgiacomo.travaglini@arm.com case WORD_TO_DOUBLE: 7512542Sgiacomo.travaglini@arm.com { 7612542Sgiacomo.travaglini@arm.com double wdouble_val = fp_val; 7712542Sgiacomo.travaglini@arm.com void *wdouble_ptr = &wdouble_val; 7812542Sgiacomo.travaglini@arm.com uint64_t wdp_bits = *(uint64_t *) wdouble_ptr; 7912542Sgiacomo.travaglini@arm.com return wdp_bits; 8012542Sgiacomo.travaglini@arm.com } 8112542Sgiacomo.travaglini@arm.com 8212542Sgiacomo.travaglini@arm.com default: 8312542Sgiacomo.travaglini@arm.com panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type); 8412542Sgiacomo.travaglini@arm.com return 0; 8512542Sgiacomo.travaglini@arm.com } 8612542Sgiacomo.travaglini@arm.com} 8712542Sgiacomo.travaglini@arm.com 8812542Sgiacomo.travaglini@arm.comdouble 8912542Sgiacomo.travaglini@arm.comMipsISA::roundFP(double val, int digits) 9010037SARM gem5 Developers{ 9110037SARM gem5 Developers double digit_offset = pow(10.0,digits); 9210037SARM gem5 Developers val = val * digit_offset; 9310037SARM gem5 Developers val = val + 0.5; 9410037SARM gem5 Developers val = floor(val); 9510037SARM gem5 Developers val = val / digit_offset; 9610037SARM gem5 Developers return val; 9710037SARM gem5 Developers} 9810474Sandreas.hansson@arm.com 9910474Sandreas.hansson@arm.comdouble 10010037SARM gem5 DevelopersMipsISA::truncFP(double val) 10110037SARM gem5 Developers{ 10210037SARM gem5 Developers int trunc_val = (int) val; 10310037SARM gem5 Developers return (double) trunc_val; 10410474Sandreas.hansson@arm.com} 10510037SARM gem5 Developers 10610037SARM gem5 Developersbool 1078782Sgblack@eecs.umich.eduMipsISA::getCondCode(uint32_t fcsr, int cc_idx) 10810037SARM gem5 Developers{ 1098782Sgblack@eecs.umich.edu int shift = (cc_idx == 0) ? 23 : cc_idx + 24; 1107199Sgblack@eecs.umich.edu bool cc_val = (fcsr >> shift) & 0x00000001; 1117199Sgblack@eecs.umich.edu return cc_val; 11210037SARM gem5 Developers} 11310037SARM gem5 Developers 1148628SAli.Saidi@ARM.comuint32_t 11510037SARM gem5 DevelopersMipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val) 11610037SARM gem5 Developers{ 11710037SARM gem5 Developers int cc_idx = (cc_num == 0) ? 23 : cc_num + 24; 11810037SARM gem5 Developers 11910037SARM gem5 Developers fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 | 12010037SARM gem5 Developers cc_val << cc_idx | 12110037SARM gem5 Developers bits(fcsr, cc_idx - 1, 0); 12210037SARM gem5 Developers 12310037SARM gem5 Developers return fcsr; 12410037SARM gem5 Developers} 12510037SARM gem5 Developers 12610037SARM gem5 Developersuint32_t 12710037SARM gem5 DevelopersMipsISA::genInvalidVector(uint32_t fcsr_bits) 12810037SARM gem5 Developers{ 12910037SARM gem5 Developers //Set FCSR invalid in "flag" field 13010474Sandreas.hansson@arm.com int invalid_offset = Invalid + Flag_Field; 13110037SARM gem5 Developers fcsr_bits = fcsr_bits | (1 << invalid_offset); 13210037SARM gem5 Developers 13310037SARM gem5 Developers //Set FCSR invalid in "cause" flag 13410037SARM gem5 Developers int cause_offset = Invalid + Cause_Field; 13510037SARM gem5 Developers fcsr_bits = fcsr_bits | (1 << cause_offset); 13610037SARM gem5 Developers 13710037SARM gem5 Developers return fcsr_bits; 13810037SARM gem5 Developers} 13910037SARM gem5 Developers 14010037SARM gem5 Developersbool 14110037SARM gem5 DevelopersMipsISA::isNan(void *val_ptr, int size) 14210037SARM gem5 Developers{ 14310037SARM gem5 Developers switch (size) 14410037SARM gem5 Developers { 14510037SARM gem5 Developers case 32: 14610037SARM gem5 Developers { 14710037SARM gem5 Developers uint32_t val_bits = *(uint32_t *) val_ptr; 14810037SARM gem5 Developers return (bits(val_bits, 30, 23) == 0xFF); 14910037SARM gem5 Developers } 15010037SARM gem5 Developers 15110037SARM gem5 Developers case 64: 15210037SARM gem5 Developers { 15310037SARM gem5 Developers uint64_t val_bits = *(uint64_t *) val_ptr; 15410037SARM gem5 Developers return (bits(val_bits, 62, 52) == 0x7FF); 15510037SARM gem5 Developers } 15610037SARM gem5 Developers 15710037SARM gem5 Developers default: 15810037SARM gem5 Developers panic("Type unsupported. Size mismatch\n"); 15910037SARM gem5 Developers } 16010037SARM gem5 Developers} 16110037SARM gem5 Developers 16210037SARM gem5 Developers 16310037SARM gem5 Developersbool 16410037SARM gem5 DevelopersMipsISA::isQnan(void *val_ptr, int size) 16510037SARM gem5 Developers{ 16610037SARM gem5 Developers switch (size) 16710037SARM gem5 Developers { 16810037SARM gem5 Developers case 32: 16911355Smitch.hayenga@arm.com { 17011355Smitch.hayenga@arm.com uint32_t val_bits = *(uint32_t *) val_ptr; 17110037SARM gem5 Developers return (bits(val_bits, 30, 22) == 0x1FE); 17210037SARM gem5 Developers } 17310037SARM gem5 Developers 17410037SARM gem5 Developers case 64: 17512258Sgiacomo.travaglini@arm.com { 17612258Sgiacomo.travaglini@arm.com uint64_t val_bits = *(uint64_t *) val_ptr; 17712258Sgiacomo.travaglini@arm.com return (bits(val_bits, 62, 51) == 0xFFE); 17810037SARM gem5 Developers } 17912258Sgiacomo.travaglini@arm.com 18012258Sgiacomo.travaglini@arm.com default: 18112258Sgiacomo.travaglini@arm.com panic("Type unsupported. Size mismatch\n"); 18212258Sgiacomo.travaglini@arm.com } 18312258Sgiacomo.travaglini@arm.com} 18412258Sgiacomo.travaglini@arm.com 18512258Sgiacomo.travaglini@arm.combool 18612258Sgiacomo.travaglini@arm.comMipsISA::isSnan(void *val_ptr, int size) 18712258Sgiacomo.travaglini@arm.com{ 18812258Sgiacomo.travaglini@arm.com switch (size) 18912258Sgiacomo.travaglini@arm.com { 19012258Sgiacomo.travaglini@arm.com case 32: 19112258Sgiacomo.travaglini@arm.com { 19212258Sgiacomo.travaglini@arm.com uint32_t val_bits = *(uint32_t *) val_ptr; 19312258Sgiacomo.travaglini@arm.com return (bits(val_bits, 30, 22) == 0x1FF); 19412258Sgiacomo.travaglini@arm.com } 19512258Sgiacomo.travaglini@arm.com 19612258Sgiacomo.travaglini@arm.com case 64: 19712258Sgiacomo.travaglini@arm.com { 19812258Sgiacomo.travaglini@arm.com uint64_t val_bits = *(uint64_t *) val_ptr; 19912258Sgiacomo.travaglini@arm.com return (bits(val_bits, 62, 51) == 0xFFF); 20012258Sgiacomo.travaglini@arm.com } 20112258Sgiacomo.travaglini@arm.com 20212258Sgiacomo.travaglini@arm.com default: 20312258Sgiacomo.travaglini@arm.com panic("Type unsupported. Size mismatch\n"); 20412258Sgiacomo.travaglini@arm.com } 20512258Sgiacomo.travaglini@arm.com} 20612258Sgiacomo.travaglini@arm.com 20712258Sgiacomo.travaglini@arm.comvoid 20812258Sgiacomo.travaglini@arm.comMipsISA::startupCPU(ThreadContext *tc, int cpuId) 20912258Sgiacomo.travaglini@arm.com{ 21012258Sgiacomo.travaglini@arm.com tc->activate(0); 21112258Sgiacomo.travaglini@arm.com} 21212258Sgiacomo.travaglini@arm.com