utility.cc revision 6379
12686Sksewell@umich.edu/* 25254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 35254Sksewell@umich.edu * All rights reserved. 42686Sksewell@umich.edu * 55254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 152686Sksewell@umich.edu * 165254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272706Sksewell@umich.edu * 285254Sksewell@umich.edu * Authors: Korey Sewell 292686Sksewell@umich.edu */ 302686Sksewell@umich.edu 314661Sksewell@umich.edu#include "arch/mips/isa_traits.hh" 322686Sksewell@umich.edu#include "arch/mips/utility.hh" 334661Sksewell@umich.edu#include "config/full_system.hh" 344661Sksewell@umich.edu#include "cpu/thread_context.hh" 354661Sksewell@umich.edu#include "cpu/static_inst.hh" 364661Sksewell@umich.edu#include "sim/serialize.hh" 374661Sksewell@umich.edu#include "base/bitfield.hh" 382980Sgblack@eecs.umich.edu#include "base/misc.hh" 392686Sksewell@umich.edu 405222Sksewell@umich.edu#if FULL_SYSTEM 416379Sgblack@eecs.umich.edu#include "arch/mips/registers.hh" 425222Sksewell@umich.edu#include "arch/mips/vtophys.hh" 435222Sksewell@umich.edu#include "mem/vport.hh" 445222Sksewell@umich.edu#endif 455222Sksewell@umich.edu 465222Sksewell@umich.edu 472686Sksewell@umich.eduusing namespace MipsISA; 484661Sksewell@umich.eduusing namespace std; 492686Sksewell@umich.edu 505222Sksewell@umich.edunamespace MipsISA { 515222Sksewell@umich.edu 522686Sksewell@umich.eduuint64_t 535222Sksewell@umich.edugetArgument(ThreadContext *tc, int number, bool fp) 545222Sksewell@umich.edu{ 555222Sksewell@umich.edu#if FULL_SYSTEM 566379Sgblack@eecs.umich.edu if (number < 4) { 575222Sksewell@umich.edu if (fp) 586379Sgblack@eecs.umich.edu return tc->readFloatRegBits(FirstArgumentReg + number); 595222Sksewell@umich.edu else 606379Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + number); 615222Sksewell@umich.edu } else { 625222Sksewell@umich.edu Addr sp = tc->readIntReg(StackPointerReg); 635498Ssaidi@eecs.umich.edu VirtualPort *vp = tc->getVirtPort(); 645222Sksewell@umich.edu uint64_t arg = vp->read<uint64_t>(sp + 656379Sgblack@eecs.umich.edu (number - 4) * sizeof(uint64_t)); 665222Sksewell@umich.edu return arg; 675222Sksewell@umich.edu } 685222Sksewell@umich.edu#else 695222Sksewell@umich.edu panic("getArgument() is Full system only\n"); 705222Sksewell@umich.edu M5_DUMMY_RETURN 715222Sksewell@umich.edu#endif 725222Sksewell@umich.edu} 735222Sksewell@umich.edu 745222Sksewell@umich.eduuint64_t 755222Sksewell@umich.edufpConvert(ConvertType cvt_type, double fp_val) 762686Sksewell@umich.edu{ 772686Sksewell@umich.edu 782686Sksewell@umich.edu switch (cvt_type) 792686Sksewell@umich.edu { 802686Sksewell@umich.edu case SINGLE_TO_DOUBLE: 812686Sksewell@umich.edu { 822686Sksewell@umich.edu double sdouble_val = fp_val; 832686Sksewell@umich.edu void *sdouble_ptr = &sdouble_val; 842686Sksewell@umich.edu uint64_t sdp_bits = *(uint64_t *) sdouble_ptr; 852686Sksewell@umich.edu return sdp_bits; 862686Sksewell@umich.edu } 872686Sksewell@umich.edu 882686Sksewell@umich.edu case SINGLE_TO_WORD: 892686Sksewell@umich.edu { 902686Sksewell@umich.edu int32_t sword_val = (int32_t) fp_val; 912686Sksewell@umich.edu void *sword_ptr = &sword_val; 922686Sksewell@umich.edu uint64_t sword_bits= *(uint32_t *) sword_ptr; 932686Sksewell@umich.edu return sword_bits; 942686Sksewell@umich.edu } 952686Sksewell@umich.edu 962686Sksewell@umich.edu case WORD_TO_SINGLE: 972686Sksewell@umich.edu { 982686Sksewell@umich.edu float wfloat_val = fp_val; 992686Sksewell@umich.edu void *wfloat_ptr = &wfloat_val; 1002686Sksewell@umich.edu uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr; 1012686Sksewell@umich.edu return wfloat_bits; 1022686Sksewell@umich.edu } 1032686Sksewell@umich.edu 1042686Sksewell@umich.edu case WORD_TO_DOUBLE: 1052686Sksewell@umich.edu { 1062686Sksewell@umich.edu double wdouble_val = fp_val; 1072686Sksewell@umich.edu void *wdouble_ptr = &wdouble_val; 1082686Sksewell@umich.edu uint64_t wdp_bits = *(uint64_t *) wdouble_ptr; 1092686Sksewell@umich.edu return wdp_bits; 1102686Sksewell@umich.edu } 1112686Sksewell@umich.edu 1122686Sksewell@umich.edu default: 1132686Sksewell@umich.edu panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type); 1142686Sksewell@umich.edu return 0; 1152686Sksewell@umich.edu } 1162686Sksewell@umich.edu} 1172686Sksewell@umich.edu 1182686Sksewell@umich.edudouble 1195222Sksewell@umich.eduroundFP(double val, int digits) 1202686Sksewell@umich.edu{ 1212686Sksewell@umich.edu double digit_offset = pow(10.0,digits); 1222686Sksewell@umich.edu val = val * digit_offset; 1232686Sksewell@umich.edu val = val + 0.5; 1242686Sksewell@umich.edu val = floor(val); 1252686Sksewell@umich.edu val = val / digit_offset; 1262686Sksewell@umich.edu return val; 1272686Sksewell@umich.edu} 1282686Sksewell@umich.edu 1292686Sksewell@umich.edudouble 1305222Sksewell@umich.edutruncFP(double val) 1312686Sksewell@umich.edu{ 1322686Sksewell@umich.edu int trunc_val = (int) val; 1332686Sksewell@umich.edu return (double) trunc_val; 1342686Sksewell@umich.edu} 1352686Sksewell@umich.edu 1362686Sksewell@umich.edubool 1375222Sksewell@umich.edugetCondCode(uint32_t fcsr, int cc_idx) 1382686Sksewell@umich.edu{ 1392686Sksewell@umich.edu int shift = (cc_idx == 0) ? 23 : cc_idx + 24; 1402686Sksewell@umich.edu bool cc_val = (fcsr >> shift) & 0x00000001; 1412686Sksewell@umich.edu return cc_val; 1422686Sksewell@umich.edu} 1432686Sksewell@umich.edu 1442686Sksewell@umich.eduuint32_t 1455222Sksewell@umich.edugenCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val) 1462686Sksewell@umich.edu{ 1472686Sksewell@umich.edu int cc_idx = (cc_num == 0) ? 23 : cc_num + 24; 1482686Sksewell@umich.edu 1495570Snate@binkert.org fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) | 1502686Sksewell@umich.edu cc_val << cc_idx | 1512686Sksewell@umich.edu bits(fcsr, cc_idx - 1, 0); 1522686Sksewell@umich.edu 1532686Sksewell@umich.edu return fcsr; 1542686Sksewell@umich.edu} 1552686Sksewell@umich.edu 1562686Sksewell@umich.eduuint32_t 1575222Sksewell@umich.edugenInvalidVector(uint32_t fcsr_bits) 1582686Sksewell@umich.edu{ 1592686Sksewell@umich.edu //Set FCSR invalid in "flag" field 1602686Sksewell@umich.edu int invalid_offset = Invalid + Flag_Field; 1612686Sksewell@umich.edu fcsr_bits = fcsr_bits | (1 << invalid_offset); 1622686Sksewell@umich.edu 1632686Sksewell@umich.edu //Set FCSR invalid in "cause" flag 1642686Sksewell@umich.edu int cause_offset = Invalid + Cause_Field; 1652686Sksewell@umich.edu fcsr_bits = fcsr_bits | (1 << cause_offset); 1662686Sksewell@umich.edu 1672686Sksewell@umich.edu return fcsr_bits; 1682686Sksewell@umich.edu} 1692686Sksewell@umich.edu 1702686Sksewell@umich.edubool 1715222Sksewell@umich.eduisNan(void *val_ptr, int size) 1722686Sksewell@umich.edu{ 1732686Sksewell@umich.edu switch (size) 1742686Sksewell@umich.edu { 1752686Sksewell@umich.edu case 32: 1762686Sksewell@umich.edu { 1772686Sksewell@umich.edu uint32_t val_bits = *(uint32_t *) val_ptr; 1782686Sksewell@umich.edu return (bits(val_bits, 30, 23) == 0xFF); 1792686Sksewell@umich.edu } 1802686Sksewell@umich.edu 1812686Sksewell@umich.edu case 64: 1822686Sksewell@umich.edu { 1832686Sksewell@umich.edu uint64_t val_bits = *(uint64_t *) val_ptr; 1842686Sksewell@umich.edu return (bits(val_bits, 62, 52) == 0x7FF); 1852686Sksewell@umich.edu } 1862686Sksewell@umich.edu 1872686Sksewell@umich.edu default: 1882686Sksewell@umich.edu panic("Type unsupported. Size mismatch\n"); 1892686Sksewell@umich.edu } 1902686Sksewell@umich.edu} 1912686Sksewell@umich.edu 1922686Sksewell@umich.edu 1932686Sksewell@umich.edubool 1945222Sksewell@umich.eduisQnan(void *val_ptr, int size) 1952686Sksewell@umich.edu{ 1962686Sksewell@umich.edu switch (size) 1972686Sksewell@umich.edu { 1982686Sksewell@umich.edu case 32: 1992686Sksewell@umich.edu { 2002686Sksewell@umich.edu uint32_t val_bits = *(uint32_t *) val_ptr; 2012686Sksewell@umich.edu return (bits(val_bits, 30, 22) == 0x1FE); 2022686Sksewell@umich.edu } 2032686Sksewell@umich.edu 2042686Sksewell@umich.edu case 64: 2052686Sksewell@umich.edu { 2062686Sksewell@umich.edu uint64_t val_bits = *(uint64_t *) val_ptr; 2072686Sksewell@umich.edu return (bits(val_bits, 62, 51) == 0xFFE); 2082686Sksewell@umich.edu } 2092686Sksewell@umich.edu 2102686Sksewell@umich.edu default: 2112686Sksewell@umich.edu panic("Type unsupported. Size mismatch\n"); 2122686Sksewell@umich.edu } 2132686Sksewell@umich.edu} 2142686Sksewell@umich.edu 2152686Sksewell@umich.edubool 2165222Sksewell@umich.eduisSnan(void *val_ptr, int size) 2172686Sksewell@umich.edu{ 2182686Sksewell@umich.edu switch (size) 2192686Sksewell@umich.edu { 2202686Sksewell@umich.edu case 32: 2212686Sksewell@umich.edu { 2222686Sksewell@umich.edu uint32_t val_bits = *(uint32_t *) val_ptr; 2232686Sksewell@umich.edu return (bits(val_bits, 30, 22) == 0x1FF); 2242686Sksewell@umich.edu } 2252686Sksewell@umich.edu 2262686Sksewell@umich.edu case 64: 2272686Sksewell@umich.edu { 2282686Sksewell@umich.edu uint64_t val_bits = *(uint64_t *) val_ptr; 2292686Sksewell@umich.edu return (bits(val_bits, 62, 51) == 0xFFF); 2302686Sksewell@umich.edu } 2312686Sksewell@umich.edu 2322686Sksewell@umich.edu default: 2332686Sksewell@umich.edu panic("Type unsupported. Size mismatch\n"); 2342686Sksewell@umich.edu } 2352686Sksewell@umich.edu} 2364661Sksewell@umich.edu 2375222Sksewell@umich.edutemplate <class CPU> 2385222Sksewell@umich.eduvoid 2395222Sksewell@umich.eduzeroRegisters(CPU *cpu) 2405222Sksewell@umich.edu{ 2415222Sksewell@umich.edu // Insure ISA semantics 2425222Sksewell@umich.edu // (no longer very clean due to the change in setIntReg() in the 2435222Sksewell@umich.edu // cpu model. Consider changing later.) 2445222Sksewell@umich.edu cpu->thread->setIntReg(ZeroReg, 0); 2455222Sksewell@umich.edu cpu->thread->setFloatReg(ZeroReg, 0.0); 2465222Sksewell@umich.edu} 2475222Sksewell@umich.edu 2485222Sksewell@umich.eduvoid 2495222Sksewell@umich.edustartupCPU(ThreadContext *tc, int cpuId) 2505222Sksewell@umich.edu{ 2515715Shsul@eecs.umich.edu tc->activate(0/*tc->threadId()*/); 2525222Sksewell@umich.edu} 2535222Sksewell@umich.edu 2546329Sgblack@eecs.umich.eduvoid 2556329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 2566329Sgblack@eecs.umich.edu{ 2576329Sgblack@eecs.umich.edu panic("Copy Regs Not Implemented Yet\n"); 2586329Sgblack@eecs.umich.edu} 2596329Sgblack@eecs.umich.edu 2606329Sgblack@eecs.umich.eduvoid 2616329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 2626329Sgblack@eecs.umich.edu{ 2636329Sgblack@eecs.umich.edu panic("Copy Misc. Regs Not Implemented Yet\n"); 2646329Sgblack@eecs.umich.edu} 2656329Sgblack@eecs.umich.edu 2665222Sksewell@umich.edu} // namespace MipsISA 267