utility.cc revision 5086
110298Salexandru.dutu@amd.com/* 210298Salexandru.dutu@amd.com * Copyright (c) 2003-2006 The Regents of The University of Michigan 310298Salexandru.dutu@amd.com * All rights reserved. 410298Salexandru.dutu@amd.com * 510298Salexandru.dutu@amd.com * Redistribution and use in source and binary forms, with or without 610298Salexandru.dutu@amd.com * modification, are permitted provided that the following conditions are 710298Salexandru.dutu@amd.com * met: redistributions of source code must retain the above copyright 810298Salexandru.dutu@amd.com * notice, this list of conditions and the following disclaimer; 910298Salexandru.dutu@amd.com * redistributions in binary form must reproduce the above copyright 1010298Salexandru.dutu@amd.com * notice, this list of conditions and the following disclaimer in the 1110298Salexandru.dutu@amd.com * documentation and/or other materials provided with the distribution; 1210298Salexandru.dutu@amd.com * neither the name of the copyright holders nor the names of its 1310298Salexandru.dutu@amd.com * contributors may be used to endorse or promote products derived from 1410298Salexandru.dutu@amd.com * this software without specific prior written permission. 1510298Salexandru.dutu@amd.com * 1610298Salexandru.dutu@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710298Salexandru.dutu@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810298Salexandru.dutu@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910298Salexandru.dutu@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010298Salexandru.dutu@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110298Salexandru.dutu@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210298Salexandru.dutu@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310298Salexandru.dutu@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410298Salexandru.dutu@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510298Salexandru.dutu@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610298Salexandru.dutu@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710298Salexandru.dutu@amd.com * 2810298Salexandru.dutu@amd.com * Authors: Korey Sewell 2910298Salexandru.dutu@amd.com */ 3010298Salexandru.dutu@amd.com 3110298Salexandru.dutu@amd.com#include "arch/mips/isa_traits.hh" 3210298Salexandru.dutu@amd.com#include "arch/mips/utility.hh" 3310298Salexandru.dutu@amd.com#include "arch/mips/constants.hh" 3410298Salexandru.dutu@amd.com#include "config/full_system.hh" 3510298Salexandru.dutu@amd.com#include "cpu/thread_context.hh" 3610298Salexandru.dutu@amd.com#include "cpu/static_inst.hh" 3710298Salexandru.dutu@amd.com#include "sim/serialize.hh" 3810298Salexandru.dutu@amd.com#include "base/bitfield.hh" 3910298Salexandru.dutu@amd.com#include "base/misc.hh" 4010298Salexandru.dutu@amd.com 4110298Salexandru.dutu@amd.comusing namespace MipsISA; 4210298Salexandru.dutu@amd.comusing namespace std; 4310298Salexandru.dutu@amd.com 4411800Sbrandon.potter@amd.comuint64_t 4511800Sbrandon.potter@amd.comMipsISA::fpConvert(ConvertType cvt_type, double fp_val) 4610298Salexandru.dutu@amd.com{ 4710298Salexandru.dutu@amd.com 4810298Salexandru.dutu@amd.com switch (cvt_type) 4910298Salexandru.dutu@amd.com { 5010298Salexandru.dutu@amd.com case SINGLE_TO_DOUBLE: 5110298Salexandru.dutu@amd.com { 5210298Salexandru.dutu@amd.com double sdouble_val = fp_val; 5310298Salexandru.dutu@amd.com void *sdouble_ptr = &sdouble_val; 5410298Salexandru.dutu@amd.com uint64_t sdp_bits = *(uint64_t *) sdouble_ptr; 5510298Salexandru.dutu@amd.com return sdp_bits; 5610298Salexandru.dutu@amd.com } 5710298Salexandru.dutu@amd.com 5810298Salexandru.dutu@amd.com case SINGLE_TO_WORD: 5910298Salexandru.dutu@amd.com { 6010298Salexandru.dutu@amd.com int32_t sword_val = (int32_t) fp_val; 6110298Salexandru.dutu@amd.com void *sword_ptr = &sword_val; 6210298Salexandru.dutu@amd.com uint64_t sword_bits= *(uint32_t *) sword_ptr; 6310298Salexandru.dutu@amd.com return sword_bits; 6410298Salexandru.dutu@amd.com } 6510298Salexandru.dutu@amd.com 6610298Salexandru.dutu@amd.com case WORD_TO_SINGLE: 6710298Salexandru.dutu@amd.com { 6810298Salexandru.dutu@amd.com float wfloat_val = fp_val; 6910298Salexandru.dutu@amd.com void *wfloat_ptr = &wfloat_val; 7010298Salexandru.dutu@amd.com uint64_t wfloat_bits = *(uint32_t *) wfloat_ptr; 7110298Salexandru.dutu@amd.com return wfloat_bits; 7210298Salexandru.dutu@amd.com } 7310298Salexandru.dutu@amd.com 7410298Salexandru.dutu@amd.com case WORD_TO_DOUBLE: 7510298Salexandru.dutu@amd.com { 7610298Salexandru.dutu@amd.com double wdouble_val = fp_val; 7710298Salexandru.dutu@amd.com void *wdouble_ptr = &wdouble_val; 7810298Salexandru.dutu@amd.com uint64_t wdp_bits = *(uint64_t *) wdouble_ptr; 7910298Salexandru.dutu@amd.com return wdp_bits; 8010298Salexandru.dutu@amd.com } 8110298Salexandru.dutu@amd.com 8210298Salexandru.dutu@amd.com default: 8310298Salexandru.dutu@amd.com panic("Invalid Floating Point Conversion Type (%d). See \"types.hh\" for List of Conversions\n",cvt_type); 8410298Salexandru.dutu@amd.com return 0; 8510298Salexandru.dutu@amd.com } 8610298Salexandru.dutu@amd.com} 8710298Salexandru.dutu@amd.com 8810298Salexandru.dutu@amd.comdouble 8910298Salexandru.dutu@amd.comMipsISA::roundFP(double val, int digits) 9010298Salexandru.dutu@amd.com{ 9110298Salexandru.dutu@amd.com double digit_offset = pow(10.0,digits); 9210298Salexandru.dutu@amd.com val = val * digit_offset; 9310298Salexandru.dutu@amd.com val = val + 0.5; 9410298Salexandru.dutu@amd.com val = floor(val); 9510298Salexandru.dutu@amd.com val = val / digit_offset; 9610298Salexandru.dutu@amd.com return val; 9710298Salexandru.dutu@amd.com} 9810298Salexandru.dutu@amd.com 9910298Salexandru.dutu@amd.comdouble 10010298Salexandru.dutu@amd.comMipsISA::truncFP(double val) 10110298Salexandru.dutu@amd.com{ 10210298Salexandru.dutu@amd.com int trunc_val = (int) val; 10310298Salexandru.dutu@amd.com return (double) trunc_val; 10410298Salexandru.dutu@amd.com} 10510298Salexandru.dutu@amd.com 10610298Salexandru.dutu@amd.combool 10710298Salexandru.dutu@amd.comMipsISA::getCondCode(uint32_t fcsr, int cc_idx) 10810298Salexandru.dutu@amd.com{ 10910298Salexandru.dutu@amd.com int shift = (cc_idx == 0) ? 23 : cc_idx + 24; 11010298Salexandru.dutu@amd.com bool cc_val = (fcsr >> shift) & 0x00000001; 11110298Salexandru.dutu@amd.com return cc_val; 11210298Salexandru.dutu@amd.com} 11310298Salexandru.dutu@amd.com 11410298Salexandru.dutu@amd.comuint32_t 11510298Salexandru.dutu@amd.comMipsISA::genCCVector(uint32_t fcsr, int cc_num, uint32_t cc_val) 11610298Salexandru.dutu@amd.com{ 11710298Salexandru.dutu@amd.com int cc_idx = (cc_num == 0) ? 23 : cc_num + 24; 11810298Salexandru.dutu@amd.com 11910298Salexandru.dutu@amd.com fcsr = bits(fcsr, 31, cc_idx + 1) << cc_idx + 1 | 12010298Salexandru.dutu@amd.com cc_val << cc_idx | 12110298Salexandru.dutu@amd.com bits(fcsr, cc_idx - 1, 0); 12210298Salexandru.dutu@amd.com 12310298Salexandru.dutu@amd.com return fcsr; 12410298Salexandru.dutu@amd.com} 12510298Salexandru.dutu@amd.com 12610298Salexandru.dutu@amd.comuint32_t 12710298Salexandru.dutu@amd.comMipsISA::genInvalidVector(uint32_t fcsr_bits) 12810298Salexandru.dutu@amd.com{ 12910298Salexandru.dutu@amd.com //Set FCSR invalid in "flag" field 13010298Salexandru.dutu@amd.com int invalid_offset = Invalid + Flag_Field; 13110298Salexandru.dutu@amd.com fcsr_bits = fcsr_bits | (1 << invalid_offset); 13210298Salexandru.dutu@amd.com 13310298Salexandru.dutu@amd.com //Set FCSR invalid in "cause" flag 13410298Salexandru.dutu@amd.com int cause_offset = Invalid + Cause_Field; 13510298Salexandru.dutu@amd.com fcsr_bits = fcsr_bits | (1 << cause_offset); 13610298Salexandru.dutu@amd.com 13710298Salexandru.dutu@amd.com return fcsr_bits; 13810298Salexandru.dutu@amd.com} 13910298Salexandru.dutu@amd.com 14010298Salexandru.dutu@amd.combool 14110298Salexandru.dutu@amd.comMipsISA::isNan(void *val_ptr, int size) 14210556Salexandru.dutu@amd.com{ 14312432Sgabeblack@google.com switch (size) 14410298Salexandru.dutu@amd.com { 14510298Salexandru.dutu@amd.com case 32: 14611175Sandreas.hansson@arm.com { 14710298Salexandru.dutu@amd.com uint32_t val_bits = *(uint32_t *) val_ptr; 14810558Salexandru.dutu@amd.com return (bits(val_bits, 30, 23) == 0xFF); 14911175Sandreas.hansson@arm.com } 15011175Sandreas.hansson@arm.com 15111175Sandreas.hansson@arm.com case 64: 15211175Sandreas.hansson@arm.com { 15311175Sandreas.hansson@arm.com uint64_t val_bits = *(uint64_t *) val_ptr; 15411168Sandreas.hansson@arm.com return (bits(val_bits, 62, 52) == 0x7FF); 15511168Sandreas.hansson@arm.com } 15610298Salexandru.dutu@amd.com 15710298Salexandru.dutu@amd.com default: 158 panic("Type unsupported. Size mismatch\n"); 159 } 160} 161 162 163bool 164MipsISA::isQnan(void *val_ptr, int size) 165{ 166 switch (size) 167 { 168 case 32: 169 { 170 uint32_t val_bits = *(uint32_t *) val_ptr; 171 return (bits(val_bits, 30, 22) == 0x1FE); 172 } 173 174 case 64: 175 { 176 uint64_t val_bits = *(uint64_t *) val_ptr; 177 return (bits(val_bits, 62, 51) == 0xFFE); 178 } 179 180 default: 181 panic("Type unsupported. Size mismatch\n"); 182 } 183} 184 185bool 186MipsISA::isSnan(void *val_ptr, int size) 187{ 188 switch (size) 189 { 190 case 32: 191 { 192 uint32_t val_bits = *(uint32_t *) val_ptr; 193 return (bits(val_bits, 30, 22) == 0x1FF); 194 } 195 196 case 64: 197 { 198 uint64_t val_bits = *(uint64_t *) val_ptr; 199 return (bits(val_bits, 62, 51) == 0xFFF); 200 } 201 202 default: 203 panic("Type unsupported. Size mismatch\n"); 204 } 205} 206 207void 208MipsISA::startupCPU(ThreadContext *tc, int cpuId) 209{ 210 tc->activate(0); 211} 212