stacktrace.cc revision 14018
15081Sgblack@eecs.umich.edu/* 25081Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 35081Sgblack@eecs.umich.edu * All rights reserved. 45081Sgblack@eecs.umich.edu * 55081Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65081Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75081Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85081Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95081Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105081Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115081Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125081Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135081Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145081Sgblack@eecs.umich.edu * this software without specific prior written permission. 155081Sgblack@eecs.umich.edu * 165081Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175081Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185081Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195081Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205081Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215081Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225081Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235081Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245081Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255081Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265081Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275081Sgblack@eecs.umich.edu * 285081Sgblack@eecs.umich.edu * Authors: Nathan Binkert 295081Sgblack@eecs.umich.edu */ 305081Sgblack@eecs.umich.edu 315081Sgblack@eecs.umich.edu#include "arch/mips/stacktrace.hh" 325081Sgblack@eecs.umich.edu 335081Sgblack@eecs.umich.edu#include <string> 345081Sgblack@eecs.umich.edu 355081Sgblack@eecs.umich.edu#include "arch/mips/isa_traits.hh" 365081Sgblack@eecs.umich.edu#include "arch/mips/vtophys.hh" 375081Sgblack@eecs.umich.edu#include "base/bitfield.hh" 385081Sgblack@eecs.umich.edu#include "base/trace.hh" 395081Sgblack@eecs.umich.edu#include "cpu/base.hh" 405081Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 415081Sgblack@eecs.umich.edu#include "mem/fs_translating_port_proxy.hh" 425081Sgblack@eecs.umich.edu#include "sim/system.hh" 435081Sgblack@eecs.umich.edu 445081Sgblack@eecs.umich.eduusing namespace MipsISA; 455081Sgblack@eecs.umich.edu 465081Sgblack@eecs.umich.eduProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc) 475081Sgblack@eecs.umich.edu{} 485081Sgblack@eecs.umich.edu 495081Sgblack@eecs.umich.eduAddr 505081Sgblack@eecs.umich.eduProcessInfo::task(Addr ksp) const 515081Sgblack@eecs.umich.edu{ 525081Sgblack@eecs.umich.edu Addr base = ksp & ~0x3fff; 535081Sgblack@eecs.umich.edu if (base == ULL(0xfffffc0000000000)) 545081Sgblack@eecs.umich.edu return 0; 555081Sgblack@eecs.umich.edu 565081Sgblack@eecs.umich.edu Addr tsk; 575081Sgblack@eecs.umich.edu 585081Sgblack@eecs.umich.edu FSTranslatingPortProxy &vp = tc->getVirtProxy(); 595081Sgblack@eecs.umich.edu tsk = vp.read<Addr>(base + task_off, GuestByteOrder); 605081Sgblack@eecs.umich.edu 615081Sgblack@eecs.umich.edu return tsk; 625081Sgblack@eecs.umich.edu} 635081Sgblack@eecs.umich.edu 645081Sgblack@eecs.umich.eduint 655081Sgblack@eecs.umich.eduProcessInfo::pid(Addr ksp) const 665081Sgblack@eecs.umich.edu{ 67 Addr task = this->task(ksp); 68 if (!task) 69 return -1; 70 71 uint16_t pd; 72 73 FSTranslatingPortProxy &vp = tc->getVirtProxy(); 74 pd = vp.read<uint16_t>(task + pid_off, GuestByteOrder); 75 76 return pd; 77} 78 79std::string 80ProcessInfo::name(Addr ksp) const 81{ 82 Addr task = this->task(ksp); 83 if (!task) 84 return "console"; 85 86 char comm[256]; 87 tc->getVirtProxy().readString(comm, task + name_off, sizeof(comm)); 88 if (!comm[0]) 89 return "startup"; 90 91 return comm; 92} 93 94StackTrace::StackTrace() 95 : tc(0), stack(64) 96{ 97} 98 99StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst) 100 : tc(0), stack(64) 101{ 102 trace(_tc, inst); 103} 104 105StackTrace::~StackTrace() 106{ 107} 108 109void 110StackTrace::trace(ThreadContext *_tc, bool is_call) 111{ 112 tc = _tc; 113 bool usermode = 0; 114 115 if (usermode) { 116 stack.push_back(user); 117 return; 118 } 119} 120 121bool 122StackTrace::isEntry(Addr addr) 123{ 124 return false; 125} 126 127bool 128StackTrace::decodeStack(MachInst inst, int &disp) 129{ 130 // lda $sp, -disp($sp) 131 // 132 // Opcode<31:26> == 0x08 133 // RA<25:21> == 30 134 // RB<20:16> == 30 135 // Disp<15:0> 136 const MachInst mem_mask = 0xffff0000; 137 const MachInst lda_pattern = 0x23de0000; 138 const MachInst lda_disp_mask = 0x0000ffff; 139 140 // subq $sp, disp, $sp 141 // addq $sp, disp, $sp 142 // 143 // Opcode<31:26> == 0x10 144 // RA<25:21> == 30 145 // Lit<20:13> 146 // One<12> = 1 147 // Func<11:5> == 0x20 (addq) 148 // Func<11:5> == 0x29 (subq) 149 // RC<4:0> == 30 150 const MachInst intop_mask = 0xffe01fff; 151 const MachInst addq_pattern = 0x43c0141e; 152 const MachInst subq_pattern = 0x43c0153e; 153 const MachInst intop_disp_mask = 0x001fe000; 154 const int intop_disp_shift = 13; 155 156 if ((inst & mem_mask) == lda_pattern) 157 disp = -sext<16>(inst & lda_disp_mask); 158 else if ((inst & intop_mask) == addq_pattern) 159 disp = -int((inst & intop_disp_mask) >> intop_disp_shift); 160 else if ((inst & intop_mask) == subq_pattern) 161 disp = int((inst & intop_disp_mask) >> intop_disp_shift); 162 else 163 return false; 164 165 return true; 166} 167 168bool 169StackTrace::decodeSave(MachInst inst, int ®, int &disp) 170{ 171 // lda $stq, disp($sp) 172 // 173 // Opcode<31:26> == 0x08 174 // RA<25:21> == ? 175 // RB<20:16> == 30 176 // Disp<15:0> 177 const MachInst stq_mask = 0xfc1f0000; 178 const MachInst stq_pattern = 0xb41e0000; 179 const MachInst stq_disp_mask = 0x0000ffff; 180 const MachInst reg_mask = 0x03e00000; 181 const int reg_shift = 21; 182 183 if ((inst & stq_mask) == stq_pattern) { 184 reg = (inst & reg_mask) >> reg_shift; 185 disp = sext<16>(inst & stq_disp_mask); 186 } else { 187 return false; 188 } 189 190 return true; 191} 192 193/* 194 * Decode the function prologue for the function we're in, and note 195 * which registers are stored where, and how large the stack frame is. 196 */ 197bool 198StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func, 199 int &size, Addr &ra) 200{ 201 size = 0; 202 ra = 0; 203 204 for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) { 205 MachInst inst = tc->getVirtProxy().read<MachInst>(pc); 206 207 int reg, disp; 208 if (decodeStack(inst, disp)) { 209 if (size) { 210 return true; 211 } 212 size += disp; 213 } else if (decodeSave(inst, reg, disp)) { 214 if (!ra && reg == ReturnAddressReg) { 215 ra = tc->getVirtProxy().read<Addr>(sp + disp); 216 if (!ra) { 217 return false; 218 } 219 } 220 } 221 } 222 223 return true; 224} 225 226#if TRACING_ON 227void 228StackTrace::dump() 229{ 230 panic("Stack trace dump not implemented.\n"); 231} 232#endif 233