registers.hh revision 6328
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Korey Sewell 30 */ 31 32#ifndef __ARCH_MIPS_REGFILE_HH__ 33#define __ARCH_MIPS_REGFILE_HH__ 34 35#include <iostream> 36#include <string> 37 38#include "arch/mips/isa_traits.hh" 39 40class BaseCPU; 41class Checkpoint; 42class EventManager; 43 44namespace MipsISA 45{ 46 const uint32_t MIPS32_QNAN = 0x7fbfffff; 47 const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff); 48 49 enum FPControlRegNums { 50 FIR = NumFloatArchRegs, 51 FCCR, 52 FEXR, 53 FENR, 54 FCSR 55 }; 56 57 enum FCSRBits { 58 Inexact = 1, 59 Underflow, 60 Overflow, 61 DivideByZero, 62 Invalid, 63 Unimplemented 64 }; 65 66 enum FCSRFields { 67 Flag_Field = 1, 68 Enable_Field = 6, 69 Cause_Field = 11 70 }; 71 72 enum MiscIntRegNums { 73 LO = NumIntArchRegs, 74 HI, 75 DSPACX0, 76 DSPLo1, 77 DSPHi1, 78 DSPACX1, 79 DSPLo2, 80 DSPHi2, 81 DSPACX2, 82 DSPLo3, 83 DSPHi3, 84 DSPACX3, 85 DSPControl, 86 DSPLo0 = LO, 87 DSPHi0 = HI 88 }; 89 90 //@TODO: Implementing ShadowSets needs to 91 //edit this value such that: 92 //TotalArchRegs = NumIntArchRegs * ShadowSets 93 const int TotalArchRegs = NumIntArchRegs; 94 95} // namespace MipsISA 96 97#endif 98