registers.hh revision 9920
12972SN/A/* 26328SN/A * Copyright (c) 2006 The Regents of The University of Michigan 36328SN/A * Copyright (c) 2007 MIPS Technologies, Inc. 45254SN/A * All rights reserved. 52972SN/A * 65254SN/A * Redistribution and use in source and binary forms, with or without 75254SN/A * modification, are permitted provided that the following conditions are 85254SN/A * met: redistributions of source code must retain the above copyright 95254SN/A * notice, this list of conditions and the following disclaimer; 105254SN/A * redistributions in binary form must reproduce the above copyright 115254SN/A * notice, this list of conditions and the following disclaimer in the 125254SN/A * documentation and/or other materials provided with the distribution; 135254SN/A * neither the name of the copyright holders nor the names of its 145254SN/A * contributors may be used to endorse or promote products derived from 155254SN/A * this software without specific prior written permission. 162972SN/A * 175254SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285222SN/A * 296328SN/A * Authors: Korey Sewell 302972SN/A */ 312972SN/A 326329Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_REGISTERS_HH__ 336329Sgblack@eecs.umich.edu#define __ARCH_MIPS_REGISTERS_HH__ 342972SN/A 358961Sgblack@eecs.umich.edu#include "arch/mips/generated/max_inst_regs.hh" 366329Sgblack@eecs.umich.edu#include "base/misc.hh" 376329Sgblack@eecs.umich.edu#include "base/types.hh" 386328SN/A 396329Sgblack@eecs.umich.educlass ThreadContext; 406328SN/A 416328SN/Anamespace MipsISA 426328SN/A{ 436328SN/A 446329Sgblack@eecs.umich.eduusing MipsISAInst::MaxInstSrcRegs; 456329Sgblack@eecs.umich.eduusing MipsISAInst::MaxInstDestRegs; 469046SAli.Saidi@ARM.comusing MipsISAInst::MaxMiscDestRegs; 476328SN/A 486329Sgblack@eecs.umich.edu// Constants Related to the number of registers 496329Sgblack@eecs.umich.educonst int NumIntArchRegs = 32; 506329Sgblack@eecs.umich.educonst int NumIntSpecialRegs = 9; 516329Sgblack@eecs.umich.educonst int NumFloatArchRegs = 32; 526329Sgblack@eecs.umich.educonst int NumFloatSpecialRegs = 5; 536328SN/A 546329Sgblack@eecs.umich.educonst int MaxShadowRegSets = 16; // Maximum number of shadow register sets 556329Sgblack@eecs.umich.educonst int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 566329Sgblack@eecs.umich.educonst int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 579920Syasuko.eckert@amd.comconst int NumCCRegs = 0; 586328SN/A 596329Sgblack@eecs.umich.educonst uint32_t MIPS32_QNAN = 0x7fbfffff; 608694Sguodeyuan@tsinghua.org.cnconst uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); 616328SN/A 626329Sgblack@eecs.umich.eduenum FPControlRegNums { 636383Sgblack@eecs.umich.edu FLOATREG_FIR = NumFloatArchRegs, 646383Sgblack@eecs.umich.edu FLOATREG_FCCR, 656383Sgblack@eecs.umich.edu FLOATREG_FEXR, 666383Sgblack@eecs.umich.edu FLOATREG_FENR, 676383Sgblack@eecs.umich.edu FLOATREG_FCSR 686329Sgblack@eecs.umich.edu}; 696329Sgblack@eecs.umich.edu 706329Sgblack@eecs.umich.eduenum FCSRBits { 716329Sgblack@eecs.umich.edu Inexact = 1, 726329Sgblack@eecs.umich.edu Underflow, 736329Sgblack@eecs.umich.edu Overflow, 746329Sgblack@eecs.umich.edu DivideByZero, 756329Sgblack@eecs.umich.edu Invalid, 766329Sgblack@eecs.umich.edu Unimplemented 776329Sgblack@eecs.umich.edu}; 786329Sgblack@eecs.umich.edu 796329Sgblack@eecs.umich.eduenum FCSRFields { 806329Sgblack@eecs.umich.edu Flag_Field = 1, 816329Sgblack@eecs.umich.edu Enable_Field = 6, 826329Sgblack@eecs.umich.edu Cause_Field = 11 836329Sgblack@eecs.umich.edu}; 846329Sgblack@eecs.umich.edu 856329Sgblack@eecs.umich.eduenum MiscIntRegNums { 866383Sgblack@eecs.umich.edu INTREG_LO = NumIntArchRegs, 876383Sgblack@eecs.umich.edu INTREG_DSP_LO0 = INTREG_LO, 886383Sgblack@eecs.umich.edu INTREG_HI, 896383Sgblack@eecs.umich.edu INTREG_DSP_HI0 = INTREG_HI, 906383Sgblack@eecs.umich.edu INTREG_DSP_ACX0, 916383Sgblack@eecs.umich.edu INTREG_DSP_LO1, 926383Sgblack@eecs.umich.edu INTREG_DSP_HI1, 936383Sgblack@eecs.umich.edu INTREG_DSP_ACX1, 946383Sgblack@eecs.umich.edu INTREG_DSP_LO2, 956383Sgblack@eecs.umich.edu INTREG_DSP_HI2, 966383Sgblack@eecs.umich.edu INTREG_DSP_ACX2, 976383Sgblack@eecs.umich.edu INTREG_DSP_LO3, 986383Sgblack@eecs.umich.edu INTREG_DSP_HI3, 996383Sgblack@eecs.umich.edu INTREG_DSP_ACX3, 1006383Sgblack@eecs.umich.edu INTREG_DSP_CONTROL 1016329Sgblack@eecs.umich.edu}; 1026329Sgblack@eecs.umich.edu 1036329Sgblack@eecs.umich.edu// semantically meaningful register indices 1046329Sgblack@eecs.umich.educonst int ZeroReg = 0; 1056329Sgblack@eecs.umich.educonst int AssemblerReg = 1; 1066329Sgblack@eecs.umich.educonst int SyscallSuccessReg = 7; 1076329Sgblack@eecs.umich.educonst int FirstArgumentReg = 4; 1086329Sgblack@eecs.umich.educonst int ReturnValueReg = 2; 1096329Sgblack@eecs.umich.edu 1106329Sgblack@eecs.umich.educonst int KernelReg0 = 26; 1116329Sgblack@eecs.umich.educonst int KernelReg1 = 27; 1126329Sgblack@eecs.umich.educonst int GlobalPointerReg = 28; 1136329Sgblack@eecs.umich.educonst int StackPointerReg = 29; 1146329Sgblack@eecs.umich.educonst int FramePointerReg = 30; 1156329Sgblack@eecs.umich.educonst int ReturnAddressReg = 31; 1166329Sgblack@eecs.umich.edu 1176329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = 3; 1186329Sgblack@eecs.umich.edu 1196329Sgblack@eecs.umich.edu// Enumerate names for 'Control' Registers in the CPU 1206329Sgblack@eecs.umich.edu// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 1216329Sgblack@eecs.umich.edu// (Register Number-Register Select) Summary of Register 1226329Sgblack@eecs.umich.edu//------------------------------------------------------ 1236329Sgblack@eecs.umich.edu// The first set of names classify the CP0 names as Register Banks 1246329Sgblack@eecs.umich.edu// for easy indexing when using the 'RD + SEL' index combination 1256329Sgblack@eecs.umich.edu// in CP0 instructions. 1266383Sgblack@eecs.umich.eduenum MiscRegIndex{ 1276383Sgblack@eecs.umich.edu MISCREG_INDEX = 0, //Bank 0: 0 - 3 1286383Sgblack@eecs.umich.edu MISCREG_MVP_CONTROL, 1296383Sgblack@eecs.umich.edu MISCREG_MVP_CONF0, 1306383Sgblack@eecs.umich.edu MISCREG_MVP_CONF1, 1316329Sgblack@eecs.umich.edu 1326383Sgblack@eecs.umich.edu MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15 1336383Sgblack@eecs.umich.edu MISCREG_VPE_CONTROL, 1346383Sgblack@eecs.umich.edu MISCREG_VPE_CONF0, 1356383Sgblack@eecs.umich.edu MISCREG_VPE_CONF1, 1366383Sgblack@eecs.umich.edu MISCREG_YQMASK, 1376383Sgblack@eecs.umich.edu MISCREG_VPE_SCHEDULE, 1386383Sgblack@eecs.umich.edu MISCREG_VPE_SCHEFBACK, 1396383Sgblack@eecs.umich.edu MISCREG_VPE_OPT, 1406329Sgblack@eecs.umich.edu 1416383Sgblack@eecs.umich.edu MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23 1426383Sgblack@eecs.umich.edu MISCREG_TC_STATUS, 1436383Sgblack@eecs.umich.edu MISCREG_TC_BIND, 1446383Sgblack@eecs.umich.edu MISCREG_TC_RESTART, 1456383Sgblack@eecs.umich.edu MISCREG_TC_HALT, 1466383Sgblack@eecs.umich.edu MISCREG_TC_CONTEXT, 1476383Sgblack@eecs.umich.edu MISCREG_TC_SCHEDULE, 1486383Sgblack@eecs.umich.edu MISCREG_TC_SCHEFBACK, 1496329Sgblack@eecs.umich.edu 1506383Sgblack@eecs.umich.edu MISCREG_ENTRYLO1 = 24, // Bank 3: 24 1516329Sgblack@eecs.umich.edu 1526383Sgblack@eecs.umich.edu MISCREG_CONTEXT = 32, // Bank 4: 32 - 33 1536383Sgblack@eecs.umich.edu MISCREG_CONTEXT_CONFIG, 1546329Sgblack@eecs.umich.edu 1556383Sgblack@eecs.umich.edu MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41 1566383Sgblack@eecs.umich.edu MISCREG_PAGEGRAIN = 41, 1576329Sgblack@eecs.umich.edu 1586383Sgblack@eecs.umich.edu MISCREG_WIRED = 48, //Bank 6:48-55 1596383Sgblack@eecs.umich.edu MISCREG_SRS_CONF0, 1606383Sgblack@eecs.umich.edu MISCREG_SRS_CONF1, 1616383Sgblack@eecs.umich.edu MISCREG_SRS_CONF2, 1626383Sgblack@eecs.umich.edu MISCREG_SRS_CONF3, 1636383Sgblack@eecs.umich.edu MISCREG_SRS_CONF4, 1646329Sgblack@eecs.umich.edu 1656383Sgblack@eecs.umich.edu MISCREG_HWRENA = 56, //Bank 7: 56-63 1666329Sgblack@eecs.umich.edu 1676383Sgblack@eecs.umich.edu MISCREG_BADVADDR = 64, //Bank 8: 64-71 1686329Sgblack@eecs.umich.edu 1696383Sgblack@eecs.umich.edu MISCREG_COUNT = 72, //Bank 9: 72-79 1706329Sgblack@eecs.umich.edu 1716383Sgblack@eecs.umich.edu MISCREG_ENTRYHI = 80, //Bank 10: 80-87 1726329Sgblack@eecs.umich.edu 1736383Sgblack@eecs.umich.edu MISCREG_COMPARE = 88, //Bank 11: 88-95 1746329Sgblack@eecs.umich.edu 1756383Sgblack@eecs.umich.edu MISCREG_STATUS = 96, //Bank 12: 96-103 1766383Sgblack@eecs.umich.edu MISCREG_INTCTL, 1776383Sgblack@eecs.umich.edu MISCREG_SRSCTL, 1786383Sgblack@eecs.umich.edu MISCREG_SRSMAP, 1796329Sgblack@eecs.umich.edu 1806383Sgblack@eecs.umich.edu MISCREG_CAUSE = 104, //Bank 13: 104-111 1816329Sgblack@eecs.umich.edu 1826383Sgblack@eecs.umich.edu MISCREG_EPC = 112, //Bank 14: 112-119 1836329Sgblack@eecs.umich.edu 1846383Sgblack@eecs.umich.edu MISCREG_PRID = 120, //Bank 15: 120-127, 1856383Sgblack@eecs.umich.edu MISCREG_EBASE, 1866329Sgblack@eecs.umich.edu 1876383Sgblack@eecs.umich.edu MISCREG_CONFIG = 128, //Bank 16: 128-135 1886383Sgblack@eecs.umich.edu MISCREG_CONFIG1, 1896383Sgblack@eecs.umich.edu MISCREG_CONFIG2, 1906383Sgblack@eecs.umich.edu MISCREG_CONFIG3, 1916383Sgblack@eecs.umich.edu MISCREG_CONFIG4, 1926383Sgblack@eecs.umich.edu MISCREG_CONFIG5, 1936383Sgblack@eecs.umich.edu MISCREG_CONFIG6, 1946383Sgblack@eecs.umich.edu MISCREG_CONFIG7, 1956329Sgblack@eecs.umich.edu 1966329Sgblack@eecs.umich.edu 1976383Sgblack@eecs.umich.edu MISCREG_LLADDR = 136, //Bank 17: 136-143 1986329Sgblack@eecs.umich.edu 1996383Sgblack@eecs.umich.edu MISCREG_WATCHLO0 = 144, //Bank 18: 144-151 2006383Sgblack@eecs.umich.edu MISCREG_WATCHLO1, 2016383Sgblack@eecs.umich.edu MISCREG_WATCHLO2, 2026383Sgblack@eecs.umich.edu MISCREG_WATCHLO3, 2036383Sgblack@eecs.umich.edu MISCREG_WATCHLO4, 2046383Sgblack@eecs.umich.edu MISCREG_WATCHLO5, 2056383Sgblack@eecs.umich.edu MISCREG_WATCHLO6, 2066383Sgblack@eecs.umich.edu MISCREG_WATCHLO7, 2076329Sgblack@eecs.umich.edu 2086383Sgblack@eecs.umich.edu MISCREG_WATCHHI0 = 152, //Bank 19: 152-159 2096383Sgblack@eecs.umich.edu MISCREG_WATCHHI1, 2106383Sgblack@eecs.umich.edu MISCREG_WATCHHI2, 2116383Sgblack@eecs.umich.edu MISCREG_WATCHHI3, 2126383Sgblack@eecs.umich.edu MISCREG_WATCHHI4, 2136383Sgblack@eecs.umich.edu MISCREG_WATCHHI5, 2146383Sgblack@eecs.umich.edu MISCREG_WATCHHI6, 2156383Sgblack@eecs.umich.edu MISCREG_WATCHHI7, 2166329Sgblack@eecs.umich.edu 2176383Sgblack@eecs.umich.edu MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167 2186329Sgblack@eecs.umich.edu 2196329Sgblack@eecs.umich.edu //Bank 21: 168-175 2206329Sgblack@eecs.umich.edu 2216329Sgblack@eecs.umich.edu //Bank 22: 176-183 2226329Sgblack@eecs.umich.edu 2236383Sgblack@eecs.umich.edu MISCREG_DEBUG = 184, //Bank 23: 184-191 2246383Sgblack@eecs.umich.edu MISCREG_TRACE_CONTROL1, 2256383Sgblack@eecs.umich.edu MISCREG_TRACE_CONTROL2, 2266383Sgblack@eecs.umich.edu MISCREG_USER_TRACE_DATA, 2276383Sgblack@eecs.umich.edu MISCREG_TRACE_BPC, 2286329Sgblack@eecs.umich.edu 2296383Sgblack@eecs.umich.edu MISCREG_DEPC = 192, //Bank 24: 192-199 2306329Sgblack@eecs.umich.edu 2316383Sgblack@eecs.umich.edu MISCREG_PERFCNT0 = 200, //Bank 25: 200-207 2326383Sgblack@eecs.umich.edu MISCREG_PERFCNT1, 2336383Sgblack@eecs.umich.edu MISCREG_PERFCNT2, 2346383Sgblack@eecs.umich.edu MISCREG_PERFCNT3, 2356383Sgblack@eecs.umich.edu MISCREG_PERFCNT4, 2366383Sgblack@eecs.umich.edu MISCREG_PERFCNT5, 2376383Sgblack@eecs.umich.edu MISCREG_PERFCNT6, 2386383Sgblack@eecs.umich.edu MISCREG_PERFCNT7, 2396329Sgblack@eecs.umich.edu 2406383Sgblack@eecs.umich.edu MISCREG_ERRCTL = 208, //Bank 26: 208-215 2416329Sgblack@eecs.umich.edu 2426383Sgblack@eecs.umich.edu MISCREG_CACHEERR0 = 216, //Bank 27: 216-223 2436383Sgblack@eecs.umich.edu MISCREG_CACHEERR1, 2446383Sgblack@eecs.umich.edu MISCREG_CACHEERR2, 2456383Sgblack@eecs.umich.edu MISCREG_CACHEERR3, 2466329Sgblack@eecs.umich.edu 2476383Sgblack@eecs.umich.edu MISCREG_TAGLO0 = 224, //Bank 28: 224-231 2486383Sgblack@eecs.umich.edu MISCREG_DATALO1, 2496383Sgblack@eecs.umich.edu MISCREG_TAGLO2, 2506383Sgblack@eecs.umich.edu MISCREG_DATALO3, 2516383Sgblack@eecs.umich.edu MISCREG_TAGLO4, 2526383Sgblack@eecs.umich.edu MISCREG_DATALO5, 2536383Sgblack@eecs.umich.edu MISCREG_TAGLO6, 2546383Sgblack@eecs.umich.edu MISCREG_DATALO7, 2556329Sgblack@eecs.umich.edu 2566383Sgblack@eecs.umich.edu MISCREG_TAGHI0 = 232, //Bank 29: 232-239 2576383Sgblack@eecs.umich.edu MISCREG_DATAHI1, 2586383Sgblack@eecs.umich.edu MISCREG_TAGHI2, 2596383Sgblack@eecs.umich.edu MISCREG_DATAHI3, 2606383Sgblack@eecs.umich.edu MISCREG_TAGHI4, 2616383Sgblack@eecs.umich.edu MISCREG_DATAHI5, 2626383Sgblack@eecs.umich.edu MISCREG_TAGHI6, 2636383Sgblack@eecs.umich.edu MISCREG_DATAHI7, 2646329Sgblack@eecs.umich.edu 2656329Sgblack@eecs.umich.edu 2666383Sgblack@eecs.umich.edu MISCREG_ERROR_EPC = 240, //Bank 30: 240-247 2676329Sgblack@eecs.umich.edu 2686383Sgblack@eecs.umich.edu MISCREG_DESAVE = 248, //Bank 31: 248-256 2696329Sgblack@eecs.umich.edu 2706383Sgblack@eecs.umich.edu MISCREG_LLFLAG = 257, 2716807Sgblack@eecs.umich.edu MISCREG_TP_VALUE, 2726329Sgblack@eecs.umich.edu 2736383Sgblack@eecs.umich.edu MISCREG_NUMREGS 2746329Sgblack@eecs.umich.edu}; 2756329Sgblack@eecs.umich.edu 2769917Ssteve.reinhardt@amd.comconst int NumMiscRegs = MISCREG_NUMREGS; 2776329Sgblack@eecs.umich.edu 2789917Ssteve.reinhardt@amd.com// These help enumerate all the registers for dependence tracking. 2799918Ssteve.reinhardt@amd.comconst int FP_Reg_Base = NumIntRegs; 2809920Syasuko.eckert@amd.comconst int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; 2819920Syasuko.eckert@amd.comconst int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 2829918Ssteve.reinhardt@amd.comconst int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; 2836329Sgblack@eecs.umich.edu 2846329Sgblack@eecs.umich.educonst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 2856329Sgblack@eecs.umich.edu 2866329Sgblack@eecs.umich.edutypedef uint16_t RegIndex; 2876329Sgblack@eecs.umich.edu 2886329Sgblack@eecs.umich.edutypedef uint32_t IntReg; 2896329Sgblack@eecs.umich.edu 2906329Sgblack@eecs.umich.edu// floating point register file entry type 2916329Sgblack@eecs.umich.edutypedef uint32_t FloatRegBits; 2926329Sgblack@eecs.umich.edutypedef float FloatReg; 2936329Sgblack@eecs.umich.edu 2946329Sgblack@eecs.umich.edu// cop-0/cop-1 system control register 2956329Sgblack@eecs.umich.edutypedef uint64_t MiscReg; 2966329Sgblack@eecs.umich.edu 2979920Syasuko.eckert@amd.com// dummy typedef since we don't have CC regs 2989920Syasuko.eckert@amd.comtypedef uint8_t CCReg; 2999920Syasuko.eckert@amd.com 3006329Sgblack@eecs.umich.edutypedef union { 3016329Sgblack@eecs.umich.edu IntReg intreg; 3026329Sgblack@eecs.umich.edu FloatReg fpreg; 3036329Sgblack@eecs.umich.edu MiscReg ctrlreg; 3046329Sgblack@eecs.umich.edu} AnyReg; 3056328SN/A 3066328SN/A} // namespace MipsISA 3072972SN/A 3082972SN/A#endif 309