registers.hh revision 6329 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Korey Sewell
30 */
31
32#ifndef __ARCH_MIPS_REGISTERS_HH__
33#define __ARCH_MIPS_REGISTERS_HH__
34
35#include "arch/mips/max_inst_regs.hh"
36#include "base/misc.hh"
37#include "base/types.hh"
38
39class ThreadContext;
40
41namespace MipsISA
42{
43
44using MipsISAInst::MaxInstSrcRegs;
45using MipsISAInst::MaxInstDestRegs;
46
47// Constants Related to the number of registers
48const int NumIntArchRegs = 32;
49const int NumIntSpecialRegs = 9;
50const int NumFloatArchRegs = 32;
51const int NumFloatSpecialRegs = 5;
52
53const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
54const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
55const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
56
57const uint32_t MIPS32_QNAN = 0x7fbfffff;
58const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
59
60enum FPControlRegNums {
61   FIR = NumFloatArchRegs,
62   FCCR,
63   FEXR,
64   FENR,
65   FCSR
66};
67
68enum FCSRBits {
69    Inexact = 1,
70    Underflow,
71    Overflow,
72    DivideByZero,
73    Invalid,
74    Unimplemented
75};
76
77enum FCSRFields {
78    Flag_Field = 1,
79    Enable_Field = 6,
80    Cause_Field = 11
81};
82
83enum MiscIntRegNums {
84   LO = NumIntArchRegs,
85   HI,
86   DSPACX0,
87   DSPLo1,
88   DSPHi1,
89   DSPACX1,
90   DSPLo2,
91   DSPHi2,
92   DSPACX2,
93   DSPLo3,
94   DSPHi3,
95   DSPACX3,
96   DSPControl,
97   DSPLo0 = LO,
98   DSPHi0 = HI
99};
100
101// semantically meaningful register indices
102const int ZeroReg = 0;
103const int AssemblerReg = 1;
104const int SyscallSuccessReg = 7;
105const int FirstArgumentReg = 4;
106const int ReturnValueReg = 2;
107
108const int KernelReg0 = 26;
109const int KernelReg1 = 27;
110const int GlobalPointerReg = 28;
111const int StackPointerReg = 29;
112const int FramePointerReg = 30;
113const int ReturnAddressReg = 31;
114
115const int SyscallPseudoReturnReg = 3;
116
117//@TODO: Implementing ShadowSets needs to
118//edit this value such that:
119//TotalArchRegs = NumIntArchRegs * ShadowSets
120const int TotalArchRegs = NumIntArchRegs;
121
122// These help enumerate all the registers for dependence tracking.
123const int FP_Base_DepTag = NumIntRegs;
124const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
125
126// Enumerate names for 'Control' Registers in the CPU
127// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
128// (Register Number-Register Select) Summary of Register
129//------------------------------------------------------
130// The first set of names classify the CP0 names as Register Banks
131// for easy indexing when using the 'RD + SEL' index combination
132// in CP0 instructions.
133enum MiscRegTags {
134    Index = Ctrl_Base_DepTag + 0,       //Bank 0: 0 - 3
135    MVPControl,
136    MVPConf0,
137    MVPConf1,
138
139    CP0_Random = Ctrl_Base_DepTag + 8,      //Bank 1: 8 - 15
140    VPEControl,
141    VPEConf0,
142    VPEConf1,
143    YQMask,
144    VPESchedule,
145    VPEScheFBack,
146    VPEOpt,
147
148    EntryLo0 = Ctrl_Base_DepTag + 16,   //Bank 2: 16 - 23
149    TCStatus,
150    TCBind,
151    TCRestart,
152    TCHalt,
153    TCContext,
154    TCSchedule,
155    TCScheFBack,
156
157    EntryLo1 = Ctrl_Base_DepTag + 24,   // Bank 3: 24
158
159    Context = Ctrl_Base_DepTag + 32,    // Bank 4: 32 - 33
160    ContextConfig,
161
162    PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
163    PageGrain = Ctrl_Base_DepTag + 41,
164
165    Wired = Ctrl_Base_DepTag + 48,          //Bank 6:48-55
166    SRSConf0,
167    SRSConf1,
168    SRSConf2,
169    SRSConf3,
170    SRSConf4,
171
172    HWRena = Ctrl_Base_DepTag + 56,         //Bank 7: 56-63
173
174    BadVAddr = Ctrl_Base_DepTag + 64,       //Bank 8: 64-71
175
176    Count = Ctrl_Base_DepTag + 72,          //Bank 9: 72-79
177
178    EntryHi = Ctrl_Base_DepTag + 80,        //Bank 10: 80-87
179
180    Compare = Ctrl_Base_DepTag + 88,        //Bank 11: 88-95
181
182    Status = Ctrl_Base_DepTag + 96,         //Bank 12: 96-103
183    IntCtl,
184    SRSCtl,
185    SRSMap,
186
187    Cause = Ctrl_Base_DepTag + 104,         //Bank 13: 104-111
188
189    EPC = Ctrl_Base_DepTag + 112,           //Bank 14: 112-119
190
191    PRId = Ctrl_Base_DepTag + 120,          //Bank 15: 120-127,
192    EBase,
193
194    Config = Ctrl_Base_DepTag + 128,        //Bank 16: 128-135
195    Config1,
196    Config2,
197    Config3,
198    Config4,
199    Config5,
200    Config6,
201    Config7,
202
203
204    LLAddr = Ctrl_Base_DepTag + 136,        //Bank 17: 136-143
205
206    WatchLo0 = Ctrl_Base_DepTag + 144,      //Bank 18: 144-151
207    WatchLo1,
208    WatchLo2,
209    WatchLo3,
210    WatchLo4,
211    WatchLo5,
212    WatchLo6,
213    WatchLo7,
214
215    WatchHi0 = Ctrl_Base_DepTag + 152,     //Bank 19: 152-159
216    WatchHi1,
217    WatchHi2,
218    WatchHi3,
219    WatchHi4,
220    WatchHi5,
221    WatchHi6,
222    WatchHi7,
223
224    XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
225
226                       //Bank 21: 168-175
227
228                       //Bank 22: 176-183
229
230    Debug = Ctrl_Base_DepTag + 184,       //Bank 23: 184-191
231    TraceControl1,
232    TraceControl2,
233    UserTraceData,
234    TraceBPC,
235
236    DEPC = Ctrl_Base_DepTag + 192,        //Bank 24: 192-199
237
238    PerfCnt0 = Ctrl_Base_DepTag + 200,    //Bank 25: 200-207
239    PerfCnt1,
240    PerfCnt2,
241    PerfCnt3,
242    PerfCnt4,
243    PerfCnt5,
244    PerfCnt6,
245    PerfCnt7,
246
247    ErrCtl = Ctrl_Base_DepTag + 208,      //Bank 26: 208-215
248
249    CacheErr0 = Ctrl_Base_DepTag + 216,   //Bank 27: 216-223
250    CacheErr1,
251    CacheErr2,
252    CacheErr3,
253
254    TagLo0 = Ctrl_Base_DepTag + 224,      //Bank 28: 224-231
255    DataLo1,
256    TagLo2,
257    DataLo3,
258    TagLo4,
259    DataLo5,
260    TagLo6,
261    DataLo7,
262
263    TagHi0 = Ctrl_Base_DepTag + 232,      //Bank 29: 232-239
264    DataHi1,
265    TagHi2,
266    DataHi3,
267    TagHi4,
268    DataHi5,
269    TagHi6,
270    DataHi7,
271
272
273    ErrorEPC = Ctrl_Base_DepTag + 240,    //Bank 30: 240-247
274
275    DESAVE = Ctrl_Base_DepTag + 248,       //Bank 31: 248-256
276
277    LLFlag = Ctrl_Base_DepTag + 257,
278
279    NumControlRegs
280};
281
282const int TotalDataRegs = NumIntRegs + NumFloatRegs;
283
284const int NumMiscRegs = NumControlRegs;
285
286const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
287
288typedef uint16_t  RegIndex;
289
290typedef uint32_t IntReg;
291
292// floating point register file entry type
293typedef uint32_t FloatRegBits;
294typedef float FloatReg;
295
296// cop-0/cop-1 system control register
297typedef uint64_t MiscReg;
298
299typedef union {
300    IntReg   intreg;
301    FloatReg fpreg;
302    MiscReg  ctrlreg;
303} AnyReg;
304
305} // namespace MipsISA
306
307#endif
308