registers.hh revision 13556
12972SN/A/* 26328SN/A * Copyright (c) 2006 The Regents of The University of Michigan 36328SN/A * Copyright (c) 2007 MIPS Technologies, Inc. 45254SN/A * All rights reserved. 52972SN/A * 65254SN/A * Redistribution and use in source and binary forms, with or without 75254SN/A * modification, are permitted provided that the following conditions are 85254SN/A * met: redistributions of source code must retain the above copyright 95254SN/A * notice, this list of conditions and the following disclaimer; 105254SN/A * redistributions in binary form must reproduce the above copyright 115254SN/A * notice, this list of conditions and the following disclaimer in the 125254SN/A * documentation and/or other materials provided with the distribution; 135254SN/A * neither the name of the copyright holders nor the names of its 145254SN/A * contributors may be used to endorse or promote products derived from 155254SN/A * this software without specific prior written permission. 162972SN/A * 175254SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185254SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195254SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205254SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215254SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225254SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235254SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245254SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255254SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265254SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275254SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285222SN/A * 296328SN/A * Authors: Korey Sewell 302972SN/A */ 312972SN/A 326329Sgblack@eecs.umich.edu#ifndef __ARCH_MIPS_REGISTERS_HH__ 336329Sgblack@eecs.umich.edu#define __ARCH_MIPS_REGISTERS_HH__ 342972SN/A 3512109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/vec_reg.hh" 368961Sgblack@eecs.umich.edu#include "arch/mips/generated/max_inst_regs.hh" 3712334Sgabeblack@google.com#include "base/logging.hh" 386329Sgblack@eecs.umich.edu#include "base/types.hh" 396328SN/A 406329Sgblack@eecs.umich.educlass ThreadContext; 416328SN/A 426328SN/Anamespace MipsISA 436328SN/A{ 446328SN/A 456329Sgblack@eecs.umich.eduusing MipsISAInst::MaxInstSrcRegs; 466329Sgblack@eecs.umich.eduusing MipsISAInst::MaxInstDestRegs; 479046SAli.Saidi@ARM.comusing MipsISAInst::MaxMiscDestRegs; 486328SN/A 496329Sgblack@eecs.umich.edu// Constants Related to the number of registers 506329Sgblack@eecs.umich.educonst int NumIntArchRegs = 32; 516329Sgblack@eecs.umich.educonst int NumIntSpecialRegs = 9; 526329Sgblack@eecs.umich.educonst int NumFloatArchRegs = 32; 536329Sgblack@eecs.umich.educonst int NumFloatSpecialRegs = 5; 546328SN/A 556329Sgblack@eecs.umich.educonst int MaxShadowRegSets = 16; // Maximum number of shadow register sets 566329Sgblack@eecs.umich.educonst int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 576329Sgblack@eecs.umich.educonst int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 589920Syasuko.eckert@amd.comconst int NumCCRegs = 0; 596328SN/A 606329Sgblack@eecs.umich.educonst uint32_t MIPS32_QNAN = 0x7fbfffff; 618694Sguodeyuan@tsinghua.org.cnconst uint64_t MIPS64_QNAN = ULL(0x7ff7ffffffffffff); 626328SN/A 636329Sgblack@eecs.umich.eduenum FPControlRegNums { 646383Sgblack@eecs.umich.edu FLOATREG_FIR = NumFloatArchRegs, 656383Sgblack@eecs.umich.edu FLOATREG_FCCR, 666383Sgblack@eecs.umich.edu FLOATREG_FEXR, 676383Sgblack@eecs.umich.edu FLOATREG_FENR, 686383Sgblack@eecs.umich.edu FLOATREG_FCSR 696329Sgblack@eecs.umich.edu}; 706329Sgblack@eecs.umich.edu 716329Sgblack@eecs.umich.eduenum FCSRBits { 726329Sgblack@eecs.umich.edu Inexact = 1, 736329Sgblack@eecs.umich.edu Underflow, 746329Sgblack@eecs.umich.edu Overflow, 756329Sgblack@eecs.umich.edu DivideByZero, 766329Sgblack@eecs.umich.edu Invalid, 776329Sgblack@eecs.umich.edu Unimplemented 786329Sgblack@eecs.umich.edu}; 796329Sgblack@eecs.umich.edu 806329Sgblack@eecs.umich.eduenum FCSRFields { 816329Sgblack@eecs.umich.edu Flag_Field = 1, 826329Sgblack@eecs.umich.edu Enable_Field = 6, 836329Sgblack@eecs.umich.edu Cause_Field = 11 846329Sgblack@eecs.umich.edu}; 856329Sgblack@eecs.umich.edu 866329Sgblack@eecs.umich.eduenum MiscIntRegNums { 876383Sgblack@eecs.umich.edu INTREG_LO = NumIntArchRegs, 886383Sgblack@eecs.umich.edu INTREG_DSP_LO0 = INTREG_LO, 896383Sgblack@eecs.umich.edu INTREG_HI, 906383Sgblack@eecs.umich.edu INTREG_DSP_HI0 = INTREG_HI, 916383Sgblack@eecs.umich.edu INTREG_DSP_ACX0, 926383Sgblack@eecs.umich.edu INTREG_DSP_LO1, 936383Sgblack@eecs.umich.edu INTREG_DSP_HI1, 946383Sgblack@eecs.umich.edu INTREG_DSP_ACX1, 956383Sgblack@eecs.umich.edu INTREG_DSP_LO2, 966383Sgblack@eecs.umich.edu INTREG_DSP_HI2, 976383Sgblack@eecs.umich.edu INTREG_DSP_ACX2, 986383Sgblack@eecs.umich.edu INTREG_DSP_LO3, 996383Sgblack@eecs.umich.edu INTREG_DSP_HI3, 1006383Sgblack@eecs.umich.edu INTREG_DSP_ACX3, 1016383Sgblack@eecs.umich.edu INTREG_DSP_CONTROL 1026329Sgblack@eecs.umich.edu}; 1036329Sgblack@eecs.umich.edu 1046329Sgblack@eecs.umich.edu// semantically meaningful register indices 1056329Sgblack@eecs.umich.educonst int ZeroReg = 0; 1066329Sgblack@eecs.umich.educonst int AssemblerReg = 1; 1076329Sgblack@eecs.umich.educonst int SyscallSuccessReg = 7; 1086329Sgblack@eecs.umich.educonst int FirstArgumentReg = 4; 1096329Sgblack@eecs.umich.educonst int ReturnValueReg = 2; 1106329Sgblack@eecs.umich.edu 1116329Sgblack@eecs.umich.educonst int KernelReg0 = 26; 1126329Sgblack@eecs.umich.educonst int KernelReg1 = 27; 1136329Sgblack@eecs.umich.educonst int GlobalPointerReg = 28; 1146329Sgblack@eecs.umich.educonst int StackPointerReg = 29; 1156329Sgblack@eecs.umich.educonst int FramePointerReg = 30; 1166329Sgblack@eecs.umich.educonst int ReturnAddressReg = 31; 1176329Sgblack@eecs.umich.edu 1186329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = 3; 1196329Sgblack@eecs.umich.edu 1206329Sgblack@eecs.umich.edu// Enumerate names for 'Control' Registers in the CPU 1216329Sgblack@eecs.umich.edu// Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8 1226329Sgblack@eecs.umich.edu// (Register Number-Register Select) Summary of Register 1236329Sgblack@eecs.umich.edu//------------------------------------------------------ 1246329Sgblack@eecs.umich.edu// The first set of names classify the CP0 names as Register Banks 1256329Sgblack@eecs.umich.edu// for easy indexing when using the 'RD + SEL' index combination 1266329Sgblack@eecs.umich.edu// in CP0 instructions. 1276383Sgblack@eecs.umich.eduenum MiscRegIndex{ 1286383Sgblack@eecs.umich.edu MISCREG_INDEX = 0, //Bank 0: 0 - 3 1296383Sgblack@eecs.umich.edu MISCREG_MVP_CONTROL, 1306383Sgblack@eecs.umich.edu MISCREG_MVP_CONF0, 1316383Sgblack@eecs.umich.edu MISCREG_MVP_CONF1, 1326329Sgblack@eecs.umich.edu 1336383Sgblack@eecs.umich.edu MISCREG_CP0_RANDOM = 8, //Bank 1: 8 - 15 1346383Sgblack@eecs.umich.edu MISCREG_VPE_CONTROL, 1356383Sgblack@eecs.umich.edu MISCREG_VPE_CONF0, 1366383Sgblack@eecs.umich.edu MISCREG_VPE_CONF1, 1376383Sgblack@eecs.umich.edu MISCREG_YQMASK, 1386383Sgblack@eecs.umich.edu MISCREG_VPE_SCHEDULE, 1396383Sgblack@eecs.umich.edu MISCREG_VPE_SCHEFBACK, 1406383Sgblack@eecs.umich.edu MISCREG_VPE_OPT, 1416329Sgblack@eecs.umich.edu 1426383Sgblack@eecs.umich.edu MISCREG_ENTRYLO0 = 16, //Bank 2: 16 - 23 1436383Sgblack@eecs.umich.edu MISCREG_TC_STATUS, 1446383Sgblack@eecs.umich.edu MISCREG_TC_BIND, 1456383Sgblack@eecs.umich.edu MISCREG_TC_RESTART, 1466383Sgblack@eecs.umich.edu MISCREG_TC_HALT, 1476383Sgblack@eecs.umich.edu MISCREG_TC_CONTEXT, 1486383Sgblack@eecs.umich.edu MISCREG_TC_SCHEDULE, 1496383Sgblack@eecs.umich.edu MISCREG_TC_SCHEFBACK, 1506329Sgblack@eecs.umich.edu 1516383Sgblack@eecs.umich.edu MISCREG_ENTRYLO1 = 24, // Bank 3: 24 1526329Sgblack@eecs.umich.edu 1536383Sgblack@eecs.umich.edu MISCREG_CONTEXT = 32, // Bank 4: 32 - 33 1546383Sgblack@eecs.umich.edu MISCREG_CONTEXT_CONFIG, 1556329Sgblack@eecs.umich.edu 1566383Sgblack@eecs.umich.edu MISCREG_PAGEMASK = 40, //Bank 5: 40 - 41 1576383Sgblack@eecs.umich.edu MISCREG_PAGEGRAIN = 41, 1586329Sgblack@eecs.umich.edu 1596383Sgblack@eecs.umich.edu MISCREG_WIRED = 48, //Bank 6:48-55 1606383Sgblack@eecs.umich.edu MISCREG_SRS_CONF0, 1616383Sgblack@eecs.umich.edu MISCREG_SRS_CONF1, 1626383Sgblack@eecs.umich.edu MISCREG_SRS_CONF2, 1636383Sgblack@eecs.umich.edu MISCREG_SRS_CONF3, 1646383Sgblack@eecs.umich.edu MISCREG_SRS_CONF4, 1656329Sgblack@eecs.umich.edu 1666383Sgblack@eecs.umich.edu MISCREG_HWRENA = 56, //Bank 7: 56-63 1676329Sgblack@eecs.umich.edu 1686383Sgblack@eecs.umich.edu MISCREG_BADVADDR = 64, //Bank 8: 64-71 1696329Sgblack@eecs.umich.edu 1706383Sgblack@eecs.umich.edu MISCREG_COUNT = 72, //Bank 9: 72-79 1716329Sgblack@eecs.umich.edu 1726383Sgblack@eecs.umich.edu MISCREG_ENTRYHI = 80, //Bank 10: 80-87 1736329Sgblack@eecs.umich.edu 1746383Sgblack@eecs.umich.edu MISCREG_COMPARE = 88, //Bank 11: 88-95 1756329Sgblack@eecs.umich.edu 1766383Sgblack@eecs.umich.edu MISCREG_STATUS = 96, //Bank 12: 96-103 1776383Sgblack@eecs.umich.edu MISCREG_INTCTL, 1786383Sgblack@eecs.umich.edu MISCREG_SRSCTL, 1796383Sgblack@eecs.umich.edu MISCREG_SRSMAP, 1806329Sgblack@eecs.umich.edu 1816383Sgblack@eecs.umich.edu MISCREG_CAUSE = 104, //Bank 13: 104-111 1826329Sgblack@eecs.umich.edu 1836383Sgblack@eecs.umich.edu MISCREG_EPC = 112, //Bank 14: 112-119 1846329Sgblack@eecs.umich.edu 1856383Sgblack@eecs.umich.edu MISCREG_PRID = 120, //Bank 15: 120-127, 1866383Sgblack@eecs.umich.edu MISCREG_EBASE, 1876329Sgblack@eecs.umich.edu 1886383Sgblack@eecs.umich.edu MISCREG_CONFIG = 128, //Bank 16: 128-135 1896383Sgblack@eecs.umich.edu MISCREG_CONFIG1, 1906383Sgblack@eecs.umich.edu MISCREG_CONFIG2, 1916383Sgblack@eecs.umich.edu MISCREG_CONFIG3, 1926383Sgblack@eecs.umich.edu MISCREG_CONFIG4, 1936383Sgblack@eecs.umich.edu MISCREG_CONFIG5, 1946383Sgblack@eecs.umich.edu MISCREG_CONFIG6, 1956383Sgblack@eecs.umich.edu MISCREG_CONFIG7, 1966329Sgblack@eecs.umich.edu 1976329Sgblack@eecs.umich.edu 1986383Sgblack@eecs.umich.edu MISCREG_LLADDR = 136, //Bank 17: 136-143 1996329Sgblack@eecs.umich.edu 2006383Sgblack@eecs.umich.edu MISCREG_WATCHLO0 = 144, //Bank 18: 144-151 2016383Sgblack@eecs.umich.edu MISCREG_WATCHLO1, 2026383Sgblack@eecs.umich.edu MISCREG_WATCHLO2, 2036383Sgblack@eecs.umich.edu MISCREG_WATCHLO3, 2046383Sgblack@eecs.umich.edu MISCREG_WATCHLO4, 2056383Sgblack@eecs.umich.edu MISCREG_WATCHLO5, 2066383Sgblack@eecs.umich.edu MISCREG_WATCHLO6, 2076383Sgblack@eecs.umich.edu MISCREG_WATCHLO7, 2086329Sgblack@eecs.umich.edu 2096383Sgblack@eecs.umich.edu MISCREG_WATCHHI0 = 152, //Bank 19: 152-159 2106383Sgblack@eecs.umich.edu MISCREG_WATCHHI1, 2116383Sgblack@eecs.umich.edu MISCREG_WATCHHI2, 2126383Sgblack@eecs.umich.edu MISCREG_WATCHHI3, 2136383Sgblack@eecs.umich.edu MISCREG_WATCHHI4, 2146383Sgblack@eecs.umich.edu MISCREG_WATCHHI5, 2156383Sgblack@eecs.umich.edu MISCREG_WATCHHI6, 2166383Sgblack@eecs.umich.edu MISCREG_WATCHHI7, 2176329Sgblack@eecs.umich.edu 2186383Sgblack@eecs.umich.edu MISCREG_XCCONTEXT64 = 160, //Bank 20: 160-167 2196329Sgblack@eecs.umich.edu 2206329Sgblack@eecs.umich.edu //Bank 21: 168-175 2216329Sgblack@eecs.umich.edu 2226329Sgblack@eecs.umich.edu //Bank 22: 176-183 2236329Sgblack@eecs.umich.edu 2246383Sgblack@eecs.umich.edu MISCREG_DEBUG = 184, //Bank 23: 184-191 2256383Sgblack@eecs.umich.edu MISCREG_TRACE_CONTROL1, 2266383Sgblack@eecs.umich.edu MISCREG_TRACE_CONTROL2, 2276383Sgblack@eecs.umich.edu MISCREG_USER_TRACE_DATA, 2286383Sgblack@eecs.umich.edu MISCREG_TRACE_BPC, 2296329Sgblack@eecs.umich.edu 2306383Sgblack@eecs.umich.edu MISCREG_DEPC = 192, //Bank 24: 192-199 2316329Sgblack@eecs.umich.edu 2326383Sgblack@eecs.umich.edu MISCREG_PERFCNT0 = 200, //Bank 25: 200-207 2336383Sgblack@eecs.umich.edu MISCREG_PERFCNT1, 2346383Sgblack@eecs.umich.edu MISCREG_PERFCNT2, 2356383Sgblack@eecs.umich.edu MISCREG_PERFCNT3, 2366383Sgblack@eecs.umich.edu MISCREG_PERFCNT4, 2376383Sgblack@eecs.umich.edu MISCREG_PERFCNT5, 2386383Sgblack@eecs.umich.edu MISCREG_PERFCNT6, 2396383Sgblack@eecs.umich.edu MISCREG_PERFCNT7, 2406329Sgblack@eecs.umich.edu 2416383Sgblack@eecs.umich.edu MISCREG_ERRCTL = 208, //Bank 26: 208-215 2426329Sgblack@eecs.umich.edu 2436383Sgblack@eecs.umich.edu MISCREG_CACHEERR0 = 216, //Bank 27: 216-223 2446383Sgblack@eecs.umich.edu MISCREG_CACHEERR1, 2456383Sgblack@eecs.umich.edu MISCREG_CACHEERR2, 2466383Sgblack@eecs.umich.edu MISCREG_CACHEERR3, 2476329Sgblack@eecs.umich.edu 2486383Sgblack@eecs.umich.edu MISCREG_TAGLO0 = 224, //Bank 28: 224-231 2496383Sgblack@eecs.umich.edu MISCREG_DATALO1, 2506383Sgblack@eecs.umich.edu MISCREG_TAGLO2, 2516383Sgblack@eecs.umich.edu MISCREG_DATALO3, 2526383Sgblack@eecs.umich.edu MISCREG_TAGLO4, 2536383Sgblack@eecs.umich.edu MISCREG_DATALO5, 2546383Sgblack@eecs.umich.edu MISCREG_TAGLO6, 2556383Sgblack@eecs.umich.edu MISCREG_DATALO7, 2566329Sgblack@eecs.umich.edu 2576383Sgblack@eecs.umich.edu MISCREG_TAGHI0 = 232, //Bank 29: 232-239 2586383Sgblack@eecs.umich.edu MISCREG_DATAHI1, 2596383Sgblack@eecs.umich.edu MISCREG_TAGHI2, 2606383Sgblack@eecs.umich.edu MISCREG_DATAHI3, 2616383Sgblack@eecs.umich.edu MISCREG_TAGHI4, 2626383Sgblack@eecs.umich.edu MISCREG_DATAHI5, 2636383Sgblack@eecs.umich.edu MISCREG_TAGHI6, 2646383Sgblack@eecs.umich.edu MISCREG_DATAHI7, 2656329Sgblack@eecs.umich.edu 2666329Sgblack@eecs.umich.edu 2676383Sgblack@eecs.umich.edu MISCREG_ERROR_EPC = 240, //Bank 30: 240-247 2686329Sgblack@eecs.umich.edu 2696383Sgblack@eecs.umich.edu MISCREG_DESAVE = 248, //Bank 31: 248-256 2706329Sgblack@eecs.umich.edu 2716383Sgblack@eecs.umich.edu MISCREG_LLFLAG = 257, 2726807Sgblack@eecs.umich.edu MISCREG_TP_VALUE, 2736329Sgblack@eecs.umich.edu 2746383Sgblack@eecs.umich.edu MISCREG_NUMREGS 2756329Sgblack@eecs.umich.edu}; 2766329Sgblack@eecs.umich.edu 2779917Ssteve.reinhardt@amd.comconst int NumMiscRegs = MISCREG_NUMREGS; 2786329Sgblack@eecs.umich.edu 2796329Sgblack@eecs.umich.educonst int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; 2806329Sgblack@eecs.umich.edu 28113556Sgabeblack@google.comtypedef RegVal IntReg; 2826329Sgblack@eecs.umich.edu 2836329Sgblack@eecs.umich.edu// floating point register file entry type 28413556Sgabeblack@google.comtypedef RegVal FloatRegBits; 28513556Sgabeblack@google.comtypedef FloatRegVal FloatReg; 2866329Sgblack@eecs.umich.edu 2876329Sgblack@eecs.umich.edu// cop-0/cop-1 system control register 28813556Sgabeblack@google.comtypedef RegVal MiscReg; 2896329Sgblack@eecs.umich.edu 2909920Syasuko.eckert@amd.com// dummy typedef since we don't have CC regs 2919920Syasuko.eckert@amd.comtypedef uint8_t CCReg; 2929920Syasuko.eckert@amd.com 29312109SRekai.GonzalezAlberquilla@arm.com// dummy typedefs since we don't have vector regs 29412109SRekai.GonzalezAlberquilla@arm.comconstexpr unsigned NumVecElemPerVecReg = 2; 29512109SRekai.GonzalezAlberquilla@arm.comusing VecElem = uint32_t; 29612109SRekai.GonzalezAlberquilla@arm.comusing VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; 29712109SRekai.GonzalezAlberquilla@arm.comusing ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; 29812109SRekai.GonzalezAlberquilla@arm.comusing VecRegContainer = VecReg::Container; 29912109SRekai.GonzalezAlberquilla@arm.com// This has to be one to prevent warnings that are treated as errors 30012109SRekai.GonzalezAlberquilla@arm.comconstexpr unsigned NumVecRegs = 1; 30112109SRekai.GonzalezAlberquilla@arm.com 3026328SN/A} // namespace MipsISA 3032972SN/A 3042972SN/A#endif 305