process.cc revision 11905 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 *          Ali Saidi
30 *          Korey Sewell
31 */
32
33#include "arch/mips/process.hh"
34
35#include "arch/mips/isa_traits.hh"
36#include "base/loader/elf_object.hh"
37#include "base/loader/object_file.hh"
38#include "base/misc.hh"
39#include "cpu/thread_context.hh"
40#include "debug/Loader.hh"
41#include "mem/page_table.hh"
42#include "sim/aux_vector.hh"
43#include "sim/process.hh"
44#include "sim/process_impl.hh"
45#include "sim/syscall_return.hh"
46#include "sim/system.hh"
47
48using namespace std;
49using namespace MipsISA;
50
51MipsProcess::MipsProcess(ProcessParams * params, ObjectFile *objFile)
52    : Process(params, objFile)
53{
54    // Set up stack. On MIPS, stack starts at the top of kuseg
55    // user address space. MIPS stack grows down from here
56    Addr stack_base = 0x7FFFFFFF;
57
58    Addr max_stack_size = 8 * 1024 * 1024;
59
60    // Set pointer for next thread stack.  Reserve 8M for main stack.
61    Addr next_thread_stack_base = stack_base - max_stack_size;
62
63    // Set up break point (Top of Heap)
64    Addr brk_point = objFile->dataBase() + objFile->dataSize() +
65                     objFile->bssSize();
66    brk_point = roundUp(brk_point, PageBytes);
67
68    // Set up region for mmaps.  Start it 1GB above the top of the heap.
69    Addr mmap_end = brk_point + 0x40000000L;
70
71    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
72                                     next_thread_stack_base, mmap_end);
73}
74
75void
76MipsProcess::initState()
77{
78    Process::initState();
79
80    argsInit<uint32_t>(PageBytes);
81}
82
83template<class IntType>
84void
85MipsProcess::argsInit(int pageSize)
86{
87    int intSize = sizeof(IntType);
88
89    // Patch the ld_bias for dynamic executables.
90    updateBias();
91
92    // load object file into target memory
93    objFile->loadSections(initVirtMem);
94
95    typedef AuxVector<IntType> auxv_t;
96    std::vector<auxv_t> auxv;
97
98    ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
99    if (elfObject)
100    {
101        // Set the system page size
102        auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::PageBytes));
103        // Set the frequency at which time() increments
104        auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
105        // For statically linked executables, this is the virtual
106        // address of the program header tables if they appear in the
107        // executable image.
108        auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
109        DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
110        // This is the size of a program header entry from the elf file.
111        auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
112        // This is the number of program headers from the original elf file.
113        auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
114        // This is the base address of the ELF interpreter; it should be
115        // zero for static executables or contain the base address for
116        // dynamic executables.
117        auxv.push_back(auxv_t(M5_AT_BASE, getBias()));
118        //The entry point to the program
119        auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint()));
120        //Different user and group IDs
121        auxv.push_back(auxv_t(M5_AT_UID, uid()));
122        auxv.push_back(auxv_t(M5_AT_EUID, euid()));
123        auxv.push_back(auxv_t(M5_AT_GID, gid()));
124        auxv.push_back(auxv_t(M5_AT_EGID, egid()));
125    }
126
127    // Calculate how much space we need for arg & env & auxv arrays.
128    int argv_array_size = intSize * (argv.size() + 1);
129    int envp_array_size = intSize * (envp.size() + 1);
130    int auxv_array_size = intSize * 2 * (auxv.size() + 1);
131
132    int arg_data_size = 0;
133    for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
134        arg_data_size += argv[i].size() + 1;
135    }
136    int env_data_size = 0;
137    for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
138        env_data_size += envp[i].size() + 1;
139    }
140
141    int space_needed =
142        argv_array_size +
143        envp_array_size +
144        auxv_array_size +
145        arg_data_size +
146        env_data_size;
147
148    // set bottom of stack
149    memState->setStackMin(memState->getStackBase() - space_needed);
150    // align it
151    memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
152    memState->setStackSize(memState->getStackBase() - memState->getStackMin());
153    // map memory
154    allocateMem(memState->getStackMin(), roundUp(memState->getStackSize(),
155                pageSize));
156
157    // map out initial stack contents; leave room for argc
158    IntType argv_array_base = memState->getStackMin() + intSize;
159    IntType envp_array_base = argv_array_base + argv_array_size;
160    IntType auxv_array_base = envp_array_base + envp_array_size;
161    IntType arg_data_base = auxv_array_base + auxv_array_size;
162    IntType env_data_base = arg_data_base + arg_data_size;
163
164    // write contents to stack
165    IntType argc = argv.size();
166
167    argc = htog((IntType)argc);
168
169    initVirtMem.writeBlob(memState->getStackMin(), (uint8_t*)&argc, intSize);
170
171    copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
172
173    copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
174
175    // Copy the aux vector
176    for (typename vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) {
177        initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize,
178                (uint8_t*)&(auxv[x].a_type), intSize);
179        initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
180                (uint8_t*)&(auxv[x].a_val), intSize);
181    }
182
183    // Write out the terminating zeroed auxilliary vector
184    for (unsigned i = 0; i < 2; i++) {
185        const IntType zero = 0;
186        const Addr addr = auxv_array_base + 2 * intSize * (auxv.size() + i);
187        initVirtMem.writeBlob(addr, (uint8_t*)&zero, intSize);
188    }
189
190    ThreadContext *tc = system->getThreadContext(contextIds[0]);
191
192    setSyscallArg(tc, 0, argc);
193    setSyscallArg(tc, 1, argv_array_base);
194    tc->setIntReg(StackPointerReg, memState->getStackMin());
195
196    tc->pcState(getStartPC());
197}
198
199
200MipsISA::IntReg
201MipsProcess::getSyscallArg(ThreadContext *tc, int &i)
202{
203    assert(i < 6);
204    return tc->readIntReg(FirstArgumentReg + i++);
205}
206
207void
208MipsProcess::setSyscallArg(ThreadContext *tc, int i, MipsISA::IntReg val)
209{
210    assert(i < 6);
211    tc->setIntReg(FirstArgumentReg + i, val);
212}
213
214void
215MipsProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
216{
217    if (sysret.successful()) {
218        // no error
219        tc->setIntReg(SyscallSuccessReg, 0);
220        tc->setIntReg(ReturnValueReg, sysret.returnValue());
221    } else {
222        // got an error, return details
223        tc->setIntReg(SyscallSuccessReg, (IntReg) -1);
224        tc->setIntReg(ReturnValueReg, sysret.errnoValue());
225    }
226}
227