process.cc revision 13028
12207SN/A/* 25254Sksewell@umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 35254Sksewell@umich.edu * All rights reserved. 42207SN/A * 55254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 152207SN/A * 165254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 285254Sksewell@umich.edu * Authors: Gabe Black 295254Sksewell@umich.edu * Ali Saidi 305254Sksewell@umich.edu * Korey Sewell 312207SN/A */ 322207SN/A 3311793Sbrandon.potter@amd.com#include "arch/mips/process.hh" 3411793Sbrandon.potter@amd.com 352474SN/A#include "arch/mips/isa_traits.hh" 368229Snate@binkert.org#include "base/loader/elf_object.hh" 372454SN/A#include "base/loader/object_file.hh" 3812334Sgabeblack@google.com#include "base/logging.hh" 392680Sktlim@umich.edu#include "cpu/thread_context.hh" 408232Snate@binkert.org#include "debug/Loader.hh" 416650Sksewell@umich.edu#include "mem/page_table.hh" 4212431Sgabeblack@google.com#include "params/Process.hh" 4311854Sbrandon.potter@amd.com#include "sim/aux_vector.hh" 446650Sksewell@umich.edu#include "sim/process.hh" 456650Sksewell@umich.edu#include "sim/process_impl.hh" 4611800Sbrandon.potter@amd.com#include "sim/syscall_return.hh" 472474SN/A#include "sim/system.hh" 482207SN/A 492447SN/Ausing namespace std; 502474SN/Ausing namespace MipsISA; 512447SN/A 5212431Sgabeblack@google.comMipsProcess::MipsProcess(ProcessParams *params, ObjectFile *objFile) 5312448Sgabeblack@google.com : Process(params, 5412448Sgabeblack@google.com new EmulationPageTable(params->name, params->pid, PageBytes), 5512432Sgabeblack@google.com objFile) 562474SN/A{ 5712441Sgabeblack@google.com fatal_if(params->useArchPT, "Arch page tables not implemented."); 582686Sksewell@umich.edu // Set up stack. On MIPS, stack starts at the top of kuseg 592686Sksewell@umich.edu // user address space. MIPS stack grows down from here 6011905SBrandon.Potter@amd.com Addr stack_base = 0x7FFFFFFF; 6111905SBrandon.Potter@amd.com 6211905SBrandon.Potter@amd.com Addr max_stack_size = 8 * 1024 * 1024; 632474SN/A 642474SN/A // Set pointer for next thread stack. Reserve 8M for main stack. 6511905SBrandon.Potter@amd.com Addr next_thread_stack_base = stack_base - max_stack_size; 662474SN/A 672686Sksewell@umich.edu // Set up break point (Top of Heap) 6811905SBrandon.Potter@amd.com Addr brk_point = objFile->dataBase() + objFile->dataSize() + 6911905SBrandon.Potter@amd.com objFile->bssSize(); 7011905SBrandon.Potter@amd.com brk_point = roundUp(brk_point, PageBytes); 712686Sksewell@umich.edu 726811SMatt DeVuyst // Set up region for mmaps. Start it 1GB above the top of the heap. 7311905SBrandon.Potter@amd.com Addr mmap_end = brk_point + 0x40000000L; 7411905SBrandon.Potter@amd.com 7511905SBrandon.Potter@amd.com memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 7611905SBrandon.Potter@amd.com next_thread_stack_base, mmap_end); 772474SN/A} 782474SN/A 792474SN/Avoid 8011851Sbrandon.potter@amd.comMipsProcess::initState() 812474SN/A{ 8211851Sbrandon.potter@amd.com Process::initState(); 836650Sksewell@umich.edu 8410318Sandreas.hansson@arm.com argsInit<uint32_t>(PageBytes); 852474SN/A} 865958Sgblack@eecs.umich.edu 876811SMatt DeVuysttemplate<class IntType> 886650Sksewell@umich.eduvoid 8911851Sbrandon.potter@amd.comMipsProcess::argsInit(int pageSize) 906650Sksewell@umich.edu{ 916811SMatt DeVuyst int intSize = sizeof(IntType); 926811SMatt DeVuyst 9311389Sbrandon.potter@amd.com // Patch the ld_bias for dynamic executables. 9411389Sbrandon.potter@amd.com updateBias(); 9511389Sbrandon.potter@amd.com 966650Sksewell@umich.edu // load object file into target memory 976650Sksewell@umich.edu objFile->loadSections(initVirtMem); 986650Sksewell@umich.edu 996811SMatt DeVuyst typedef AuxVector<IntType> auxv_t; 1006811SMatt DeVuyst std::vector<auxv_t> auxv; 1016811SMatt DeVuyst 1026811SMatt DeVuyst ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 1036811SMatt DeVuyst if (elfObject) 1046811SMatt DeVuyst { 1056811SMatt DeVuyst // Set the system page size 10610318Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::PageBytes)); 1076811SMatt DeVuyst // Set the frequency at which time() increments 1086811SMatt DeVuyst auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 1096811SMatt DeVuyst // For statically linked executables, this is the virtual 1106811SMatt DeVuyst // address of the program header tables if they appear in the 1116811SMatt DeVuyst // executable image. 1126811SMatt DeVuyst auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 1136811SMatt DeVuyst DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); 1146811SMatt DeVuyst // This is the size of a program header entry from the elf file. 1156811SMatt DeVuyst auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 1166811SMatt DeVuyst // This is the number of program headers from the original elf file. 1176811SMatt DeVuyst auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 11811389Sbrandon.potter@amd.com // This is the base address of the ELF interpreter; it should be 11911389Sbrandon.potter@amd.com // zero for static executables or contain the base address for 12011389Sbrandon.potter@amd.com // dynamic executables. 12111389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 1226811SMatt DeVuyst //The entry point to the program 1236811SMatt DeVuyst auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 1246811SMatt DeVuyst //Different user and group IDs 1256811SMatt DeVuyst auxv.push_back(auxv_t(M5_AT_UID, uid())); 1266811SMatt DeVuyst auxv.push_back(auxv_t(M5_AT_EUID, euid())); 1276811SMatt DeVuyst auxv.push_back(auxv_t(M5_AT_GID, gid())); 1286811SMatt DeVuyst auxv.push_back(auxv_t(M5_AT_EGID, egid())); 1296811SMatt DeVuyst } 1306811SMatt DeVuyst 1316811SMatt DeVuyst // Calculate how much space we need for arg & env & auxv arrays. 1326650Sksewell@umich.edu int argv_array_size = intSize * (argv.size() + 1); 1336650Sksewell@umich.edu int envp_array_size = intSize * (envp.size() + 1); 1346811SMatt DeVuyst int auxv_array_size = intSize * 2 * (auxv.size() + 1); 1356811SMatt DeVuyst 1366650Sksewell@umich.edu int arg_data_size = 0; 1376650Sksewell@umich.edu for (vector<string>::size_type i = 0; i < argv.size(); ++i) { 1386650Sksewell@umich.edu arg_data_size += argv[i].size() + 1; 1396650Sksewell@umich.edu } 1406650Sksewell@umich.edu int env_data_size = 0; 1416650Sksewell@umich.edu for (vector<string>::size_type i = 0; i < envp.size(); ++i) { 1426650Sksewell@umich.edu env_data_size += envp[i].size() + 1; 1436650Sksewell@umich.edu } 1446650Sksewell@umich.edu 1456650Sksewell@umich.edu int space_needed = 1466811SMatt DeVuyst argv_array_size + 1476811SMatt DeVuyst envp_array_size + 1486811SMatt DeVuyst auxv_array_size + 1496811SMatt DeVuyst arg_data_size + 1506811SMatt DeVuyst env_data_size; 1516650Sksewell@umich.edu 1526650Sksewell@umich.edu // set bottom of stack 15311905SBrandon.Potter@amd.com memState->setStackMin(memState->getStackBase() - space_needed); 1546650Sksewell@umich.edu // align it 15511905SBrandon.Potter@amd.com memState->setStackMin(roundDown(memState->getStackMin(), pageSize)); 15611905SBrandon.Potter@amd.com memState->setStackSize(memState->getStackBase() - memState->getStackMin()); 1576650Sksewell@umich.edu // map memory 15811905SBrandon.Potter@amd.com allocateMem(memState->getStackMin(), roundUp(memState->getStackSize(), 15911905SBrandon.Potter@amd.com pageSize)); 1606650Sksewell@umich.edu 16111905SBrandon.Potter@amd.com // map out initial stack contents; leave room for argc 16211905SBrandon.Potter@amd.com IntType argv_array_base = memState->getStackMin() + intSize; 1636811SMatt DeVuyst IntType envp_array_base = argv_array_base + argv_array_size; 1646811SMatt DeVuyst IntType auxv_array_base = envp_array_base + envp_array_size; 1656811SMatt DeVuyst IntType arg_data_base = auxv_array_base + auxv_array_size; 1666811SMatt DeVuyst IntType env_data_base = arg_data_base + arg_data_size; 1676650Sksewell@umich.edu 1686650Sksewell@umich.edu // write contents to stack 1696811SMatt DeVuyst IntType argc = argv.size(); 1706650Sksewell@umich.edu 1716811SMatt DeVuyst argc = htog((IntType)argc); 1726650Sksewell@umich.edu 17311905SBrandon.Potter@amd.com initVirtMem.writeBlob(memState->getStackMin(), (uint8_t*)&argc, intSize); 1746650Sksewell@umich.edu 1756650Sksewell@umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 1766650Sksewell@umich.edu 1776650Sksewell@umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 1786650Sksewell@umich.edu 1796811SMatt DeVuyst // Copy the aux vector 1806811SMatt DeVuyst for (typename vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) { 1818852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 18213028Sbrandon.potter@amd.com (uint8_t*)&(auxv[x].getAuxType()), intSize); 1838852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 18413028Sbrandon.potter@amd.com (uint8_t*)&(auxv[x].getAuxVal()), intSize); 1856811SMatt DeVuyst } 1866811SMatt DeVuyst 1876811SMatt DeVuyst // Write out the terminating zeroed auxilliary vector 1886811SMatt DeVuyst for (unsigned i = 0; i < 2; i++) { 1896811SMatt DeVuyst const IntType zero = 0; 1906811SMatt DeVuyst const Addr addr = auxv_array_base + 2 * intSize * (auxv.size() + i); 1918852Sandreas.hansson@arm.com initVirtMem.writeBlob(addr, (uint8_t*)&zero, intSize); 1926811SMatt DeVuyst } 1936811SMatt DeVuyst 1946650Sksewell@umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 1956650Sksewell@umich.edu 1966650Sksewell@umich.edu setSyscallArg(tc, 0, argc); 1976650Sksewell@umich.edu setSyscallArg(tc, 1, argv_array_base); 19811905SBrandon.Potter@amd.com tc->setIntReg(StackPointerReg, memState->getStackMin()); 1996650Sksewell@umich.edu 20011389Sbrandon.potter@amd.com tc->pcState(getStartPC()); 2016650Sksewell@umich.edu} 2026650Sksewell@umich.edu 2036650Sksewell@umich.edu 2045958Sgblack@eecs.umich.eduMipsISA::IntReg 20511851Sbrandon.potter@amd.comMipsProcess::getSyscallArg(ThreadContext *tc, int &i) 2065958Sgblack@eecs.umich.edu{ 2075958Sgblack@eecs.umich.edu assert(i < 6); 2086701Sgblack@eecs.umich.edu return tc->readIntReg(FirstArgumentReg + i++); 2095958Sgblack@eecs.umich.edu} 2105958Sgblack@eecs.umich.edu 2115958Sgblack@eecs.umich.eduvoid 21211851Sbrandon.potter@amd.comMipsProcess::setSyscallArg(ThreadContext *tc, int i, MipsISA::IntReg val) 2135958Sgblack@eecs.umich.edu{ 2145958Sgblack@eecs.umich.edu assert(i < 6); 2155958Sgblack@eecs.umich.edu tc->setIntReg(FirstArgumentReg + i, val); 2165958Sgblack@eecs.umich.edu} 2175958Sgblack@eecs.umich.edu 2185958Sgblack@eecs.umich.eduvoid 21911851Sbrandon.potter@amd.comMipsProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) 2205958Sgblack@eecs.umich.edu{ 22110223Ssteve.reinhardt@amd.com if (sysret.successful()) { 2225958Sgblack@eecs.umich.edu // no error 2235958Sgblack@eecs.umich.edu tc->setIntReg(SyscallSuccessReg, 0); 22410223Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, sysret.returnValue()); 2255958Sgblack@eecs.umich.edu } else { 2265958Sgblack@eecs.umich.edu // got an error, return details 2275958Sgblack@eecs.umich.edu tc->setIntReg(SyscallSuccessReg, (IntReg) -1); 22810223Ssteve.reinhardt@amd.com tc->setIntReg(ReturnValueReg, sysret.errnoValue()); 2295958Sgblack@eecs.umich.edu } 2305958Sgblack@eecs.umich.edu} 231