pra_constants.hh revision 5222
19814Sandreas.hansson@arm.com/* 22292SN/A * Copyright (c) 2007 MIPS Technologies, Inc. 310030SAli.Saidi@ARM.com * All rights reserved. 47597Sminkyu.jeong@arm.com * 57597Sminkyu.jeong@arm.com * Redistribution and use in source and binary forms, with or without 67597Sminkyu.jeong@arm.com * modification, are permitted provided that the following conditions are 77597Sminkyu.jeong@arm.com * met: redistributions of source code must retain the above copyright 87597Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer; 97597Sminkyu.jeong@arm.com * redistributions in binary form must reproduce the above copyright 107597Sminkyu.jeong@arm.com * notice, this list of conditions and the following disclaimer in the 117597Sminkyu.jeong@arm.com * documentation and/or other materials provided with the distribution; 127597Sminkyu.jeong@arm.com * neither the name of the copyright holders nor the names of its 137597Sminkyu.jeong@arm.com * contributors may be used to endorse or promote products derived from 147597Sminkyu.jeong@arm.com * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272292SN/A * 282292SN/A * Authors: Jaidev Patwardhan 292292SN/A */ 302292SN/A 312292SN/A#ifndef __ARCH_MIPS_PRA_CONSTANTS_HH__ 322292SN/A#define __ARCH_MIPS_PRA_CONSTANTS_HH__ 332292SN/A 342292SN/A#include "arch/mips/types.hh" 352292SN/A//#include "config/full_system.hh" 362292SN/A 372292SN/Anamespace MipsISA 382292SN/A{ 392292SN/A // See MIPS32(R) Architecture Reference Manual Volume - III 402689Sktlim@umich.edu // This header file uses definitions from Revision 2.50 412689Sktlim@umich.edu 422689Sktlim@umich.edu // Index Status Register - CP0 Reg 0, Sel 0 432292SN/A 442292SN/A const unsigned Index_P_HI = 31; 459944Smatt.horsnell@ARM.com const unsigned Index_P_LO = 31; 469944Smatt.horsnell@ARM.com // Need to figure out how to put in the TLB specific bits here 479944Smatt.horsnell@ARM.com // For now, we assume that the entire length is used by the index field 488591Sgblack@eecs.umich.edu // In reality, Index_HI = N-1, where Ceiling(log2(TLB Entries))=N 493326Sktlim@umich.edu const unsigned Index_HI = 30; 508229Snate@binkert.org const unsigned Index_LO = 0; 516658Snate@binkert.org 528887Sgeoffrey.blake@arm.com // CP0 Reg 0, Sel 1-3 are MT registers, see mt_constants.hh 532907Sktlim@umich.edu 542292SN/A // Random Register - CP0 Reg 1, Sel 0 558232Snate@binkert.org // This has a problem similar to the Index_HI fields. We'll keep both consistent at 30 for now 568232Snate@binkert.org const unsigned Random_HI = 30; 578232Snate@binkert.org const unsigned Random_LO = 0; 589527SMatt.Horsnell@arm.com 592722Sktlim@umich.edu // EntryLo0 - CP0 Reg2, Sel 0 - Table 8-6, ARM Vol-3 602669Sktlim@umich.edu const unsigned EntryLo0_Fill_HI = 31; // See Table 8-8, ARM Vol III 612292SN/A const unsigned EntryLo0_Fill_LO = 30; 622669Sktlim@umich.edu const unsigned EntryLo0_PFN_HI = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III) 632678Sktlim@umich.edu const unsigned EntryLo0_PFN_LO = 6; 642678Sktlim@umich.edu const unsigned EntryLo0_C_HI = 5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III) 658581Ssteve.reinhardt@amd.com const unsigned EntryLo0_C_LO = 3; 668581Ssteve.reinhardt@amd.com const unsigned EntryLo0_D_HI = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 672292SN/A const unsigned EntryLo0_D_LO = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 682292SN/A const unsigned EntryLo0_V_HI = 1; // Valid Bit 692292SN/A const unsigned EntryLo0_V_LO = 1; // Valid Bit 702669Sktlim@umich.edu const unsigned EntryLo0_G_HI = 0; // Global Bit. From the ARM Vol-III, Table 8-5: 712292SN/A const unsigned EntryLo0_G_LO = 0; // Global Bit. From the ARM Vol-III, Table 8-5: 722678Sktlim@umich.edu // On a TLB write, the logical AND of the G bits from EntryLo0 and EntryLo1 732292SN/A // becomes the G bit in the TLB entry. If the TLB entry G bit is 1, ASID comparisons are 749444SAndreas.Sandberg@ARM.com // ignored during TLB matches. On a read from a TLB entry, the G bits of both Lo0 and Lo1 759444SAndreas.Sandberg@ARM.com // reflect the state of the TLB G bit. 769444SAndreas.Sandberg@ARM.com 774319Sktlim@umich.edu // EntryLo1 - CP0 Reg3, Sel 0 784319Sktlim@umich.edu const unsigned EntryLo1_G_HI = 0; 794319Sktlim@umich.edu const unsigned EntryLo1_G_LO = 0; 804319Sktlim@umich.edu const unsigned EntryLo1_V_HI = 1; // Valid Bit 814319Sktlim@umich.edu const unsigned EntryLo1_V_LO = 1; // Valid Bit 822678Sktlim@umich.edu const unsigned EntryLo1_D_HI = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 832678Sktlim@umich.edu const unsigned EntryLo1_D_LO = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 842292SN/A const unsigned EntryLo1_C_HI = 5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III) 852678Sktlim@umich.edu const unsigned EntryLo1_C_LO = 3; 862678Sktlim@umich.edu const unsigned EntryLo1_PFN_HI = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III) 875336Shines@cs.fsu.edu const unsigned EntryLo1_PFN_LO = 6; 882678Sktlim@umich.edu const unsigned EntryLo1_Fill_LO = 30; 894873Sstever@eecs.umich.edu const unsigned EntryLo1_Fill_HI = 31; // See Table 8-8, ARM Vol III 902678Sktlim@umich.edu 912292SN/A 922678Sktlim@umich.edu // Context Register - CP0 Reg 4, Sel 0 932678Sktlim@umich.edu const unsigned Context_PTEBase_HI = 31; // Used by the OS to point into current PTE array 942678Sktlim@umich.edu const unsigned Context_PTEBase_LO = 23; 952678Sktlim@umich.edu const unsigned Context_BadVPN2_HI = 22; // This is written by hardware on a TLB exception. Contains bits 31-13 of the 962678Sktlim@umich.edu const unsigned Context_BadVPN2_LO = 4; // virtual address 972678Sktlim@umich.edu // Bits 3-0 are zeros 987852SMatt.Horsnell@arm.com 997852SMatt.Horsnell@arm.com // PageMask Register - CP0 Reg 5, Sel 0 1002344SN/A // Bits 31-29 are 0 1012678Sktlim@umich.edu const unsigned PageMask_Mask_HI = 28; // (Table 8-10, ARM Vol-III) The Mask field is a bit mask in which a "1" indicates that 1022678Sktlim@umich.edu const unsigned PageMask_Mask_LO = 13; // the corresponding bit of the virtual address should not participate in the TLB match 1036974Stjones1@inf.ed.ac.uk const unsigned PageMask_MaskX_HI = 12; // See Table 8-10, ARM Vol-III 1046974Stjones1@inf.ed.ac.uk const unsigned PageMask_MaskX_LO = 11; 1056974Stjones1@inf.ed.ac.uk // Bits 10-0 are zero 1066974Stjones1@inf.ed.ac.uk 1076974Stjones1@inf.ed.ac.uk 1086974Stjones1@inf.ed.ac.uk // PageGrain Register - CP0 Reg 5, Sel 1 1096974Stjones1@inf.ed.ac.uk const unsigned PageGrain_ASE_UP_HI = 31; // ASE specific bits (SmartMIPS) 1109444SAndreas.Sandberg@ARM.com const unsigned PageGrain_ASE_UP_LO = 30; // 1119444SAndreas.Sandberg@ARM.com const unsigned PageGrain_ELPA = 29; // Used to enable support for large physical addresses in MIPS64 processors, unused in MIPS32 1122820Sktlim@umich.edu const unsigned PageGrain_ESP = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12 1132678Sktlim@umich.edu const unsigned PageGrain_ESP_HI = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12 1142678Sktlim@umich.edu const unsigned PageGrain_ESP_LO = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12 1156974Stjones1@inf.ed.ac.uk const unsigned PageGrain_ASE_DN_HI = 12; 1166974Stjones1@inf.ed.ac.uk const unsigned PageGrain_ASE_DN_LO = 8; 1176974Stjones1@inf.ed.ac.uk // Bits 27-13, 7-0 are zeros 1186974Stjones1@inf.ed.ac.uk 1196974Stjones1@inf.ed.ac.uk // Wired Register - CPO Reg 6, Sel 0 1206974Stjones1@inf.ed.ac.uk // See note on Index register (CP0, Sel0) above 1212678Sktlim@umich.edu const unsigned Wired_HI = 30; 1222678Sktlim@umich.edu const unsigned Wired_LO = 0; 1232678Sktlim@umich.edu 1242678Sktlim@umich.edu 1252678Sktlim@umich.edu // HWREna Register - CP0 Reg 7, Sel 0 1262344SN/A const unsigned HWREna_IMPL_HI = 31; // These bits enable access to implementation dependent hardware registers 31 1272307SN/A const unsigned HWREna_IMPL_LO = 30; // and 30 1286974Stjones1@inf.ed.ac.uk const unsigned HWREna_Mask_HI = 3; // Each bit enables access to a particular hardware register. If bit 'n' is 1, HW Reg n is accessible 1296974Stjones1@inf.ed.ac.uk const unsigned HWREna_Mask_LO = 0; // See the RDHWR instruction for more details 1306974Stjones1@inf.ed.ac.uk 1316974Stjones1@inf.ed.ac.uk 13210020Smatt.horsnell@ARM.com // BadVAddr Register - CP0 Reg 8, Sel 0 13310020Smatt.horsnell@ARM.com const unsigned BadVAddr_HI = 31; 13410023Smatt.horsnell@ARM.com const unsigned BadVAddr_LO = 0; 13510023Smatt.horsnell@ARM.com 1362678Sktlim@umich.edu // Count Register - CP0 Reg 9, Sel 0 1374032Sktlim@umich.edu const unsigned Count_HI = 31; 1382678Sktlim@umich.edu const unsigned Count_LO = 0; 1392292SN/A 1402292SN/A // EntryHI Register - CP0 Reg 10, Sel 0 1412292SN/A const unsigned EntryHi_VPN2_HI = 31; // This field is written by hardware on a TLB exception or on a TLB read 1422292SN/A const unsigned EntryHi_VPN2_LO = 13; // and is written by software before a TLB write 1438545Ssaidi@eecs.umich.edu const unsigned EntryHi_VPN2X_HI = 12; // Extension to support 1KB pages 1442678Sktlim@umich.edu const unsigned EntryHi_VPN2X_LO = 11; 1458727Snilay@cs.wisc.edu const unsigned EntryHi_ASID_HI = 7; // Address space identifier 1462292SN/A const unsigned EntryHi_ASID_LO = 0; 1472292SN/A 1482292SN/A // Compare Register - CP0 Reg 11, Sel 0 1492292SN/A const unsigned Compare_HI = 31; // Used in conjunction with Count 1502292SN/A const unsigned Compare_LO = 0; 1515529Snate@binkert.org 1525529Snate@binkert.org // Status Register - CP Reg 12, Sel 0 1535529Snate@binkert.org const unsigned Status_IE_HI = 0; 1542292SN/A const unsigned Status_IE_LO = 0; 1554329Sktlim@umich.edu 1564329Sktlim@umich.edu const unsigned Status_EXL = 1; 1574329Sktlim@umich.edu const unsigned Status_EXL_HI = 1; 1582907Sktlim@umich.edu const unsigned Status_EXL_LO = 1; 1592907Sktlim@umich.edu const unsigned Status_ERL_HI = 2; 1602292SN/A const unsigned Status_ERL_LO = 2; 1612292SN/A const unsigned Status_R0 = 3; 16210175SMitch.Hayenga@ARM.com const unsigned Status_UM = 4; 16310175SMitch.Hayenga@ARM.com const unsigned Status_KSU_HI = 4; // R0 and UM are also aliased as KSU 1642329SN/A const unsigned Status_KSU_LO = 3; 1652329SN/A const unsigned Status_UX = 5; 1662329SN/A const unsigned Status_SX = 6; 1672292SN/A const unsigned Status_KX = 7; 1689936SFaissal.Sleiman@arm.com const unsigned Status_IM0 = 8; 1699936SFaissal.Sleiman@arm.com const unsigned Status_IM1 = 9; 1709936SFaissal.Sleiman@arm.com const unsigned Status_IM2 = 10; 1719936SFaissal.Sleiman@arm.com const unsigned Status_IM3 = 11; 1722292SN/A const unsigned Status_IM4 = 12; 1732292SN/A const unsigned Status_IM5 = 13; 1742292SN/A const unsigned Status_IM6 = 14; 1758199SAli.Saidi@ARM.com const unsigned Status_IM7 = 15; 1768199SAli.Saidi@ARM.com const unsigned Status_IPL_HI = 15; // IM7..IM2 are also aliased as IPL 1779444SAndreas.Sandberg@ARM.com const unsigned Status_IPL_LO = 10; 1789444SAndreas.Sandberg@ARM.com const unsigned Status_IMPL_HI = 17; 1799444SAndreas.Sandberg@ARM.com const unsigned Status_IMPL_LO = 16; 1809444SAndreas.Sandberg@ARM.com const unsigned Status_NMI = 19; 1819444SAndreas.Sandberg@ARM.com const unsigned Status_SR = 20; 1829444SAndreas.Sandberg@ARM.com const unsigned Status_TS = 21; 1839444SAndreas.Sandberg@ARM.com const unsigned Status_BEV = 22; 1849444SAndreas.Sandberg@ARM.com const unsigned Status_BEV_HI = 22; 1859444SAndreas.Sandberg@ARM.com const unsigned Status_BEV_LO = 22; 1869444SAndreas.Sandberg@ARM.com const unsigned Status_PX = 23; 1879444SAndreas.Sandberg@ARM.com const unsigned Status_MX = 24; 1889444SAndreas.Sandberg@ARM.com const unsigned Status_RE = 25; 1898199SAli.Saidi@ARM.com const unsigned Status_FR = 26; 1902292SN/A const unsigned Status_RP = 27; 1912292SN/A const unsigned Status_CU3_HI = 31; 1922292SN/A const unsigned Status_CU3_LO = 31; 1932292SN/A const unsigned Status_CU2_HI = 30; 1942292SN/A const unsigned Status_CU2_LO = 30; 1952292SN/A const unsigned Status_CU1_HI = 29; 1963492Sktlim@umich.edu const unsigned Status_CU1_LO = 29; 1972329SN/A const unsigned Status_CU0_HI = 28; 1982292SN/A const unsigned Status_CU0_LO = 28; 1992292SN/A 2009444SAndreas.Sandberg@ARM.com // IntCtl Register - CP0 Reg 12, Sel 1 2019444SAndreas.Sandberg@ARM.com // Interrupt System status and control 2029444SAndreas.Sandberg@ARM.com const unsigned IntCtl_IPTI_HI = 31; 2039444SAndreas.Sandberg@ARM.com const unsigned IntCtl_IPTI_LO = 29; 2049444SAndreas.Sandberg@ARM.com const unsigned IntCtl_IPPCI_HI = 28; 2059814Sandreas.hansson@arm.com const unsigned IntCtl_IPPCI_LO = 26; 2062292SN/A const unsigned IntCtl_VS_HI = 9; 2072292SN/A const unsigned IntCtl_VS_LO = 5; 2082292SN/A // Bits 26-10, 4-0 are zeros 2092292SN/A 2102292SN/A // SRSCtl Register - CP0 Reg 12, Sel 2 2112292SN/A // Shadow Register Set Status and Control 2122292SN/A const unsigned SRSCtl_HSS_HI=29; // Highest Shadow Set 2132292SN/A const unsigned SRSCtl_HSS_LO=26; 2142292SN/A const unsigned SRSCtl_EICSS_HI=21; //EIC interrupt mode shadow set 2158247Snate@binkert.org const unsigned SRSCtl_EICSS_LO=18; 2162292SN/A const unsigned SRSCtl_ESS_HI=15; // Exception Shadow Set 2172292SN/A const unsigned SRSCtl_ESS_LO=12; 2182292SN/A const unsigned SRSCtl_PSS_HI=9; // Previous Shadow Set 2192292SN/A const unsigned SRSCtl_PSS_LO=6; 2202292SN/A const unsigned SRSCtl_CSS_HI=3; // Current Shadow Set 2212727Sktlim@umich.edu const unsigned SRSCtl_CSS_LO=0; 2222727Sktlim@umich.edu 2232727Sktlim@umich.edu // SRSMap Register - CP0 Reg 12, Sel 3 2242727Sktlim@umich.edu // Shadow Set IPL mapping 2252727Sktlim@umich.edu const unsigned SRSMap_SSV7_HI = 31; // Shadow sets for particular vector numbers (7..0) 2262727Sktlim@umich.edu const unsigned SRSMap_SSV7_LO = 28; 2272727Sktlim@umich.edu const unsigned SRSMap_SSV6_HI = 27; 2282727Sktlim@umich.edu const unsigned SRSMap_SSV6_LO = 24; 2292727Sktlim@umich.edu const unsigned SRSMap_SSV5_HI = 23; 2302727Sktlim@umich.edu const unsigned SRSMap_SSV5_LO = 20; 2312727Sktlim@umich.edu const unsigned SRSMap_SSV4_HI = 19; 2322727Sktlim@umich.edu const unsigned SRSMap_SSV4_LO = 16; 2332727Sktlim@umich.edu const unsigned SRSMap_SSV3_HI = 15; 2342727Sktlim@umich.edu const unsigned SRSMap_SSV3_LO = 12; 2352727Sktlim@umich.edu const unsigned SRSMap_SSV2_HI = 11; 2362727Sktlim@umich.edu const unsigned SRSMap_SSV2_LO = 8; 2372727Sktlim@umich.edu const unsigned SRSMap_SSV1_HI = 7; 2382727Sktlim@umich.edu const unsigned SRSMap_SSV1_LO = 4; 2392361SN/A const unsigned SRSMap_SSV0_HI = 3; 2402361SN/A const unsigned SRSMap_SSV0_LO = 20; 2412361SN/A 2422361SN/A // Cause Register - CP0 Reg 13, Sel 0 2432727Sktlim@umich.edu const unsigned Cause_BD_HI = 31; 2442727Sktlim@umich.edu const unsigned Cause_BD_LO = 31; 2452727Sktlim@umich.edu const unsigned Cause_TI_HI = 30; 2462727Sktlim@umich.edu const unsigned Cause_TI_LO = 30; 2472727Sktlim@umich.edu const unsigned Cause_CE_HI = 29; 2482727Sktlim@umich.edu const unsigned Cause_CE_LO = 28; 2492727Sktlim@umich.edu const unsigned Cause_DC = 27; 2502727Sktlim@umich.edu const unsigned Cause_PCI = 26; 2512727Sktlim@umich.edu const unsigned Cause_IV = 24; 2522727Sktlim@umich.edu const unsigned Cause_WP = 23; 2532727Sktlim@umich.edu const unsigned Cause_RIPL_HI = 15; // The individual bits of RIPL are also available as IP7..IP5 2542727Sktlim@umich.edu const unsigned Cause_RIPL_LO = 10; 2552727Sktlim@umich.edu const unsigned Cause_IP7 = 15; 2562727Sktlim@umich.edu const unsigned Cause_IP6 = 14; 2572727Sktlim@umich.edu const unsigned Cause_IP5 = 13; 2582727Sktlim@umich.edu const unsigned Cause_IP4 = 12; 2592727Sktlim@umich.edu const unsigned Cause_IP3 = 11; 2602727Sktlim@umich.edu const unsigned Cause_IP2 = 10; 2612727Sktlim@umich.edu const unsigned Cause_IP1 = 9; 2622727Sktlim@umich.edu const unsigned Cause_IP0 = 8; 2632727Sktlim@umich.edu const unsigned Cause_EXCCODE_HI = 6; 2642727Sktlim@umich.edu const unsigned Cause_EXCCODE_LO = 2; 2652727Sktlim@umich.edu // All intermediate undefined bits must be ZERO 2668922Swilliam.wang@arm.com 2674329Sktlim@umich.edu 2684329Sktlim@umich.edu // EPC Register - CP0 Reg 14, Sel 0 2694329Sktlim@umich.edu // Exception Program Counter 2704329Sktlim@umich.edu const unsigned EPC_HI = 31; 2714329Sktlim@umich.edu const unsigned EPC_LO = 0; 2724329Sktlim@umich.edu 2732292SN/A // PRId Register - CP0 Reg 15, Sel 0 2742292SN/A // Processor Identification register 2752292SN/A const unsigned PRIdCoOp_HI = 31; 2762292SN/A const unsigned PRIdCoOp_LO = 24; 2772292SN/A const unsigned PRIdCoID_HI = 23; 2782292SN/A const unsigned PRIdCoID_LO = 16; 2792292SN/A const unsigned PRIdProc_ID_HI = 15; 2802292SN/A const unsigned PRIdProc_ID_LO = 8; 2812292SN/A const unsigned PRIdRev_HI = 7; 2822292SN/A const unsigned PRIdRev_LO = 0; 2832292SN/A 2842292SN/A 2852292SN/A // EBase Register - CP0 Reg 15, Sel 1 2862292SN/A // Exception Base Register 2879444SAndreas.Sandberg@ARM.com const unsigned EBase_MSB = 31; // MUST BE = 1 2882307SN/A const unsigned EBase_EXCEPTION_Base_HI = 29; 2899444SAndreas.Sandberg@ARM.com const unsigned EBase_EXCEPTION_Base_LO = 12; 2902367SN/A const unsigned EBase_CPUNum_HI = 9; 2912307SN/A const unsigned EBase_CPUNum_LO = 0; 2922329SN/A // Undefined bits must be zero 2939444SAndreas.Sandberg@ARM.com 2942307SN/A // Config Register - CP0 Reg 16, Sel 0 2952307SN/A const unsigned Config_M = 31; 2962307SN/A const unsigned Config_K23_HI = 30; 2972307SN/A const unsigned Config_K23_LO = 28; 2982307SN/A const unsigned Config_KU_HI = 27; 2992307SN/A const unsigned Config_KU_LO = 25; 3009444SAndreas.Sandberg@ARM.com const unsigned Config_IMPL_HI = 24; 3012307SN/A const unsigned Config_IMPL_LO = 16; 3022307SN/A const unsigned Config_BE_HI = 15; 3032307SN/A const unsigned Config_BE_LO = 15; 3042307SN/A const unsigned Config_AT_HI = 14; 3052292SN/A const unsigned Config_AT_LO = 13; 3062292SN/A const unsigned Config_AR_HI = 12; 3072329SN/A const unsigned Config_AR_LO = 10; 3082329SN/A const unsigned Config_MT_HI = 9; 3092292SN/A const unsigned Config_MT_LO = 7; 3102329SN/A const unsigned Config_VI_HI = 3; 3112329SN/A const unsigned Config_VI_LO = 3; 3122292SN/A const unsigned Config_K0_HI = 2; 3132292SN/A const unsigned Config_K0_LO = 0; 3142292SN/A 3152292SN/A // Config1 Register - CP0 Reg 16, Sel 1 3162292SN/A const unsigned Config1_M = 31; 3172329SN/A const unsigned Config1_MMUSize_HI = 30; 3182292SN/A const unsigned Config1_MMUSize_LO = 25; 3192292SN/A const unsigned Config1_IS_HI = 24; 3209936SFaissal.Sleiman@arm.com const unsigned Config1_IS_LO = 22; 3212292SN/A const unsigned Config1_IL_HI = 21; 3222292SN/A const unsigned Config1_IL_LO = 19; 3232292SN/A const unsigned Config1_IA_HI = 18; 3242292SN/A const unsigned Config1_IA_LO = 16; 3252292SN/A const unsigned Config1_DS_HI = 15; 3262292SN/A const unsigned Config1_DS_LO = 13; 3272329SN/A const unsigned Config1_DL_HI = 12; 3282329SN/A const unsigned Config1_DL_LO = 10; 3292329SN/A const unsigned Config1_DA_HI = 9; 3302292SN/A const unsigned Config1_DA_LO = 7; 3312292SN/A const unsigned Config1_C2_HI = 6; 3322292SN/A const unsigned Config1_C2_LO = 6; 3332292SN/A const unsigned Config1_MD_HI = 5; 3342292SN/A const unsigned Config1_MD_LO = 5; 3352329SN/A const unsigned Config1_PC_HI = 4; 3362292SN/A const unsigned Config1_PC_LO = 4; 3379936SFaissal.Sleiman@arm.com const unsigned Config1_WR_HI = 3; 3389936SFaissal.Sleiman@arm.com const unsigned Config1_WR_LO = 3; 3392292SN/A const unsigned Config1_CA_HI = 2; 3402292SN/A const unsigned Config1_CA_LO = 2; 3412292SN/A const unsigned Config1_EP_HI = 1; 3422292SN/A const unsigned Config1_EP_LO = 1; 3432292SN/A const unsigned Config1_FP_HI = 0; 3442292SN/A const unsigned Config1_FP_LO = 0; 3452292SN/A 3462292SN/A 3472292SN/A // Config2 Register - CP0 Reg 16, Sel 2 3482292SN/A const unsigned Config2_M = 31; 3492292SN/A const unsigned Config2_TU_HI = 30; 3502292SN/A const unsigned Config2_TU_LO = 28; 3512292SN/A const unsigned Config2_TS_HI = 27; 3522292SN/A const unsigned Config2_TS_LO = 24; 3532292SN/A const unsigned Config2_TL_HI = 23; 3542292SN/A const unsigned Config2_TL_LO = 20; 3552292SN/A const unsigned Config2_TA_HI = 19; 3562292SN/A const unsigned Config2_TA_LO = 16; 3572292SN/A const unsigned Config2_SU_HI = 15; 3582292SN/A const unsigned Config2_SU_LO = 12; 3592292SN/A const unsigned Config2_SS_HI = 11; 3602292SN/A const unsigned Config2_SS_LO = 8; 3612292SN/A const unsigned Config2_SL_HI = 7; 3622329SN/A const unsigned Config2_SL_LO = 4; 3632329SN/A const unsigned Config2_SA_HI = 3; 3642292SN/A const unsigned Config2_SA_LO = 0; 3657720Sgblack@eecs.umich.edu 3667720Sgblack@eecs.umich.edu // Config3 Register - CP0 Reg 16, Sel 3 3672292SN/A const unsigned Config3_M = 31; 3682292SN/A const unsigned Config3_DSPP_HI = 10; 3692292SN/A const unsigned Config3_DSPP_LO = 10; 3702292SN/A const unsigned Config3_LPA_HI=7; 3712292SN/A const unsigned Config3_LPA_LO=7; 3722292SN/A const unsigned Config3_VEIC_HI=6; 3732292SN/A const unsigned Config3_VEIC_LO=6; 3742292SN/A const unsigned Config3_VINT_HI=5; 3752292SN/A const unsigned Config3_VINT_LO=5; 3762292SN/A const unsigned Config3_SP=4; 3772292SN/A const unsigned Config3_SP_HI=4; 3782292SN/A const unsigned Config3_SP_LO=4; 3792292SN/A const unsigned Config3_MT_HI=2; 3802292SN/A const unsigned Config3_MT_LO=2; 3812292SN/A const unsigned Config3_SM_HI=1; 3822292SN/A const unsigned Config3_SM_LO=1; 3832292SN/A const unsigned Config3_TL_HI=0; 3842292SN/A const unsigned Config3_TL_LO=0; 3852292SN/A 3862292SN/A 3872292SN/A // LLAddr Register - CP0 Reg 17, Sel 0 3882292SN/A // Load Linked Address (Physical) 3892292SN/A const unsigned LLAddr_PAddr_HI = 31; 3902292SN/A const unsigned LLAddr_PAddr_LO = 0; 3917720Sgblack@eecs.umich.edu 3927720Sgblack@eecs.umich.edu 3932292SN/A 3942292SN/A // WatchLo Register - CP0 Reg 18, Sel 0-n 3952292SN/A // See WatchHi to determine how many pairs of these registers are available 3962292SN/A const unsigned WatchLo_VAddr_HI = 31; 3972292SN/A const unsigned WatchLo_VAddr_LO = 3; 3982292SN/A const unsigned WatchLo_I = 2; 3992292SN/A const unsigned WatchLo_R = 1; 4002292SN/A const unsigned WatchLo_W = 0; 4012292SN/A 4022292SN/A 4032292SN/A // WatchHi Register - CP0 Reg 19, Sel 0-n 4042292SN/A const unsigned WatchHi_M = 31; // If M = 1, another pair of WatchHi/Lo registers exist 4052292SN/A const unsigned WatchHi_G = 30; 4062292SN/A const unsigned WatchHi_ASID_HI = 23; 4072292SN/A const unsigned WatchHi_ASID_LO = 16; 4082292SN/A const unsigned WatchHi_Mask_HI = 11; 4092292SN/A const unsigned WatchHi_Mask_LO = 3; 4102292SN/A const unsigned WatchHi_I = 2; 4112292SN/A const unsigned WatchHi_R = 1; 4122292SN/A const unsigned WatchHi_W = 0; 4132292SN/A 4142292SN/A // Debug Register - CP0 Reg 23, Sel 0 4152292SN/A 4162292SN/A // TraceControl Register - CP0 Reg 23, Sel 1 4172292SN/A // TraceControl2 Register - CP0 Reg 23, Sel 2 4182292SN/A // UserTraceData Register - CP0 Reg 23, Sel 3 4192292SN/A // TraceBPC Register - CP0 Reg 23, Sel 4 4202292SN/A // DEPC Register - CP0 Reg 24, Sel 0 4212292SN/A 4222292SN/A 4232292SN/A // PerfCnt Register - CP0 Reg 25, Sel 0-n 4242292SN/A // Each Perf. counter that exists is mapped onto even-odd select pairs of Reg 25 4252292SN/A // Even values are control registers, odd values are the actual counter 4262292SN/A // The format for the control reg is: 4272292SN/A const unsigned PerfCntCtl_M = 31; // Is there another pair of perf counter registers? 4282292SN/A const unsigned PerfCntCtl_W = 30; 4292292SN/A const unsigned PerfCntCtl_Event_HI = 10; 4302292SN/A const unsigned PerfCntCtl_Event_LO = 5; 4312292SN/A const unsigned PerfCntCtl_IE = 4; 4328545Ssaidi@eecs.umich.edu const unsigned PerfCntCtl_U = 3; 4338545Ssaidi@eecs.umich.edu const unsigned PerfCntCtl_S = 2; 4348545Ssaidi@eecs.umich.edu const unsigned PerfCntCtl_K = 1; 4358545Ssaidi@eecs.umich.edu const unsigned PerfCntCtl_EXL = 0; 43610030SAli.Saidi@ARM.com 4378545Ssaidi@eecs.umich.edu // The format for the counter is a 32-bit value (or 64-bit for MIPS64) 4389383SAli.Saidi@ARM.com const unsigned PerfCnt_Count_HI = 31; 4399383SAli.Saidi@ARM.com const unsigned PerfCnt_Count_LO = 0; 4409383SAli.Saidi@ARM.com 4419383SAli.Saidi@ARM.com // ErrCtl Register - CP0 Reg 26, Sel 0 44210030SAli.Saidi@ARM.com // This is implementation dependent, not defined by the ISA 4439383SAli.Saidi@ARM.com 4449383SAli.Saidi@ARM.com // CacheErr Register - CP0 Reg 27, Sel 0 4459383SAli.Saidi@ARM.com // NOTE: Page 65 of the ARM, Volume-III indicates that there are four sel. values (0-3) 4469383SAli.Saidi@ARM.com // used by the CacheErr registers. However, on page 134, only one sel value is shown 4479383SAli.Saidi@ARM.com const unsigned Cache_Err_ER = 31; 4489383SAli.Saidi@ARM.com const unsigned Cache_Err_EC = 30; 4499383SAli.Saidi@ARM.com const unsigned Cache_Err_ED = 29; 45010030SAli.Saidi@ARM.com const unsigned Cache_Err_ET = 28; 45110030SAli.Saidi@ARM.com const unsigned Cache_Err_ES = 27; 45210030SAli.Saidi@ARM.com const unsigned Cache_Err_EE = 26; 45310030SAli.Saidi@ARM.com const unsigned Cache_Err_EB = 25; 45410030SAli.Saidi@ARM.com const unsigned Cache_Err_IMPL_HI = 24; 45510030SAli.Saidi@ARM.com const unsigned Cache_Err_IMPL_LO = 22; 45610030SAli.Saidi@ARM.com const unsigned Cache_Err_Index_HI = 21; 45710030SAli.Saidi@ARM.com const unsigned Cache_Err_Index_LO = 0; 45810030SAli.Saidi@ARM.com 45910030SAli.Saidi@ARM.com // TagLo Register - CP0 Reg 28 - Even Selects (0,2) 46010030SAli.Saidi@ARM.com const unsigned TagLo_PTagLo_HI = 31; 4618545Ssaidi@eecs.umich.edu const unsigned TagLo_PTagLo_LO = 8; 4628545Ssaidi@eecs.umich.edu const unsigned TagLo_PState_HI = 7; 4638545Ssaidi@eecs.umich.edu const unsigned TagLo_PState_LO = 6; 46410030SAli.Saidi@ARM.com const unsigned TagLo_L = 5; 4658545Ssaidi@eecs.umich.edu const unsigned TagLo_IMPL_HI = 4; 4668545Ssaidi@eecs.umich.edu const unsigned TagLo_IMPL_LO = 3; 46710149Smarco.elver@ed.ac.uk const unsigned TagLo_P = 0; 46810149Smarco.elver@ed.ac.uk // undefined bits must be written 0 4698545Ssaidi@eecs.umich.edu 4708545Ssaidi@eecs.umich.edu 4718545Ssaidi@eecs.umich.edu // DataLo Register - CP0 Reg 28 - Odd Selects (1,3) 4729046SAli.Saidi@ARM.com const unsigned DataLo_HI = 31; 4738545Ssaidi@eecs.umich.edu const unsigned DataLo_LO = 0; 4748545Ssaidi@eecs.umich.edu 4758545Ssaidi@eecs.umich.edu // TagHi Register - CP0 Reg 29 - Even Selects (0,2) 4768545Ssaidi@eecs.umich.edu // Not defined by the architecture 4778545Ssaidi@eecs.umich.edu 4788545Ssaidi@eecs.umich.edu // DataHi Register - CP0 Reg 29 - Odd Selects (1,3) 4798545Ssaidi@eecs.umich.edu const unsigned DataHi_HI = 31; 4808545Ssaidi@eecs.umich.edu const unsigned DataHi_LO = 0; 48110149Smarco.elver@ed.ac.uk 48210149Smarco.elver@ed.ac.uk 48310149Smarco.elver@ed.ac.uk // ErrorEPC - CP0 Reg 30, Sel 0 48410149Smarco.elver@ed.ac.uk const unsigned ErrorPC_HI = 31; 48510149Smarco.elver@ed.ac.uk const unsigned ErrorPC_LO = 0; 48610149Smarco.elver@ed.ac.uk 48710149Smarco.elver@ed.ac.uk // DESAVE - CP0 Reg 31, Sel 0 48810149Smarco.elver@ed.ac.uk 4898545Ssaidi@eecs.umich.edu 49010030SAli.Saidi@ARM.com 4918545Ssaidi@eecs.umich.edu 4928545Ssaidi@eecs.umich.edu 4938545Ssaidi@eecs.umich.edu} // namespace MipsISA 4948545Ssaidi@eecs.umich.edu 49510030SAli.Saidi@ARM.com#endif 49610030SAli.Saidi@ARM.com