pra_constants.hh revision 4661
16657Snate@binkert.org/* 26657Snate@binkert.org * Copyright (c) 2006 The Regents of The University of Michigan 310972Sdavid.hashe@amd.com * All rights reserved. 46657Snate@binkert.org * 56657Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66657Snate@binkert.org * modification, are permitted provided that the following conditions are 76657Snate@binkert.org * met: redistributions of source code must retain the above copyright 86657Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96657Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106657Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116657Snate@binkert.org * documentation and/or other materials provided with the distribution; 126657Snate@binkert.org * neither the name of the copyright holders nor the names of its 136657Snate@binkert.org * contributors may be used to endorse or promote products derived from 146657Snate@binkert.org * this software without specific prior written permission. 156657Snate@binkert.org * 166657Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176657Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186657Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196657Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206657Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216657Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226657Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236657Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246657Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256657Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266657Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276657Snate@binkert.org * 286657Snate@binkert.org * Authors: Jaidev Patwardhan 296999Snate@binkert.org */ 306657Snate@binkert.org 316657Snate@binkert.org#ifndef __ARCH_MIPS_PRA_CONSTANTS_HH__ 326657Snate@binkert.org#define __ARCH_MIPS_PRA_CONSTANTS_HH__ 336657Snate@binkert.org 348189SLisa.Hsu@amd.com#include "arch/mips/types.hh" 356657Snate@binkert.org//#include "config/full_system.hh" 369499Snilay@cs.wisc.edu 379499Snilay@cs.wisc.edunamespace MipsISA 3811308Santhony.gutierrez@amd.com{ 399364Snilay@cs.wisc.edu // See MIPS32(R) Architecture Reference Manual Volume - III 407055Snate@binkert.org // This header file uses definitions from Revision 2.50 416882SBrad.Beckmann@amd.com 426882SBrad.Beckmann@amd.com // Index Status Register - CP0 Reg 0, Sel 0 438191SLisa.Hsu@amd.com 446882SBrad.Beckmann@amd.com const unsigned Index_P_HI = 31; 4511308Santhony.gutierrez@amd.com const unsigned Index_P_LO = 31; 4611308Santhony.gutierrez@amd.com // Need to figure out how to put in the TLB specific bits here 476882SBrad.Beckmann@amd.com // For now, we assume that the entire length is used by the index field 4811308Santhony.gutierrez@amd.com // In reality, Index_HI = N-1, where Ceiling(log2(TLB Entries))=N 499102SNuwan.Jayasena@amd.com const unsigned Index_HI = 30; 5011084Snilay@cs.wisc.edu const unsigned Index_LO = 0; 519366Snilay@cs.wisc.edu 529499Snilay@cs.wisc.edu // CP0 Reg 0, Sel 1-3 are MT registers, see mt_constants.hh 539499Snilay@cs.wisc.edu 549499Snilay@cs.wisc.edu // Random Register - CP0 Reg 1, Sel 0 556882SBrad.Beckmann@amd.com // This has a problem similar to the Index_HI fields. We'll keep both consistent at 30 for now 566657Snate@binkert.org const unsigned Random_HI = 30; 576657Snate@binkert.org const unsigned Random_LO = 0; 586657Snate@binkert.org 596657Snate@binkert.org // EntryLo0 - CP0 Reg2, Sel 0 - Table 8-6, ARM Vol-3 6010311Snilay@cs.wisc.edu const unsigned EntryLo0_Fill_HI = 31; // See Table 8-8, ARM Vol III 6110311Snilay@cs.wisc.edu const unsigned EntryLo0_Fill_LO = 30; 6210311Snilay@cs.wisc.edu const unsigned EntryLo0_PFN_HI = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III) 6310311Snilay@cs.wisc.edu const unsigned EntryLo0_PFN_LO = 6; 646657Snate@binkert.org const unsigned EntryLo0_C_HI = 5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III) 6510311Snilay@cs.wisc.edu const unsigned EntryLo0_C_LO = 3; 669366Snilay@cs.wisc.edu const unsigned EntryLo0_D = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 677839Snilay@cs.wisc.edu const unsigned EntryLo0_V = 1; // Valid Bit 686657Snate@binkert.org const unsigned EntryLo0_G = 0; // Global Bit. From the ARM Vol-III, Table 8-5: 696882SBrad.Beckmann@amd.com // On a TLB write, the logical AND of the G bits from EntryLo0 and EntryLo1 7010308Snilay@cs.wisc.edu // becomes the G bit in the TLB entry. If the TLB entry G bit is 1, ASID comparisons are 7110308Snilay@cs.wisc.edu // ignored during TLB matches. On a read from a TLB entry, the G bits of both Lo0 and Lo1 726882SBrad.Beckmann@amd.com // reflect the state of the TLB G bit. 7310308Snilay@cs.wisc.edu 7410308Snilay@cs.wisc.edu // EntryLo1 - CP0 Reg3, Sel 0 7510308Snilay@cs.wisc.edu const unsigned EntryLo1_G = 0; 7610308Snilay@cs.wisc.edu const unsigned EntryLo1_V = 1; // Valid Bit 7710308Snilay@cs.wisc.edu const unsigned EntryLo1_D = 2; // Dirty Bit, if D=1, page is writable. If D=0, a write causes a TLB Modified Exception 789366Snilay@cs.wisc.edu const unsigned EntryLo1_C_HI = 5; // Coherency attribute of a Page (see Table 8-8, ARM Vol III) 799366Snilay@cs.wisc.edu const unsigned EntryLo1_C_LO = 3; 806657Snate@binkert.org const unsigned EntryLo1_PFN_HI = 29; //PFN defines the Page Frame Number (see Table 8-7, ARM Vol III) 816657Snate@binkert.org const unsigned EntryLo1_PFN_LO = 6; 826657Snate@binkert.org const unsigned EntryLo1_Fill_LO = 30; 836657Snate@binkert.org const unsigned EntryLo1_Fill_HI = 31; // See Table 8-8, ARM Vol III 849104Shestness@cs.utexas.edu 856657Snate@binkert.org 866657Snate@binkert.org // Context Register - CP0 Reg 4, Sel 0 876657Snate@binkert.org const unsigned Context_PTEBase_HI = 31; // Used by the OS to point into current PTE array 8810311Snilay@cs.wisc.edu const unsigned Context_PTEBase_LO = 23; 8910311Snilay@cs.wisc.edu const unsigned Context_BadVPN2_HI = 22; // This is written by hardware on a TLB exception. Contains bits 31-13 of the 9010311Snilay@cs.wisc.edu const unsigned Context_BadVPN2_LO = 4; // virtual address 9110311Snilay@cs.wisc.edu // Bits 3-0 are zeros 926657Snate@binkert.org 937839Snilay@cs.wisc.edu // PageMask Register - CP0 Reg 5, Sel 0 947839Snilay@cs.wisc.edu // Bits 31-29 are 0 9510972Sdavid.hashe@amd.com const unsigned PageMask_Mask_HI = 28; // (Table 8-10, ARM Vol-III) The Mask field is a bit mask in which a "1" indicates that 9610972Sdavid.hashe@amd.com const unsigned PageMask_Mask_LO = 13; // the corresponding bit of the virtual address should not participate in the TLB match 9710972Sdavid.hashe@amd.com const unsigned PageMask_MaskX_HI = 12; // See Table 8-10, ARM Vol-III 986657Snate@binkert.org const unsigned PageMask_MaskX_LO = 11; 996657Snate@binkert.org // Bits 10-0 are zero 1006657Snate@binkert.org 1016657Snate@binkert.org 1026657Snate@binkert.org // PageGrain Register - CP0 Reg 5, Sel 1 1036657Snate@binkert.org const unsigned PageGrain_ASE_UP_HI = 31; // ASE specific bits (SmartMIPS) 1046657Snate@binkert.org const unsigned PageGrain_ASE_UP_LO = 30; // 1056657Snate@binkert.org const unsigned PageGrain_ELPA = 29; // Used to enable support for large physical addresses in MIPS64 processors, unused in MIPS32 1066657Snate@binkert.org const unsigned PageGrain_ESP = 28; // Enables support for 1KB pages (1==enabled,0==disabled), See ARM Vol-III, Table 8-12 1076657Snate@binkert.org const unsigned PageGrain_ASE_DN_HI = 12; 1086657Snate@binkert.org const unsigned PageGrain_ASE_DN_LO = 8; 1096657Snate@binkert.org // Bits 27-13, 7-0 are zeros 1106657Snate@binkert.org 1116657Snate@binkert.org // Wired Register - CPO Reg 6, Sel 0 1126657Snate@binkert.org // See note on Index register (CP0, Sel0) above 1136657Snate@binkert.org const unsigned Wired_HI = 30; 1146657Snate@binkert.org const unsigned Wired_LO = 0; 1156657Snate@binkert.org 1166779SBrad.Beckmann@amd.com 1176657Snate@binkert.org // HWREna Register - CP0 Reg 7, Sel 0 1186657Snate@binkert.org const unsigned HWREna_IMPL_HI = 31; // These bits enable access to implementation dependent hardware registers 31 1196657Snate@binkert.org const unsigned HWREna_IMPL_LO = 30; // and 30 1206657Snate@binkert.org const unsigned HWREna_Mask_HI = 3; // Each bit enables access to a particular hardware register. If bit 'n' is 1, HW Reg n is accessible 1216657Snate@binkert.org const unsigned HWREna_Mask_LO = 0; // See the RDHWR instruction for more details 1226657Snate@binkert.org 1236657Snate@binkert.org 1246657Snate@binkert.org // BadVAddr Register - CP0 Reg 8, Sel 0 1256657Snate@binkert.org const unsigned BadVAddr_HI = 31; 12610972Sdavid.hashe@amd.com const unsigned BadVAddr_LO = 0; 12710972Sdavid.hashe@amd.com 12810972Sdavid.hashe@amd.com // Count Register - CP0 Reg 9, Sel 0 1299104Shestness@cs.utexas.edu const unsigned Count_HI = 31; 1309104Shestness@cs.utexas.edu const unsigned Count_LO = 0; 1319104Shestness@cs.utexas.edu 1329104Shestness@cs.utexas.edu // EntryHI Register - CP0 Reg 10, Sel 0 1336657Snate@binkert.org const unsigned Entry_HI_VPN2_HI = 31; // This field is written by hardware on a TLB exception or on a TLB read 1346657Snate@binkert.org const unsigned Entry_HI_VPN2_LO = 13; // and is written by software before a TLB write 1356657Snate@binkert.org const unsigned Entry_HI_VPN2X_HI = 12; // Extension to support 1KB pages 1366657Snate@binkert.org const unsigned Entry_HI_VPN2X_LO = 11; 1376657Snate@binkert.org const unsigned Entry_HI_ASID_HI = 7; // Address space identifier 1386657Snate@binkert.org const unsigned Entry_HI_ASID_LO = 0; 1396657Snate@binkert.org 1406657Snate@binkert.org // Compare Register - CP0 Reg 11, Sel 0 1416657Snate@binkert.org const unsigned Compare_HI = 31; // Used in conjunction with Count 1426657Snate@binkert.org const unsigned Compare_LO = 0; 1436657Snate@binkert.org 1446657Snate@binkert.org // Status Register - CP Reg 12, Sel 0 1456657Snate@binkert.org const unsigned Status_IE_HI = 0; 14610307Snilay@cs.wisc.edu const unsigned Status_IE_LO = 0; 1476657Snate@binkert.org 1486657Snate@binkert.org const unsigned Status_EXL_HI = 1; 1497839Snilay@cs.wisc.edu const unsigned Status_EXL_LO = 1; 1507839Snilay@cs.wisc.edu const unsigned Status_ERL_HI = 2; 1517839Snilay@cs.wisc.edu const unsigned Status_ERL_LO = 2; 1527839Snilay@cs.wisc.edu const unsigned Status_R0 = 3; 1537839Snilay@cs.wisc.edu const unsigned Status_UM = 4; 1547839Snilay@cs.wisc.edu const unsigned Status_KSU_HI = 4; // R0 and UM are also aliased as KSU 1557839Snilay@cs.wisc.edu const unsigned Status_KSU_LO = 3; 1567839Snilay@cs.wisc.edu const unsigned Status_UX = 5; 1577839Snilay@cs.wisc.edu const unsigned Status_SX = 6; 1587839Snilay@cs.wisc.edu const unsigned Status_KX = 7; 15910968Sdavid.hashe@amd.com const unsigned Status_IM0 = 8; 16010968Sdavid.hashe@amd.com const unsigned Status_IM1 = 9; 16110968Sdavid.hashe@amd.com const unsigned Status_IM2 = 10; 16210968Sdavid.hashe@amd.com const unsigned Status_IM3 = 11; 16310968Sdavid.hashe@amd.com const unsigned Status_IM4 = 12; 16410968Sdavid.hashe@amd.com const unsigned Status_IM5 = 13; 16510968Sdavid.hashe@amd.com const unsigned Status_IM6 = 14; 1667839Snilay@cs.wisc.edu const unsigned Status_IM7 = 15; 1676657Snate@binkert.org const unsigned Status_IPL_HI = 15; // IM7..IM2 are also aliased as IPL 1686657Snate@binkert.org const unsigned Status_IPL_LO = 10; 1696657Snate@binkert.org const unsigned Status_IMPL_HI = 17; 1706657Snate@binkert.org const unsigned Status_IMPL_LO = 16; 1716657Snate@binkert.org const unsigned Status_NMI = 19; 1726657Snate@binkert.org const unsigned Status_SR = 20; 1736657Snate@binkert.org const unsigned Status_TS = 21; 1746657Snate@binkert.org const unsigned Status_BEV = 22; 1756657Snate@binkert.org const unsigned Status_PX = 23; 1766657Snate@binkert.org const unsigned Status_MX = 24; 1776657Snate@binkert.org const unsigned Status_RE = 25; 1786657Snate@binkert.org const unsigned Status_FR = 26; 1796657Snate@binkert.org const unsigned Status_RP = 27; 1806657Snate@binkert.org const unsigned Status_CU3_HI = 31; 1816657Snate@binkert.org const unsigned Status_CU3_LO = 31; 1826657Snate@binkert.org const unsigned Status_CU2_HI = 30; 1836657Snate@binkert.org const unsigned Status_CU2_LO = 30; 1846657Snate@binkert.org const unsigned Status_CU1_HI = 29; 1856657Snate@binkert.org const unsigned Status_CU1_LO = 29; 1866657Snate@binkert.org const unsigned Status_CU0_HI = 28; 1876657Snate@binkert.org const unsigned Status_CU0_LO = 28; 1886657Snate@binkert.org 1896657Snate@binkert.org // IntCtl Register - CP0 Reg 12, Sel 1 1906657Snate@binkert.org // Interrupt System status and control 1916657Snate@binkert.org const unsigned IntCtl_IPTI_HI = 31; 1926657Snate@binkert.org const unsigned IntCtl_IPTI_LO = 29; 1936657Snate@binkert.org const unsigned IntCtl_IPPCI_HI = 28; 1946657Snate@binkert.org const unsigned IntCtl_IPPCI_LO = 26; 1956657Snate@binkert.org const unsigned IntCtl_VS_HI = 9; 1966657Snate@binkert.org const unsigned IntCtl_VS_LO = 5; 19710963Sdavid.hashe@amd.com // Bits 26-10, 4-0 are zeros 19810963Sdavid.hashe@amd.com 19910963Sdavid.hashe@amd.com // SRSCtl Register - CP0 Reg 12, Sel 2 20010963Sdavid.hashe@amd.com // Shadow Register Set Status and Control 20110963Sdavid.hashe@amd.com const unsigned SRSCtl_HSS_HI=29; // Highest Shadow Set 20210963Sdavid.hashe@amd.com const unsigned SRSCtl_HSS_LO=26; 20311095Snilay@cs.wisc.edu const unsigned SRSCtl_EICSS_HI=21; //EIC interrupt mode shadow set 20410963Sdavid.hashe@amd.com const unsigned SRSCtl_EICSS_LO=18; 20510963Sdavid.hashe@amd.com const unsigned SRSCtl_ESS_HI=15; // Exception Shadow Set 20610963Sdavid.hashe@amd.com const unsigned SRSCtl_ESS_LO=12; 20710963Sdavid.hashe@amd.com const unsigned SRSCtl_PSS_HI=9; // Previous Shadow Set 20810963Sdavid.hashe@amd.com const unsigned SRSCtl_PSS_LO=6; 20910963Sdavid.hashe@amd.com const unsigned SRSCtl_CSS_HI=3; // Current Shadow Set 21010963Sdavid.hashe@amd.com const unsigned SRSCtl_CSS_LO=0; 21110963Sdavid.hashe@amd.com 2129219Spower.jg@gmail.com // SRSMap Register - CP0 Reg 12, Sel 3 2136877Ssteve.reinhardt@amd.com // Shadow Set IPL mapping 2146657Snate@binkert.org const unsigned SRSMap_SSV7_HI = 31; // Shadow sets for particular vector numbers (7..0) 2159219Spower.jg@gmail.com const unsigned SRSMap_SSV7_LO = 28; 2166657Snate@binkert.org const unsigned SRSMap_SSV6_HI = 27; 2179219Spower.jg@gmail.com const unsigned SRSMap_SSV6_LO = 24; 2186657Snate@binkert.org const unsigned SRSMap_SSV5_HI = 23; 2196877Ssteve.reinhardt@amd.com const unsigned SRSMap_SSV5_LO = 20; 2206999Snate@binkert.org const unsigned SRSMap_SSV4_HI = 19; 2216877Ssteve.reinhardt@amd.com const unsigned SRSMap_SSV4_LO = 16; 22210308Snilay@cs.wisc.edu const unsigned SRSMap_SSV3_HI = 15; 2236877Ssteve.reinhardt@amd.com const unsigned SRSMap_SSV3_LO = 12; 2246877Ssteve.reinhardt@amd.com const unsigned SRSMap_SSV2_HI = 11; 22510308Snilay@cs.wisc.edu const unsigned SRSMap_SSV2_LO = 8; 2266877Ssteve.reinhardt@amd.com const unsigned SRSMap_SSV1_HI = 7; 2276877Ssteve.reinhardt@amd.com const unsigned SRSMap_SSV1_LO = 4; 2286877Ssteve.reinhardt@amd.com const unsigned SRSMap_SSV0_HI = 3; 2296877Ssteve.reinhardt@amd.com const unsigned SRSMap_SSV0_LO = 20; 2306877Ssteve.reinhardt@amd.com 2316877Ssteve.reinhardt@amd.com // Cause Register - CP0 Reg 13, Sel 0 2326877Ssteve.reinhardt@amd.com const unsigned Cause_BD = 31; 2339338SAndreas.Sandberg@arm.com const unsigned Cause_TI = 30; 2346877Ssteve.reinhardt@amd.com const unsigned Cause_CE_HI = 29; 2356877Ssteve.reinhardt@amd.com const unsigned Cause_CE_LO = 28; 2366877Ssteve.reinhardt@amd.com const unsigned Cause_DC = 27; 2376877Ssteve.reinhardt@amd.com const unsigned Cause_PCI = 26; 23810308Snilay@cs.wisc.edu const unsigned Cause_IV = 24; 23910308Snilay@cs.wisc.edu const unsigned Cause_WP = 23; 24010308Snilay@cs.wisc.edu const unsigned Cause_RIPL_HI = 15; // The individual bits of RIPL are also available as IP7..IP5 24110308Snilay@cs.wisc.edu const unsigned Cause_RIPL_LO = 10; 24211084Snilay@cs.wisc.edu const unsigned Cause_IP7 = 15; 2436882SBrad.Beckmann@amd.com const unsigned Cause_IP6 = 14; 24410308Snilay@cs.wisc.edu const unsigned Cause_IP5 = 13; 24510308Snilay@cs.wisc.edu const unsigned Cause_IP4 = 12; 2466882SBrad.Beckmann@amd.com const unsigned Cause_IP3 = 11; 2476882SBrad.Beckmann@amd.com const unsigned Cause_IP2 = 10; 2486882SBrad.Beckmann@amd.com const unsigned Cause_IP1 = 9; 2496882SBrad.Beckmann@amd.com const unsigned Cause_IP0 = 8; 25011021Sjthestness@gmail.com const unsigned Cause_EXCCODE_HI = 6; 2516877Ssteve.reinhardt@amd.com const unsigned Cause_EXCCODE_LO = 2; 2526877Ssteve.reinhardt@amd.com // All intermediate undefined bits must be ZERO 25310917Sbrandon.potter@amd.com 2546877Ssteve.reinhardt@amd.com 2556657Snate@binkert.org // EPC Register - CP0 Reg 14, Sel 0 2566657Snate@binkert.org // Exception Program Counter 2576999Snate@binkert.org const unsigned EPC_HI = 31; 2586657Snate@binkert.org const unsigned EPC_LO = 0; 2596657Snate@binkert.org 2606657Snate@binkert.org // PRId Register - CP0 Reg 15, Sel 0 2616657Snate@binkert.org // Processor Identification register 2627007Snate@binkert.org const unsigned PRIdCoOp_HI = 31; 2636657Snate@binkert.org const unsigned PRIdCoOp_LO = 24; 2646657Snate@binkert.org const unsigned PRIdCoID_HI = 23; 2656657Snate@binkert.org const unsigned PRIdCoID_LO = 16; 2666657Snate@binkert.org const unsigned PRIdProc_ID_HI = 15; 2676657Snate@binkert.org const unsigned PRIdProc_ID_LO = 8; 2687007Snate@binkert.org const unsigned PRIdRev_HI = 7; 2697007Snate@binkert.org const unsigned PRIdRev_LO = 0; 2706657Snate@binkert.org 2717002Snate@binkert.org 2727002Snate@binkert.org // EBase Register - CP0 Reg 15, Sel 1 2737002Snate@binkert.org // Exception Base Register 2747002Snate@binkert.org const unsigned EBase_MSB = 31; // MUST BE = 1 2756657Snate@binkert.org const unsigned EBase_EXCEPTION_Base_HI = 29; 2766657Snate@binkert.org const unsigned EBase_EXCEPTION_Base_LO = 12; 2778229Snate@binkert.org const unsigned EBase_CPUNum_HI = 9; 2788229Snate@binkert.org const unsigned EBase_CPUNum_LO = 0; 2798229Snate@binkert.org // Undefined bits must be zero 28010972Sdavid.hashe@amd.com 2816657Snate@binkert.org // Config Register - CP0 Reg 16, Sel 0 2826657Snate@binkert.org const unsigned Config_M = 31; 2836657Snate@binkert.org const unsigned Config_K23_HI = 30; 2846657Snate@binkert.org const unsigned Config_K23_LO = 28; 2856793SBrad.Beckmann@amd.com const unsigned Config_KU_HI = 27; 2866657Snate@binkert.org const unsigned Config_KU_LO = 25; 28710311Snilay@cs.wisc.edu const unsigned Config_IMPL_HI = 24; 2886657Snate@binkert.org const unsigned Config_IMPL_LO = 16; 2896657Snate@binkert.org const unsigned Config_BE = 15; 2906657Snate@binkert.org const unsigned Config_AT_HI = 14; 2917002Snate@binkert.org const unsigned Config_AT_LO = 13; 2926657Snate@binkert.org const unsigned Config_AR_HI = 12; 2937007Snate@binkert.org const unsigned Config_AR_LO = 10; 2947007Snate@binkert.org const unsigned Config_MT_HI = 9; 2959271Snilay@cs.wisc.edu const unsigned Config_MT_LO = 7; 2966877Ssteve.reinhardt@amd.com const unsigned Config_VI = 3; 2976877Ssteve.reinhardt@amd.com const unsigned Config_K0_HI = 2; 2986657Snate@binkert.org const unsigned Config_K0_LO = 0; 2996877Ssteve.reinhardt@amd.com 30010311Snilay@cs.wisc.edu // Config1 Register - CP0 Reg 16, Sel 1 30111084Snilay@cs.wisc.edu const unsigned Config1_M = 31; 30211084Snilay@cs.wisc.edu const unsigned Config1_MMUSize_HI = 30; 30311021Sjthestness@gmail.com const unsigned Config1_MMUSize_LO = 25; 3049745Snilay@cs.wisc.edu const unsigned Config1_IS_HI = 24; 3057002Snate@binkert.org const unsigned Config1_IS_LO = 22; 3066657Snate@binkert.org const unsigned Config1_IL_HI = 21; 30710012Snilay@cs.wisc.edu const unsigned Config1_IL_LO = 19; 3089745Snilay@cs.wisc.edu const unsigned Config1_IA_HI = 18; 3099745Snilay@cs.wisc.edu const unsigned Config1_IA_LO = 16; 3109745Snilay@cs.wisc.edu const unsigned Config1_DS_HI = 15; 3118683Snilay@cs.wisc.edu const unsigned Config1_DS_LO = 13; 31211308Santhony.gutierrez@amd.com const unsigned Config1_DL_HI = 12; 31311309Sdavid.hashe@amd.com const unsigned Config1_DL_LO = 10; 3147007Snate@binkert.org const unsigned Config1_DA_HI = 9; 31510524Snilay@cs.wisc.edu const unsigned Config1_DA_LO = 7; 3169302Snilay@cs.wisc.edu const unsigned Config1_C2 = 6; 3179745Snilay@cs.wisc.edu const unsigned Config1_MD = 5; 3189745Snilay@cs.wisc.edu const unsigned Config1_PC = 4; 31911061Snilay@cs.wisc.edu const unsigned Config1_WR = 3; 3209745Snilay@cs.wisc.edu const unsigned Config1_CA = 2; 32111061Snilay@cs.wisc.edu const unsigned Config1_EP = 1; 3229745Snilay@cs.wisc.edu const unsigned Config1_FP = 0; 3236657Snate@binkert.org 3246657Snate@binkert.org 3256657Snate@binkert.org // Config2 Register - CP0 Reg 16, Sel 2 3266657Snate@binkert.org const unsigned Config2_M = 31; 3276657Snate@binkert.org const unsigned Config2_TU_HI = 30; 3286657Snate@binkert.org const unsigned Config2_TU_LO = 28; 3296882SBrad.Beckmann@amd.com const unsigned Config2_TS_HI = 27; 3306882SBrad.Beckmann@amd.com const unsigned Config2_TS_LO = 24; 3316882SBrad.Beckmann@amd.com const unsigned Config2_TL_HI = 23; 3326882SBrad.Beckmann@amd.com const unsigned Config2_TL_LO = 20; 3336657Snate@binkert.org const unsigned Config2_TA_HI = 19; 3346657Snate@binkert.org const unsigned Config2_TA_LO = 16; 3357007Snate@binkert.org const unsigned Config2_SU_HI = 15; 3367839Snilay@cs.wisc.edu const unsigned Config2_SU_LO = 12; 3377839Snilay@cs.wisc.edu const unsigned Config2_SS_HI = 11; 3387839Snilay@cs.wisc.edu const unsigned Config2_SS_LO = 8; 3397839Snilay@cs.wisc.edu const unsigned Config2_SL_HI = 7; 3407839Snilay@cs.wisc.edu const unsigned Config2_SL_LO = 4; 3417839Snilay@cs.wisc.edu const unsigned Config2_SA_HI = 3; 3427839Snilay@cs.wisc.edu const unsigned Config2_SA_LO = 0; 3437839Snilay@cs.wisc.edu 3447839Snilay@cs.wisc.edu // Config3 Register - CP0 Reg 16, Sel 3 3457839Snilay@cs.wisc.edu const unsigned Config3_M = 31; 3467839Snilay@cs.wisc.edu const unsigned Config3_DSPP = 10; 3477839Snilay@cs.wisc.edu const unsigned Config3_LPA=7; 34811025Snilay@cs.wisc.edu const unsigned Config3_VEIC=6; 3497007Snate@binkert.org const unsigned Config3_VINT=5; 3507007Snate@binkert.org const unsigned Config3_SP=4; 3517007Snate@binkert.org const unsigned Config3_MT=2; 3527007Snate@binkert.org const unsigned Config3_SM=1; 3537839Snilay@cs.wisc.edu const unsigned Config3_TL=0; 3547839Snilay@cs.wisc.edu 3557839Snilay@cs.wisc.edu 3567839Snilay@cs.wisc.edu // LLAddr Register - CP0 Reg 17, Sel 0 3577839Snilay@cs.wisc.edu // Load Linked Address (Physical) 3587839Snilay@cs.wisc.edu const unsigned LLAddr_PAddr_HI = 31; 3597839Snilay@cs.wisc.edu const unsigned LLAddr_PAddr_LO = 0; 3607839Snilay@cs.wisc.edu 3617839Snilay@cs.wisc.edu 3627839Snilay@cs.wisc.edu 3637839Snilay@cs.wisc.edu // WatchLo Register - CP0 Reg 18, Sel 0-n 3647839Snilay@cs.wisc.edu // See WatchHi to determine how many pairs of these registers are available 36511025Snilay@cs.wisc.edu const unsigned WatchLo_VAddr_HI = 31; 3667007Snate@binkert.org const unsigned WatchLo_VAddr_LO = 3; 3679745Snilay@cs.wisc.edu const unsigned WatchLo_I = 2; 3689745Snilay@cs.wisc.edu const unsigned WatchLo_R = 1; 3699745Snilay@cs.wisc.edu const unsigned WatchLo_W = 0; 3709745Snilay@cs.wisc.edu 3719745Snilay@cs.wisc.edu 3729745Snilay@cs.wisc.edu // WatchHi Register - CP0 Reg 19, Sel 0-n 3736657Snate@binkert.org const unsigned WatchHi_M = 31; // If M = 1, another pair of WatchHi/Lo registers exist 3747007Snate@binkert.org const unsigned WatchHi_G = 30; 3756657Snate@binkert.org const unsigned WatchHi_ASID_HI = 23; 3766657Snate@binkert.org const unsigned WatchHi_ASID_LO = 16; 3776657Snate@binkert.org const unsigned WatchHi_Mask_HI = 11; 3786657Snate@binkert.org const unsigned WatchHi_Mask_LO = 3; 3796657Snate@binkert.org const unsigned WatchHi_I = 2; 3806657Snate@binkert.org const unsigned WatchHi_R = 1; 3816657Snate@binkert.org const unsigned WatchHi_W = 0; 3826657Snate@binkert.org 3837839Snilay@cs.wisc.edu // Debug Register - CP0 Reg 23, Sel 0 3847839Snilay@cs.wisc.edu 3857839Snilay@cs.wisc.edu // TraceControl Register - CP0 Reg 23, Sel 1 3867839Snilay@cs.wisc.edu // TraceControl2 Register - CP0 Reg 23, Sel 2 3877839Snilay@cs.wisc.edu // UserTraceData Register - CP0 Reg 23, Sel 3 3887839Snilay@cs.wisc.edu // TraceBPC Register - CP0 Reg 23, Sel 4 3897839Snilay@cs.wisc.edu // DEPC Register - CP0 Reg 24, Sel 0 3907839Snilay@cs.wisc.edu 3917839Snilay@cs.wisc.edu 3927839Snilay@cs.wisc.edu // PerfCnt Register - CP0 Reg 25, Sel 0-n 3937839Snilay@cs.wisc.edu // Each Perf. counter that exists is mapped onto even-odd select pairs of Reg 25 3947839Snilay@cs.wisc.edu // Even values are control registers, odd values are the actual counter 3957839Snilay@cs.wisc.edu // The format for the control reg is: 3967839Snilay@cs.wisc.edu const unsigned PerfCntCtl_M = 31; // Is there another pair of perf counter registers? 3977839Snilay@cs.wisc.edu const unsigned PerfCntCtl_W = 30; 3987839Snilay@cs.wisc.edu const unsigned PerfCntCtl_Event_HI = 10; 39910121Snilay@cs.wisc.edu const unsigned PerfCntCtl_Event_LO = 5; 4006657Snate@binkert.org const unsigned PerfCntCtl_IE = 4; 4016657Snate@binkert.org const unsigned PerfCntCtl_U = 3; 4026657Snate@binkert.org const unsigned PerfCntCtl_S = 2; 4036657Snate@binkert.org const unsigned PerfCntCtl_K = 1; 4047839Snilay@cs.wisc.edu const unsigned PerfCntCtl_EXL = 0; 4057839Snilay@cs.wisc.edu 4067839Snilay@cs.wisc.edu // The format for the counter is a 32-bit value (or 64-bit for MIPS64) 40710121Snilay@cs.wisc.edu const unsigned PerfCnt_Count_HI = 31; 40810121Snilay@cs.wisc.edu const unsigned PerfCnt_Count_LO = 0; 40911025Snilay@cs.wisc.edu 4107839Snilay@cs.wisc.edu // ErrCtl Register - CP0 Reg 26, Sel 0 4117839Snilay@cs.wisc.edu // This is implementation dependent, not defined by the ISA 4127839Snilay@cs.wisc.edu 41310121Snilay@cs.wisc.edu // CacheErr Register - CP0 Reg 27, Sel 0 41411025Snilay@cs.wisc.edu // NOTE: Page 65 of the ARM, Volume-III indicates that there are four sel. values (0-3) 4157839Snilay@cs.wisc.edu // used by the CacheErr registers. However, on page 134, only one sel value is shown 4167839Snilay@cs.wisc.edu const unsigned Cache_Err_ER = 31; 4177839Snilay@cs.wisc.edu const unsigned Cache_Err_EC = 30; 41810121Snilay@cs.wisc.edu const unsigned Cache_Err_ED = 29; 41911025Snilay@cs.wisc.edu const unsigned Cache_Err_ET = 28; 4207839Snilay@cs.wisc.edu const unsigned Cache_Err_ES = 27; 4217839Snilay@cs.wisc.edu const unsigned Cache_Err_EE = 26; 4227839Snilay@cs.wisc.edu const unsigned Cache_Err_EB = 25; 42311025Snilay@cs.wisc.edu const unsigned Cache_Err_IMPL_HI = 24; 4246657Snate@binkert.org const unsigned Cache_Err_IMPL_LO = 22; 4256657Snate@binkert.org const unsigned Cache_Err_Index_HI = 21; 4266657Snate@binkert.org const unsigned Cache_Err_Index_LO = 0; 4276657Snate@binkert.org 4287007Snate@binkert.org // TagLo Register - CP0 Reg 28 - Even Selects (0,2) 4296657Snate@binkert.org const unsigned TagLo_PTagLo_HI = 31; 4306657Snate@binkert.org const unsigned TagLo_PTagLo_LO = 8; 4319273Snilay@cs.wisc.edu const unsigned TagLo_PState_HI = 7; 43210305Snilay@cs.wisc.edu const unsigned TagLo_PState_LO = 6; 4336657Snate@binkert.org const unsigned TagLo_L = 5; 4346657Snate@binkert.org const unsigned TagLo_IMPL_HI = 4; 4356657Snate@binkert.org const unsigned TagLo_IMPL_LO = 3; 4367007Snate@binkert.org const unsigned TagLo_P = 0; 4376657Snate@binkert.org // undefined bits must be written 0 4386657Snate@binkert.org 4399219Spower.jg@gmail.com 4406657Snate@binkert.org // DataLo Register - CP0 Reg 28 - Odd Selects (1,3) 4416657Snate@binkert.org const unsigned DataLo_HI = 31; 4426999Snate@binkert.org const unsigned DataLo_LO = 0; 4436657Snate@binkert.org 4446657Snate@binkert.org // TagHi Register - CP0 Reg 29 - Even Selects (0,2) 4456657Snate@binkert.org // Not defined by the architecture 4466657Snate@binkert.org 4477007Snate@binkert.org // DataHi Register - CP0 Reg 29 - Odd Selects (1,3) 4486657Snate@binkert.org const unsigned DataHi_HI = 31; 4496657Snate@binkert.org const unsigned DataHi_LO = 0; 4506657Snate@binkert.org 4516657Snate@binkert.org 4526657Snate@binkert.org // ErrorEPC - CP0 Reg 30, Sel 0 4538946Sandreas.hansson@arm.com const unsigned ErrorPC_HI = 31; 4548946Sandreas.hansson@arm.com const unsigned ErrorPC_LO = 0; 4558946Sandreas.hansson@arm.com 4567832Snate@binkert.org // DESAVE - CP0 Reg 31, Sel 0 4577002Snate@binkert.org 4587002Snate@binkert.org 45910972Sdavid.hashe@amd.com 4607002Snate@binkert.org 4618641Snate@binkert.org 4627056Snate@binkert.org} // namespace MipsISA 46310972Sdavid.hashe@amd.com 46410972Sdavid.hashe@amd.com#endif 46510972Sdavid.hashe@amd.com