pagetable.hh revision 5268
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * Copyright (c) 2007 MIPS Technologies, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * Authors: Nathan Binkert 30 * Steve Reinhardt 31 * Jaidev Patwardhan 32 */ 33 34#ifndef __ARCH_MIPS_PAGETABLE_H__ 35#define __ARCH_MIPS_PAGETABLE_H__ 36 37#include "arch/mips/isa_traits.hh" 38#include "arch/mips/utility.hh" 39#include "arch/mips/vtophys.hh" 40#include "config/full_system.hh" 41 42namespace MipsISA { 43 44 struct VAddr 45 { 46 static const int ImplBits = 43; 47 static const Addr ImplMask = (ULL(1) << ImplBits) - 1; 48 static const Addr UnImplMask = ~ImplMask; 49 50 VAddr(Addr a) : addr(a) {} 51 Addr addr; 52 operator Addr() const { return addr; } 53 const VAddr &operator=(Addr a) { addr = a; return *this; } 54 55 Addr vpn() const { return (addr & ImplMask) >> PageShift; } 56 Addr page() const { return addr & Page_Mask; } 57 Addr offset() const { return addr & PageOffset; } 58 59 Addr level3() const 60 { return MipsISA::PteAddr(addr >> PageShift); } 61 Addr level2() const 62 { return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); } 63 Addr level1() const 64 { return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); } 65 }; 66 67 // ITB/DTB page table entry 68 struct PTE 69 { 70 Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask) 71 Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi) 72 uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi 73 74 bool G; // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit 75 76 /* Contents of Entry Lo0 */ 77 Addr PFN0; // Physical Frame Number - Even 78 bool D0; // Even entry Dirty Bit 79 bool V0; // Even entry Valid Bit 80 uint8_t C0; // Cache Coherency Bits - Even 81 82 /* Contents of Entry Lo1 */ 83 Addr PFN1; // Physical Frame Number - Odd 84 bool D1; // Odd entry Dirty Bit 85 bool V1; // Odd entry Valid Bit 86 uint8_t C1; // Cache Coherency Bits (3 bits) 87 88 /* The next few variables are put in as optimizations to reduce TLB lookup overheads */ 89 /* For a given Mask, what is the address shift amount, and what is the OffsetMask */ 90 int AddrShiftAmount; 91 int OffsetMask; 92 93 bool Valid() { return (V0 | V1);}; 94 void serialize(std::ostream &os); 95 void unserialize(Checkpoint *cp, const std::string §ion); 96 }; 97 98}; 99#endif // __ARCH_MIPS_PAGETABLE_H__ 100 101