pagetable.hh revision 5254
15222Sksewell@umich.edu/* 25254Sksewell@umich.edu * Copyright (c) 2007 MIPS Technologies, Inc. 35254Sksewell@umich.edu * All rights reserved. 45222Sksewell@umich.edu * 55254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 155222Sksewell@umich.edu * 165254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275222Sksewell@umich.edu * 285222Sksewell@umich.edu * Authors: Jaidev Patwardhan 295222Sksewell@umich.edu */ 305222Sksewell@umich.edu 315222Sksewell@umich.edu#ifndef __ARCH_MIPS_PAGETABLE_H__ 325222Sksewell@umich.edu#define __ARCH_MIPS_PAGETABLE_H__ 335222Sksewell@umich.edu 345222Sksewell@umich.edu#include "arch/mips/isa_traits.hh" 355222Sksewell@umich.edu#include "arch/mips/utility.hh" 365254Sksewell@umich.edu#include "arch/mips/vtophys.hh" 375222Sksewell@umich.edu#include "config/full_system.hh" 385222Sksewell@umich.edu 395222Sksewell@umich.edunamespace MipsISA { 405222Sksewell@umich.edu 415222Sksewell@umich.edu struct VAddr 425222Sksewell@umich.edu { 435222Sksewell@umich.edu static const int ImplBits = 43; 445222Sksewell@umich.edu static const Addr ImplMask = (ULL(1) << ImplBits) - 1; 455222Sksewell@umich.edu static const Addr UnImplMask = ~ImplMask; 465222Sksewell@umich.edu 475222Sksewell@umich.edu VAddr(Addr a) : addr(a) {} 485222Sksewell@umich.edu Addr addr; 495222Sksewell@umich.edu operator Addr() const { return addr; } 505222Sksewell@umich.edu const VAddr &operator=(Addr a) { addr = a; return *this; } 515222Sksewell@umich.edu 525222Sksewell@umich.edu Addr vpn() const { return (addr & ImplMask) >> PageShift; } 535222Sksewell@umich.edu Addr page() const { return addr & Page_Mask; } 545222Sksewell@umich.edu Addr offset() const { return addr & PageOffset; } 555222Sksewell@umich.edu 565222Sksewell@umich.edu Addr level3() const 575222Sksewell@umich.edu { return MipsISA::PteAddr(addr >> PageShift); } 585222Sksewell@umich.edu Addr level2() const 595222Sksewell@umich.edu { return MipsISA::PteAddr(addr >> NPtePageShift + PageShift); } 605222Sksewell@umich.edu Addr level1() const 615222Sksewell@umich.edu { return MipsISA::PteAddr(addr >> 2 * NPtePageShift + PageShift); } 625222Sksewell@umich.edu }; 635222Sksewell@umich.edu 645222Sksewell@umich.edu // ITB/DTB page table entry 655222Sksewell@umich.edu struct PTE 665222Sksewell@umich.edu { 675222Sksewell@umich.edu Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask) 685222Sksewell@umich.edu Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi) 695222Sksewell@umich.edu uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi 705222Sksewell@umich.edu 715222Sksewell@umich.edu bool G; // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit 725222Sksewell@umich.edu 735222Sksewell@umich.edu /* Contents of Entry Lo0 */ 745222Sksewell@umich.edu Addr PFN0; // Physical Frame Number - Even 755222Sksewell@umich.edu bool D0; // Even entry Dirty Bit 765222Sksewell@umich.edu bool V0; // Even entry Valid Bit 775222Sksewell@umich.edu uint8_t C0; // Cache Coherency Bits - Even 785222Sksewell@umich.edu 795222Sksewell@umich.edu /* Contents of Entry Lo1 */ 805222Sksewell@umich.edu Addr PFN1; // Physical Frame Number - Odd 815222Sksewell@umich.edu bool D1; // Odd entry Dirty Bit 825222Sksewell@umich.edu bool V1; // Odd entry Valid Bit 835222Sksewell@umich.edu uint8_t C1; // Cache Coherency Bits (3 bits) 845222Sksewell@umich.edu 855222Sksewell@umich.edu /* The next few variables are put in as optimizations to reduce TLB lookup overheads */ 865222Sksewell@umich.edu /* For a given Mask, what is the address shift amount, and what is the OffsetMask */ 875222Sksewell@umich.edu int AddrShiftAmount; 885222Sksewell@umich.edu int OffsetMask; 895222Sksewell@umich.edu 905222Sksewell@umich.edu bool Valid() { return (V0 | V1);}; 915222Sksewell@umich.edu void serialize(std::ostream &os); 925222Sksewell@umich.edu void unserialize(Checkpoint *cp, const std::string §ion); 935222Sksewell@umich.edu }; 945222Sksewell@umich.edu 955222Sksewell@umich.edu}; 965222Sksewell@umich.edu#endif // __ARCH_MIPS_PAGETABLE_H__ 975222Sksewell@umich.edu 98