isa_traits.hh revision 2972:f84c6c5309ce
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 * Korey Sewell 30 */ 31 32#ifndef __ARCH_MIPS_ISA_TRAITS_HH__ 33#define __ARCH_MIPS_ISA_TRAITS_HH__ 34 35#include "arch/mips/types.hh" 36#include "sim/host.hh" 37 38namespace LittleEndianGuest {}; 39 40#define TARGET_MIPS 41 42class StaticInstPtr; 43 44namespace MipsISA 45{ 46 using namespace LittleEndianGuest; 47 48 StaticInstPtr decodeInst(ExtMachInst); 49 50 const Addr PageShift = 13; 51 const Addr PageBytes = ULL(1) << PageShift; 52 const Addr PageMask = ~(PageBytes - 1); 53 const Addr PageOffset = PageBytes - 1; 54 55 // return a no-op instruction... used for instruction fetch faults 56 const ExtMachInst NoopMachInst = 0x00000000; 57 58 // Constants Related to the number of registers 59 const int NumIntArchRegs = 32; 60 const int NumIntSpecialRegs = 2; 61 const int NumFloatArchRegs = 32; 62 const int NumFloatSpecialRegs = 5; 63 const int NumControlRegs = 265; 64 const int NumInternalProcRegs = 0; 65 66 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs 67 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// 68 const int NumMiscRegs = NumControlRegs; 69 70 const int TotalNumRegs = NumIntRegs + NumFloatRegs + 71 NumMiscRegs + 0/*NumInternalProcRegs*/; 72 73 const int TotalDataRegs = NumIntRegs + NumFloatRegs; 74 75 // Static instruction parameters 76 const int MaxInstSrcRegs = 3; 77 const int MaxInstDestRegs = 2; 78 79 // semantically meaningful register indices 80 const int ZeroReg = 0; 81 const int AssemblerReg = 1; 82 const int ReturnValueReg = 2; 83 const int ReturnValueReg1 = 2; 84 const int ReturnValueReg2 = 3; 85 const int ArgumentReg0 = 4; 86 const int ArgumentReg1 = 5; 87 const int ArgumentReg2 = 6; 88 const int ArgumentReg3 = 7; 89 const int KernelReg0 = 26; 90 const int KernelReg1 = 27; 91 const int GlobalPointerReg = 28; 92 const int StackPointerReg = 29; 93 const int FramePointerReg = 30; 94 const int ReturnAddressReg = 31; 95 96 const int SyscallNumReg = ReturnValueReg1; 97 const int SyscallPseudoReturnReg = ReturnValueReg1; 98 const int SyscallSuccessReg = ArgumentReg3; 99 100 const int LogVMPageSize = 13; // 8K bytes 101 const int VMPageSize = (1 << LogVMPageSize); 102 103 const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned 104 105 const int MachineBytes = 4; 106 const int WordBytes = 4; 107 const int HalfwordBytes = 2; 108 const int ByteBytes = 1; 109 110 // These help enumerate all the registers for dependence tracking. 111 const int FP_Base_DepTag = 34; 112 const int Ctrl_Base_DepTag = 257; 113 114 const int ANNOTE_NONE = 0; 115 const uint32_t ITOUCH_ANNOTE = 0xffffffff; 116 117}; 118 119using namespace MipsISA; 120 121#endif // __ARCH_MIPS_ISA_TRAITS_HH__ 122