operands.isa revision 2495 
1def operand_types {{
2    'sb' : ('signed int', 8),
3    'ub' : ('unsigned int', 8),
4    'sh' : ('signed int', 16),
5    'uh' : ('unsigned int', 16),
6    'sw' : ('signed int', 32),
7    'uw' : ('unsigned int', 32),
8    'sd' : ('signed int', 64),
9    'ud' : ('unsigned int', 64),
10    'sf' : ('float', 32),
11    'df' : ('float', 64),
12    'qf' : ('float', 128)
13}};
14
15def operands {{
16    'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
17    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
18    'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
19    'r31': ('IntReg', 'uw','R31','IsInteger', 4),
20    'R0':  ('IntReg', 'uw','R0', 'IsInteger', 5),
21
22    'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
23
24    'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
25    'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
26    'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
27    'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
28
29    'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
30
31    'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
32    'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
33}};
34