util.isa revision 5736:426510e758ad
19243SN/A// -*- mode:c++ -*- 210206Sandreas.hansson@arm.com 39243SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 49243SN/A// Copyright (c) 2007 MIPS Technologies, Inc. 59243SN/A// All rights reserved. 69243SN/A// 79243SN/A// Redistribution and use in source and binary forms, with or without 89243SN/A// modification, are permitted provided that the following conditions are 99243SN/A// met: redistributions of source code must retain the above copyright 109243SN/A// notice, this list of conditions and the following disclaimer; 119243SN/A// redistributions in binary form must reproduce the above copyright 129243SN/A// notice, this list of conditions and the following disclaimer in the 139243SN/A// documentation and/or other materials provided with the distribution; 149831SN/A// neither the name of the copyright holders nor the names of its 159831SN/A// contributors may be used to endorse or promote products derived from 169831SN/A// this software without specific prior written permission. 179243SN/A// 189243SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 199243SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 209243SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 219243SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 229243SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 239243SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 249243SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 259243SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 269243SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 279243SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 289243SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 299243SN/A// 309243SN/A// Authors: Steve Reinhardt 319243SN/A// Korey Sewell 329243SN/A 339243SN/Alet {{ 349243SN/Adef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 359243SN/A postacc_code = '', base_class = 'Memory', 369243SN/A decode_template = BasicDecode, exec_template_base = ''): 379243SN/A # Make sure flags are in lists (convert to lists if not). 389243SN/A mem_flags = makeList(mem_flags) 399243SN/A inst_flags = makeList(inst_flags) 409243SN/A 419243SN/A # add hook to get effective addresses into execution trace output. 429967SN/A ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' 439243SN/A 449243SN/A # Some CPU models execute the memory operation as an atomic unit, 4510146Sandreas.hansson@arm.com # while others want to separate them into an effective address 469356SN/A # computation and a memory access operation. As a result, we need 4710146Sandreas.hansson@arm.com # to generate three StaticInst objects. Note that the latter two 4810208Sandreas.hansson@arm.com # are nested inside the larger "atomic" one. 499352SN/A 5010146Sandreas.hansson@arm.com # Generate InstObjParams for each of the three objects. Note that 519814SN/A # they differ only in the set of code objects contained (which in 529243SN/A # turn affects the object's overall operand list). 539243SN/A iop = InstObjParams(name, Name, base_class, 549243SN/A { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 5510146Sandreas.hansson@arm.com inst_flags) 569243SN/A ea_iop = InstObjParams(name, Name, base_class, 579243SN/A { 'ea_code':ea_code }, 589243SN/A inst_flags) 5910211Sandreas.hansson@arm.com memacc_iop = InstObjParams(name, Name, base_class, 6010208Sandreas.hansson@arm.com { 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 6110208Sandreas.hansson@arm.com inst_flags) 6210208Sandreas.hansson@arm.com 639831SN/A if mem_flags: 649831SN/A mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] 659831SN/A s = '\n\tmemAccessFlags.reset(' + string.join(mem_flags, '|') + ');' 669831SN/A iop.constructor += s 679831SN/A memacc_iop.constructor += s 6810140SN/A 699243SN/A # select templates 709566SN/A 719243SN/A # The InitiateAcc template is the same for StoreCond templates as the 729243SN/A # corresponding Store template.. 7310140SN/A StoreCondInitiateAcc = StoreInitiateAcc 7410140SN/A 7510147Sandreas.hansson@arm.com memAccExecTemplate = eval(exec_template_base + 'MemAccExecute') 7610147Sandreas.hansson@arm.com fullExecTemplate = eval(exec_template_base + 'Execute') 7710206Sandreas.hansson@arm.com initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 7810210Sandreas.hansson@arm.com completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 7910212Sandreas.hansson@arm.com eaCompExecuteTemplate = eval('EACompExecute') 809488SN/A 819243SN/A if (exec_template_base == 'Load' or exec_template_base == 'Store'): 829243SN/A memAccSizeTemplate = eval('LoadStoreMemAccSize') 8310141SN/A else: 849726SN/A memAccSizeTemplate = eval('MiscMemAccSize') 859726SN/A 8610208Sandreas.hansson@arm.com # (header_output, decoder_output, decode_block, exec_output) 8710208Sandreas.hansson@arm.com return (LoadStoreDeclare.subst(iop), 8810208Sandreas.hansson@arm.com EACompConstructor.subst(ea_iop) 899243SN/A + MemAccConstructor.subst(memacc_iop) 909243SN/A + LoadStoreConstructor.subst(iop), 919243SN/A decode_template.subst(iop), 929243SN/A eaCompExecuteTemplate.subst(ea_iop) 939969SN/A + memAccExecTemplate.subst(memacc_iop) 949243SN/A + fullExecTemplate.subst(iop) 959243SN/A + initiateAccTemplate.subst(iop) 969969SN/A + completeAccTemplate.subst(iop) 979243SN/A + memAccSizeTemplate.subst(memacc_iop)) 989243SN/A}}; 9910140SN/A 10010140SN/Aoutput header {{ 10110140SN/A std::string inst2string(MachInst machInst); 10210140SN/A}}; 10310140SN/A 1049243SN/Aoutput decoder {{ 1059243SN/A 1069567SN/Astd::string inst2string(MachInst machInst) 1079243SN/A{ 1089243SN/A string str = ""; 1099243SN/A uint32_t mask = 0x80000000; 1109831SN/A 1119831SN/A for(int i=0; i < 32; i++) { 1129831SN/A if ((machInst & mask) == 0) { 1139831SN/A str += "0"; 1149831SN/A } else { 1159243SN/A str += "1"; 1169566SN/A } 1179566SN/A 11810143SN/A mask = mask >> 1; 1199566SN/A } 1209566SN/A 12110136SN/A return str; 1229831SN/A} 12310143SN/A 12410136SN/A}}; 1259566SN/A