noop.isa revision 5268
12810SN/A// -*- mode:c++ -*- 22810SN/A 32810SN/A// Copyright (c) 2007 MIPS Technologies, Inc. 42810SN/A// All rights reserved. 52810SN/A// 62810SN/A// Redistribution and use in source and binary forms, with or without 72810SN/A// modification, are permitted provided that the following conditions are 82810SN/A// met: redistributions of source code must retain the above copyright 92810SN/A// notice, this list of conditions and the following disclaimer; 102810SN/A// redistributions in binary form must reproduce the above copyright 112810SN/A// notice, this list of conditions and the following disclaimer in the 122810SN/A// documentation and/or other materials provided with the distribution; 132810SN/A// neither the name of the copyright holders nor the names of its 142810SN/A// contributors may be used to endorse or promote products derived from 152810SN/A// this software without specific prior written permission. 162810SN/A// 172810SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182810SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192810SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202810SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212810SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222810SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232810SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242810SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252810SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262810SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272810SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282810SN/A// 292810SN/A// Authors: Korey Sewell 302810SN/A 312810SN/A//////////////////////////////////////////////////////////////////// 322810SN/A// 332810SN/A// Nop 342810SN/A// 352810SN/A 362810SN/Aoutput header {{ 372810SN/A /** 382810SN/A * Static instruction class for no-ops. This is a leaf class. 394626SN/A */ 404626SN/A class Nop : public MipsStaticInst 415314SN/A { 422810SN/A /// Disassembly of original instruction. 432810SN/A const std::string originalDisassembly; 444626SN/A 454626SN/A public: 462810SN/A /// Constructor 472810SN/A Nop(const std::string _originalDisassembly, MachInst _machInst) 482810SN/A : MipsStaticInst("nop", _machInst, No_OpClass), 493374SN/A originalDisassembly(_originalDisassembly) 502810SN/A { 515314SN/A flags[IsNop] = true; 524626SN/A } 534626SN/A 542810SN/A ~Nop() { } 554626SN/A 564626SN/A std::string 574626SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 585875Ssteve.reinhardt@amd.com 595875Ssteve.reinhardt@amd.com %(BasicExecDeclare)s 605875Ssteve.reinhardt@amd.com }; 615875Ssteve.reinhardt@amd.com}}; 625875Ssteve.reinhardt@amd.com 635875Ssteve.reinhardt@amd.comoutput decoder {{ 645875Ssteve.reinhardt@amd.com std::string Nop::generateDisassembly(Addr pc, 654871SN/A const SymbolTable *symtab) const 664871SN/A { 674666SN/A return csprintf("%-10s %s", "nop", originalDisassembly); 684626SN/A } 695875Ssteve.reinhardt@amd.com 705318SN/A /// Helper function for decoding nops. Substitute Nop object 715318SN/A /// for original inst passed in as arg (and delete latter). 724626SN/A inline 735318SN/A MipsStaticInst * 745875Ssteve.reinhardt@amd.com makeNop(MipsStaticInst *inst) 757823Ssteve.reinhardt@amd.com { 765875Ssteve.reinhardt@amd.com std::string nop_str = "(" + inst->disassemble(0) + ")"; 774626SN/A MipsStaticInst *nop = new Nop(nop_str, inst->machInst); 784626SN/A delete inst; 794626SN/A return nop; 804903SN/A } 814903SN/A}}; 824903SN/A 835314SN/Aoutput exec {{ 844903SN/A Fault 854903SN/A Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const 864903SN/A { 874903SN/A return NoFault; 884903SN/A } 894903SN/A}}; 904903SN/A 914903SN/A// Int & FP operate instructions use RD as dest, so check for 925318SN/A// RD == 0 to detect nops 935875Ssteve.reinhardt@amd.comdef template RegNopCheckDecode {{ 944903SN/A { 954908SN/A MipsStaticInst *i = new %(class_name)s(machInst); 964920SN/A //if (RD == 0) { 975314SN/A //i = makeNop(i); 985314SN/A //} 994903SN/A return i; 1004903SN/A } 1012810SN/A}}; 1022810SN/A 1032810SN/Adef template OperateNopCheckDecode {{ 1042810SN/A { 1052810SN/A MipsStaticInst *i = new %(class_name)s(machInst); 1062810SN/A //if (RD == 0) { 1072810SN/A // i = makeNop(i); 1084626SN/A //} 1094626SN/A return i; 1104626SN/A } 1114666SN/A}}; 1124871SN/A 1134666SN/A// IntImm & Memory instructions use Rt as dest, so check for 1144666SN/A// Rt == 0 to detect nops 1154666SN/Adef template ImmNopCheckDecode {{ 1164666SN/A { 1174626SN/A MipsStaticInst *i = new %(class_name)s(machInst); 1182810SN/A //if (RT == 0) { 1194626SN/A // i = makeNop(i); 1204626SN/A // } 1214626SN/A return i; 1224626SN/A } 1233374SN/A}}; 1242810SN/A 1254626SN/A 1265730SSteve.Reinhardt@amd.com// Like BasicOperate format, but generates NOP if RC/FC == 31 1275730SSteve.Reinhardt@amd.comdef format BasicOperateWithNopCheck(code, *opt_args) {{ 1284903SN/A iop = InstObjParams(name, Name, 'MipsStaticInst', code, 1294626SN/A opt_args) 1305314SN/A header_output = BasicDeclare.subst(iop) 1314665SN/A decoder_output = BasicConstructor.subst(iop) 1324626SN/A decode_block = OperateNopCheckDecode.subst(iop) 1334626SN/A exec_output = BasicExecute.subst(iop) 1344626SN/A}}; 1354908SN/A 1364908SN/Adef format Nop() {{ 1377667Ssteve.reinhardt@amd.com decode_block = 'return new Nop(\"\",machInst);\n' 1387667Ssteve.reinhardt@amd.com}}; 1397667Ssteve.reinhardt@amd.com 1407667Ssteve.reinhardt@amd.com