noop.isa revision 2750
12101SN/A// -*- mode:c++ -*- 22084SN/A 32084SN/A//////////////////////////////////////////////////////////////////// 42084SN/A// 52084SN/A// Nop 62084SN/A// 72084SN/A 82084SN/Aoutput header {{ 92084SN/A /** 102084SN/A * Static instruction class for no-ops. This is a leaf class. 112084SN/A */ 122101SN/A class Nop : public MipsStaticInst 132084SN/A { 142084SN/A /// Disassembly of original instruction. 152084SN/A const std::string originalDisassembly; 162084SN/A 172084SN/A public: 182084SN/A /// Constructor 192084SN/A Nop(const std::string _originalDisassembly, MachInst _machInst) 202101SN/A : MipsStaticInst("nop", _machInst, No_OpClass), 212084SN/A originalDisassembly(_originalDisassembly) 222084SN/A { 232084SN/A flags[IsNop] = true; 242084SN/A } 252084SN/A 262084SN/A ~Nop() { } 272084SN/A 282084SN/A std::string 292084SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 302084SN/A 312084SN/A %(BasicExecDeclare)s 322084SN/A }; 332084SN/A}}; 342084SN/A 352084SN/Aoutput decoder {{ 362084SN/A std::string Nop::generateDisassembly(Addr pc, 372084SN/A const SymbolTable *symtab) const 382084SN/A { 392686Sksewell@umich.edu return csprintf("%-10s %s", "nop", originalDisassembly); 402084SN/A } 412084SN/A 422084SN/A /// Helper function for decoding nops. Substitute Nop object 432084SN/A /// for original inst passed in as arg (and delete latter). 442084SN/A inline 452101SN/A MipsStaticInst * 462101SN/A makeNop(MipsStaticInst *inst) 472084SN/A { 482750Sksewell@umich.edu std::string nop_str = "(" + inst->disassemble(0) + ")"; 492750Sksewell@umich.edu MipsStaticInst *nop = new Nop(nop_str, inst->machInst); 502084SN/A delete inst; 512084SN/A return nop; 522084SN/A } 532084SN/A}}; 542084SN/A 552084SN/Aoutput exec {{ 562084SN/A Fault 572084SN/A Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const 582084SN/A { 592239SN/A return NoFault; 602084SN/A } 612084SN/A}}; 622084SN/A 632750Sksewell@umich.edu// Int & FP operate instructions use RD as dest, so check for 642750Sksewell@umich.edu// RD == 0 to detect nops 652750Sksewell@umich.edudef template RegNopCheckDecode {{ 662750Sksewell@umich.edu { 672750Sksewell@umich.edu MipsStaticInst *i = new %(class_name)s(machInst); 682750Sksewell@umich.edu //if (RD == 0) { 692750Sksewell@umich.edu //i = makeNop(i); 702750Sksewell@umich.edu //} 712750Sksewell@umich.edu return i; 722750Sksewell@umich.edu } 732750Sksewell@umich.edu}}; 742750Sksewell@umich.edu 752084SN/Adef template OperateNopCheckDecode {{ 762084SN/A { 772101SN/A MipsStaticInst *i = new %(class_name)s(machInst); 782750Sksewell@umich.edu //if (RD == 0) { 792750Sksewell@umich.edu // i = makeNop(i); 802750Sksewell@umich.edu //} 812750Sksewell@umich.edu return i; 822750Sksewell@umich.edu } 832750Sksewell@umich.edu}}; 842239SN/A 852750Sksewell@umich.edu// IntImm & Memory instructions use Rt as dest, so check for 862750Sksewell@umich.edu// Rt == 0 to detect nops 872750Sksewell@umich.edudef template ImmNopCheckDecode {{ 882750Sksewell@umich.edu { 892750Sksewell@umich.edu MipsStaticInst *i = new %(class_name)s(machInst); 902750Sksewell@umich.edu //if (RT == 0) { 912750Sksewell@umich.edu // i = makeNop(i); 922750Sksewell@umich.edu // } 932084SN/A return i; 942084SN/A } 952084SN/A}}; 962084SN/A 972084SN/A 982084SN/A// Like BasicOperate format, but generates NOP if RC/FC == 31 992084SN/Adef format BasicOperateWithNopCheck(code, *opt_args) {{ 1002101SN/A iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), 1012084SN/A opt_args) 1022084SN/A header_output = BasicDeclare.subst(iop) 1032084SN/A decoder_output = BasicConstructor.subst(iop) 1042084SN/A decode_block = OperateNopCheckDecode.subst(iop) 1052084SN/A exec_output = BasicExecute.subst(iop) 1062084SN/A}}; 1072084SN/A 1082470SN/Adef format Nop() {{ 1092686Sksewell@umich.edu decode_block = 'return new Nop(\"\",machInst);\n' 1102470SN/A}}; 1112470SN/A 112