mt.isa revision 8607:5fb918115c07
1955SN/A// -*- mode:c++ -*- 2955SN/A 31762SN/A// Copyright (c) 2007 MIPS Technologies, Inc. 4955SN/A// All rights reserved. 5955SN/A// 6955SN/A// Redistribution and use in source and binary forms, with or without 7955SN/A// modification, are permitted provided that the following conditions are 8955SN/A// met: redistributions of source code must retain the above copyright 9955SN/A// notice, this list of conditions and the following disclaimer; 10955SN/A// redistributions in binary form must reproduce the above copyright 11955SN/A// notice, this list of conditions and the following disclaimer in the 12955SN/A// documentation and/or other materials provided with the distribution; 13955SN/A// neither the name of the copyright holders nor the names of its 14955SN/A// contributors may be used to endorse or promote products derived from 15955SN/A// this software without specific prior written permission. 16955SN/A// 17955SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18955SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19955SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20955SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21955SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22955SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23955SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24955SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25955SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26955SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27955SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Korey Sewell 305863Snate@binkert.org 31955SN/A//////////////////////////////////////////////////////////////////// 32955SN/A// 33955SN/A// MT instructions 34955SN/A// 35955SN/A 362632Sstever@eecs.umich.eduoutput header {{ 372632Sstever@eecs.umich.edu /** 382632Sstever@eecs.umich.edu * Base class for MIPS MT ASE operations. 392632Sstever@eecs.umich.edu */ 40955SN/A class MTOp : public MipsStaticInst 412632Sstever@eecs.umich.edu { 422632Sstever@eecs.umich.edu protected: 432761Sstever@eecs.umich.edu 442632Sstever@eecs.umich.edu /// Constructor 452632Sstever@eecs.umich.edu MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 462632Sstever@eecs.umich.edu MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 472761Sstever@eecs.umich.edu { 482761Sstever@eecs.umich.edu } 492761Sstever@eecs.umich.edu 502632Sstever@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 512632Sstever@eecs.umich.edu 522761Sstever@eecs.umich.edu bool user_mode; 532761Sstever@eecs.umich.edu }; 542761Sstever@eecs.umich.edu 552761Sstever@eecs.umich.edu class MTUserModeOp : public MTOp 562761Sstever@eecs.umich.edu { 572632Sstever@eecs.umich.edu protected: 582632Sstever@eecs.umich.edu 592632Sstever@eecs.umich.edu /// Constructor 602632Sstever@eecs.umich.edu MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 612632Sstever@eecs.umich.edu MTOp(mnem, _machInst, __opClass) 622632Sstever@eecs.umich.edu { 632632Sstever@eecs.umich.edu user_mode = true; 64955SN/A } 65955SN/A 66955SN/A //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 675863Snate@binkert.org }; 685863Snate@binkert.org}}; 695863Snate@binkert.org 705863Snate@binkert.orgoutput decoder {{ 715863Snate@binkert.org std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 725863Snate@binkert.org { 735863Snate@binkert.org std::stringstream ss; 745863Snate@binkert.org 755863Snate@binkert.org if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) { 765863Snate@binkert.org ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 775863Snate@binkert.org } else if (strcmp(mnemonic,"mftgpr") == 0) { 785863Snate@binkert.org ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 795863Snate@binkert.org } else { 805863Snate@binkert.org ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 815863Snate@binkert.org } 825863Snate@binkert.org 835863Snate@binkert.org return ss.str(); 845863Snate@binkert.org } 855863Snate@binkert.org}}; 865863Snate@binkert.org 875863Snate@binkert.orgoutput exec {{ 885863Snate@binkert.org void getThrRegExValues(%(CPU_exec_context)s *xc, 895863Snate@binkert.org VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt, 905863Snate@binkert.org TCBindReg &tc_bind, VPEControlReg &vpe_control, 915863Snate@binkert.org MVPConf0Reg &mvp_conf0) 925863Snate@binkert.org { 935863Snate@binkert.org vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); 945863Snate@binkert.org tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag); 955863Snate@binkert.org tc_bind = xc->readMiscReg(MISCREG_TC_BIND); 965863Snate@binkert.org vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); 975863Snate@binkert.org mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); 98955SN/A } 995396Ssaidi@eecs.umich.edu 1005863Snate@binkert.org void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3) 1015863Snate@binkert.org { 1024202Sbinkertn@umich.edu config3 = xc->readMiscReg(MISCREG_CONFIG3); 1035863Snate@binkert.org } 1045863Snate@binkert.org}}; 1055863Snate@binkert.org 1065863Snate@binkert.orgdef template ThreadRegisterExecute {{ 107955SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1085273Sstever@gmail.com { 1095273Sstever@gmail.com Fault fault = NoFault; 1105863Snate@binkert.org int64_t data M5_VAR_USED; 1115863Snate@binkert.org %(op_decl)s; 1125863Snate@binkert.org %(op_rd)s; 1135863Snate@binkert.org 1145863Snate@binkert.org VPEConf0Reg vpeConf0; 1155863Snate@binkert.org TCBindReg tcBindMT; 1165227Ssaidi@eecs.umich.edu TCBindReg tcBind; 1175396Ssaidi@eecs.umich.edu VPEControlReg vpeControl; 1185396Ssaidi@eecs.umich.edu MVPConf0Reg mvpConf0; 1195396Ssaidi@eecs.umich.edu 1205396Ssaidi@eecs.umich.edu getThrRegExValues(xc, vpeConf0, tcBindMT, 1215396Ssaidi@eecs.umich.edu tcBind, vpeControl, mvpConf0); 1225396Ssaidi@eecs.umich.edu 1235396Ssaidi@eecs.umich.edu if (isCoprocessorEnabled(xc, 0)) { 1245396Ssaidi@eecs.umich.edu if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) { 1255588Ssaidi@eecs.umich.edu data = -1; 1265396Ssaidi@eecs.umich.edu } else if (vpeControl.targTC > mvpConf0.ptc) { 1275396Ssaidi@eecs.umich.edu data = -1; 1285396Ssaidi@eecs.umich.edu } else { 1295396Ssaidi@eecs.umich.edu %(code)s; 1305396Ssaidi@eecs.umich.edu } 1315396Ssaidi@eecs.umich.edu } else { 1325396Ssaidi@eecs.umich.edu fault = new CoprocessorUnusableFault(0); 1335396Ssaidi@eecs.umich.edu } 1345396Ssaidi@eecs.umich.edu 1355396Ssaidi@eecs.umich.edu if(fault == NoFault) 1365396Ssaidi@eecs.umich.edu { 1375396Ssaidi@eecs.umich.edu %(op_wb)s; 1385396Ssaidi@eecs.umich.edu } 1395396Ssaidi@eecs.umich.edu 140955SN/A return fault; 141955SN/A } 142955SN/A}}; 1433717Sstever@eecs.umich.edu 1443716Sstever@eecs.umich.edudef template MTExecute{{ 145955SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1461533SN/A { 1473716Sstever@eecs.umich.edu Fault fault = NoFault; 1481533SN/A %(op_decl)s; 1495863Snate@binkert.org %(op_rd)s; 1505863Snate@binkert.org 1515863Snate@binkert.org Config3Reg config3; 1525863Snate@binkert.org 1535863Snate@binkert.org getMTExValues(xc, config3); 1545863Snate@binkert.org 1555863Snate@binkert.org if (isCoprocessorEnabled(xc, 0)) { 1565863Snate@binkert.org if (config3.mt == 1) { 1575863Snate@binkert.org %(code)s; 1585863Snate@binkert.org } else { 1595863Snate@binkert.org fault = new ReservedInstructionFault(); 1605863Snate@binkert.org } 1615863Snate@binkert.org } else { 1625863Snate@binkert.org fault = new CoprocessorUnusableFault(0); 1635863Snate@binkert.org } 1645863Snate@binkert.org 1655863Snate@binkert.org if(fault == NoFault) 1665863Snate@binkert.org { 1675863Snate@binkert.org %(op_wb)s; 1684678Snate@binkert.org } 1694678Snate@binkert.org return fault; 1704678Snate@binkert.org } 1714678Snate@binkert.org}}; 1724678Snate@binkert.org 1734678Snate@binkert.org// Primary format for integer operate instructions: 1744678Snate@binkert.orgdef format MT_Control(code, *opt_flags) {{ 1754678Snate@binkert.org inst_flags = ('IsNonSpeculative', ) 1764678Snate@binkert.org op_type = 'MTOp' 1774678Snate@binkert.org 1784678Snate@binkert.org for x in opt_flags: 1794678Snate@binkert.org if x == 'UserMode': 1804678Snate@binkert.org op_type = 'MTUserModeOp' 1814678Snate@binkert.org else: 1824678Snate@binkert.org inst_flags += (x, ) 1834678Snate@binkert.org 1844678Snate@binkert.org iop = InstObjParams(name, Name, op_type, code, inst_flags) 1854678Snate@binkert.org header_output = BasicDeclare.subst(iop) 1864678Snate@binkert.org decoder_output = BasicConstructor.subst(iop) 1874678Snate@binkert.org decode_block = BasicDecode.subst(iop) 1884678Snate@binkert.org exec_output = MTExecute.subst(iop) 1894973Ssaidi@eecs.umich.edu}}; 1904678Snate@binkert.org 1914678Snate@binkert.orgdef format MT_MFTR(code, *flags) {{ 1924678Snate@binkert.org flags += ('IsNonSpeculative', ) 1934678Snate@binkert.org# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 1944678Snate@binkert.org 1954678Snate@binkert.org code += ''' 1965863Snate@binkert.org if (MT_H) 197955SN/A data = bits(data, 63, 32); 198955SN/A Rd = data; 1992632Sstever@eecs.umich.edu ''' 2002632Sstever@eecs.umich.edu 201955SN/A iop = InstObjParams(name, Name, 'MTOp', code, flags) 202955SN/A header_output = BasicDeclare.subst(iop) 203955SN/A decoder_output = BasicConstructor.subst(iop) 204955SN/A decode_block = BasicDecode.subst(iop) 2055863Snate@binkert.org exec_output = ThreadRegisterExecute.subst(iop) 206955SN/A}}; 2072632Sstever@eecs.umich.edu 2082632Sstever@eecs.umich.edudef format MT_MTTR(code, *flags) {{ 2092632Sstever@eecs.umich.edu flags += ('IsNonSpeculative', ) 2102632Sstever@eecs.umich.edu# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2112632Sstever@eecs.umich.edu iop = InstObjParams(name, Name, 'MTOp', code, flags) 2122632Sstever@eecs.umich.edu header_output = BasicDeclare.subst(iop) 2132632Sstever@eecs.umich.edu decoder_output = BasicConstructor.subst(iop) 2142632Sstever@eecs.umich.edu decode_block = BasicDecode.subst(iop) 2152632Sstever@eecs.umich.edu exec_output = ThreadRegisterExecute.subst(iop) 2162632Sstever@eecs.umich.edu}}; 2172632Sstever@eecs.umich.edu