mt.isa revision 12104:edd63f9c6184
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30 31//////////////////////////////////////////////////////////////////// 32// 33// MT instructions 34// 35 36output header {{ 37 /** 38 * Base class for MIPS MT ASE operations. 39 */ 40 class MTOp : public MipsStaticInst 41 { 42 protected: 43 44 /// Constructor 45 MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 46 MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 47 { 48 } 49 50 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 51 52 bool user_mode; 53 }; 54 55 class MTUserModeOp : public MTOp 56 { 57 protected: 58 59 /// Constructor 60 MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 61 MTOp(mnem, _machInst, __opClass) 62 { 63 user_mode = true; 64 } 65 66 //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 67 }; 68}}; 69 70output decoder {{ 71 std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 72 { 73 std::stringstream ss; 74 75 if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) { 76 ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 77 } else if (strcmp(mnemonic,"mftgpr") == 0) { 78 ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 79 } else { 80 ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 81 } 82 83 return ss.str(); 84 } 85}}; 86 87output header {{ 88 void getThrRegExValues(%(CPU_exec_context)s *xc, 89 MipsISA::VPEConf0Reg &vpe_conf0, 90 MipsISA::TCBindReg &tc_bind_mt, 91 MipsISA::TCBindReg &tc_bind, 92 MipsISA::VPEControlReg &vpe_control, 93 MipsISA::MVPConf0Reg &mvp_conf0); 94 95 void getMTExValues(%(CPU_exec_context)s *xc, MipsISA::Config3Reg &config3); 96}}; 97 98output exec {{ 99 void getThrRegExValues(CPU_EXEC_CONTEXT *xc, 100 VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt, 101 TCBindReg &tc_bind, VPEControlReg &vpe_control, 102 MVPConf0Reg &mvp_conf0) 103 { 104 vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); 105 tc_bind_mt = xc->readRegOtherThread(RegId(MiscRegClass, 106 MISCREG_TC_BIND)); 107 tc_bind = xc->readMiscReg(MISCREG_TC_BIND); 108 vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); 109 mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); 110 } 111 112 void getMTExValues(CPU_EXEC_CONTEXT *xc, Config3Reg &config3) 113 { 114 config3 = xc->readMiscReg(MISCREG_CONFIG3); 115 } 116}}; 117 118def template ThreadRegisterExecute {{ 119 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 120 { 121 Fault fault = NoFault; 122 int64_t data M5_VAR_USED; 123 %(op_decl)s; 124 %(op_rd)s; 125 126 VPEConf0Reg vpeConf0; 127 TCBindReg tcBindMT; 128 TCBindReg tcBind; 129 VPEControlReg vpeControl; 130 MVPConf0Reg mvpConf0; 131 132 getThrRegExValues(xc, vpeConf0, tcBindMT, 133 tcBind, vpeControl, mvpConf0); 134 135 if (isCoprocessorEnabled(xc, 0)) { 136 if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) { 137 data = -1; 138 } else if (vpeControl.targTC > mvpConf0.ptc) { 139 data = -1; 140 } else { 141 %(code)s; 142 } 143 } else { 144 fault = std::make_shared<CoprocessorUnusableFault>(0); 145 } 146 147 if(fault == NoFault) 148 { 149 %(op_wb)s; 150 } 151 152 return fault; 153 } 154}}; 155 156def template MTExecute{{ 157 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 158 { 159 Fault fault = NoFault; 160 %(op_decl)s; 161 %(op_rd)s; 162 163 Config3Reg config3; 164 165 getMTExValues(xc, config3); 166 167 if (isCoprocessorEnabled(xc, 0)) { 168 if (config3.mt == 1) { 169 %(code)s; 170 } else { 171 fault = std::make_shared<ReservedInstructionFault>(); 172 } 173 } else { 174 fault = std::make_shared<CoprocessorUnusableFault>(0); 175 } 176 177 if(fault == NoFault) 178 { 179 %(op_wb)s; 180 } 181 return fault; 182 } 183}}; 184 185// Primary format for integer operate instructions: 186def format MT_Control(code, *opt_flags) {{ 187 inst_flags = ('IsNonSpeculative', ) 188 op_type = 'MTOp' 189 190 for x in opt_flags: 191 if x == 'UserMode': 192 op_type = 'MTUserModeOp' 193 else: 194 inst_flags += (x, ) 195 196 iop = InstObjParams(name, Name, op_type, code, inst_flags) 197 header_output = BasicDeclare.subst(iop) 198 decoder_output = BasicConstructor.subst(iop) 199 decode_block = BasicDecode.subst(iop) 200 exec_output = MTExecute.subst(iop) 201}}; 202 203def format MT_MFTR(code, *flags) {{ 204 flags += ('IsNonSpeculative', ) 205# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 206 207 code += ''' 208 if (MT_H) 209 data = bits(data, 63, 32); 210 Rd = data; 211 ''' 212 213 iop = InstObjParams(name, Name, 'MTOp', code, flags) 214 header_output = BasicDeclare.subst(iop) 215 decoder_output = BasicConstructor.subst(iop) 216 decode_block = BasicDecode.subst(iop) 217 exec_output = ThreadRegisterExecute.subst(iop) 218}}; 219 220def format MT_MTTR(code, *flags) {{ 221 flags += ('IsNonSpeculative', ) 222# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 223 iop = InstObjParams(name, Name, 'MTOp', code, flags) 224 header_output = BasicDeclare.subst(iop) 225 decoder_output = BasicConstructor.subst(iop) 226 decode_block = BasicDecode.subst(iop) 227 exec_output = ThreadRegisterExecute.subst(iop) 228}}; 229