mt.isa revision 9554
11689SN/A// -*- mode:c++ -*- 29444SAndreas.Sandberg@ARM.com 39444SAndreas.Sandberg@ARM.com// Copyright (c) 2007 MIPS Technologies, Inc. 49444SAndreas.Sandberg@ARM.com// All rights reserved. 59444SAndreas.Sandberg@ARM.com// 69444SAndreas.Sandberg@ARM.com// Redistribution and use in source and binary forms, with or without 79444SAndreas.Sandberg@ARM.com// modification, are permitted provided that the following conditions are 89444SAndreas.Sandberg@ARM.com// met: redistributions of source code must retain the above copyright 99444SAndreas.Sandberg@ARM.com// notice, this list of conditions and the following disclaimer; 109444SAndreas.Sandberg@ARM.com// redistributions in binary form must reproduce the above copyright 119444SAndreas.Sandberg@ARM.com// notice, this list of conditions and the following disclaimer in the 129444SAndreas.Sandberg@ARM.com// documentation and/or other materials provided with the distribution; 139444SAndreas.Sandberg@ARM.com// neither the name of the copyright holders nor the names of its 142329SN/A// contributors may be used to endorse or promote products derived from 151689SN/A// this software without specific prior written permission. 161689SN/A// 171689SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 281689SN/A// 291689SN/A// Authors: Korey Sewell 301689SN/A 311689SN/A//////////////////////////////////////////////////////////////////// 321689SN/A// 331689SN/A// MT instructions 341689SN/A// 351689SN/A 361689SN/Aoutput header {{ 371689SN/A /** 381689SN/A * Base class for MIPS MT ASE operations. 392665Ssaidi@eecs.umich.edu */ 402665Ssaidi@eecs.umich.edu class MTOp : public MipsStaticInst 412831Sksewell@umich.edu { 421689SN/A protected: 431689SN/A 449944Smatt.horsnell@ARM.com /// Constructor 459944Smatt.horsnell@ARM.com MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 469944Smatt.horsnell@ARM.com MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 476221Snate@binkert.org { 486221Snate@binkert.org } 4913449Sgabeblack@google.com 501717SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 518232Snate@binkert.org 528232Snate@binkert.org bool user_mode; 539954SFaissal.Sleiman@arm.com }; 541060SN/A 556221Snate@binkert.org class MTUserModeOp : public MTOp 562292SN/A { 571061SN/A protected: 589954SFaissal.Sleiman@arm.com 5913562Snikos.nikoleris@arm.com /// Constructor 6013562Snikos.nikoleris@arm.com MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 619954SFaissal.Sleiman@arm.com MTOp(mnem, _machInst, __opClass) 629954SFaissal.Sleiman@arm.com { 631060SN/A user_mode = true; 649954SFaissal.Sleiman@arm.com } 651060SN/A 662292SN/A //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 6713562Snikos.nikoleris@arm.com }; 682292SN/A}}; 696221Snate@binkert.org 706221Snate@binkert.orgoutput decoder {{ 712292SN/A std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 722292SN/A { 7313562Snikos.nikoleris@arm.com std::stringstream ss; 744329Sktlim@umich.edu 752292SN/A if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) { 762292SN/A ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 772292SN/A } else if (strcmp(mnemonic,"mftgpr") == 0) { 782292SN/A ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 792292SN/A } else { 806221Snate@binkert.org ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 816221Snate@binkert.org } 822292SN/A 832292SN/A return ss.str(); 8413562Snikos.nikoleris@arm.com } 854329Sktlim@umich.edu}}; 862292SN/A 879954SFaissal.Sleiman@arm.comoutput header {{ 882292SN/A void getThrRegExValues(%(CPU_exec_context)s *xc, 892292SN/A MipsISA::VPEConf0Reg &vpe_conf0, 906221Snate@binkert.org MipsISA::TCBindReg &tc_bind_mt, 916221Snate@binkert.org MipsISA::TCBindReg &tc_bind, 922292SN/A MipsISA::VPEControlReg &vpe_control, 932292SN/A MipsISA::MVPConf0Reg &mvp_conf0); 9413562Snikos.nikoleris@arm.com 9513453Srekai.gonzalezalberquilla@arm.com void getMTExValues(%(CPU_exec_context)s *xc, MipsISA::Config3Reg &config3); 9613453Srekai.gonzalezalberquilla@arm.com}}; 9713453Srekai.gonzalezalberquilla@arm.com 981060SN/Aoutput exec {{ 999444SAndreas.Sandberg@ARM.com void getThrRegExValues(%(CPU_exec_context)s *xc, 1009444SAndreas.Sandberg@ARM.com VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt, 1019444SAndreas.Sandberg@ARM.com TCBindReg &tc_bind, VPEControlReg &vpe_control, 1029444SAndreas.Sandberg@ARM.com MVPConf0Reg &mvp_conf0) 1039444SAndreas.Sandberg@ARM.com { 1049444SAndreas.Sandberg@ARM.com vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); 1059444SAndreas.Sandberg@ARM.com tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag); 10613453Srekai.gonzalezalberquilla@arm.com tc_bind = xc->readMiscReg(MISCREG_TC_BIND); 1079444SAndreas.Sandberg@ARM.com vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); 1086221Snate@binkert.org mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); 1099444SAndreas.Sandberg@ARM.com } 11013453Srekai.gonzalezalberquilla@arm.com 1112292SN/A void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3) 1129444SAndreas.Sandberg@ARM.com { 1131060SN/A config3 = xc->readMiscReg(MISCREG_CONFIG3); 1142292SN/A } 1152292SN/A}}; 1162292SN/A 1172292SN/Adef template ThreadRegisterExecute {{ 1182292SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1192292SN/A { 1202292SN/A Fault fault = NoFault; 1214329Sktlim@umich.edu int64_t data M5_VAR_USED; 1224329Sktlim@umich.edu %(op_decl)s; 1234329Sktlim@umich.edu %(op_rd)s; 1244329Sktlim@umich.edu 1254329Sktlim@umich.edu VPEConf0Reg vpeConf0; 1264329Sktlim@umich.edu TCBindReg tcBindMT; 1274329Sktlim@umich.edu TCBindReg tcBind; 1282292SN/A VPEControlReg vpeControl; 1296221Snate@binkert.org MVPConf0Reg mvpConf0; 1302292SN/A 1312292SN/A getThrRegExValues(xc, vpeConf0, tcBindMT, 1322292SN/A tcBind, vpeControl, mvpConf0); 1332292SN/A 1342292SN/A if (isCoprocessorEnabled(xc, 0)) { 1352307SN/A if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) { 1362307SN/A data = -1; 1379444SAndreas.Sandberg@ARM.com } else if (vpeControl.targTC > mvpConf0.ptc) { 1382307SN/A data = -1; 1399444SAndreas.Sandberg@ARM.com } else { 1409444SAndreas.Sandberg@ARM.com %(code)s; 1419444SAndreas.Sandberg@ARM.com } 1422307SN/A } else { 1432307SN/A fault = new CoprocessorUnusableFault(0); 1442307SN/A } 1452307SN/A 1462307SN/A if(fault == NoFault) 1472307SN/A { 1489444SAndreas.Sandberg@ARM.com %(op_wb)s; 1492307SN/A } 1502292SN/A 1512292SN/A return fault; 1522292SN/A } 1532292SN/A}}; 1542292SN/A 15513562Snikos.nikoleris@arm.comdef template MTExecute{{ 15614016SAndrea.Mondelli@ucf.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1572292SN/A { 1586221Snate@binkert.org Fault fault = NoFault; 1596221Snate@binkert.org %(op_decl)s; 1602292SN/A %(op_rd)s; 1613867Sbinkertn@umich.edu 1626221Snate@binkert.org Config3Reg config3; 1633867Sbinkertn@umich.edu 16413562Snikos.nikoleris@arm.com getMTExValues(xc, config3); 1653867Sbinkertn@umich.edu 16613562Snikos.nikoleris@arm.com if (isCoprocessorEnabled(xc, 0)) { 16713562Snikos.nikoleris@arm.com if (config3.mt == 1) { 1683867Sbinkertn@umich.edu %(code)s; 1692292SN/A } else { 1702292SN/A fault = new ReservedInstructionFault(); 1712292SN/A } 1722292SN/A } else { 1732292SN/A fault = new CoprocessorUnusableFault(0); 1742292SN/A } 1752292SN/A 1766221Snate@binkert.org if(fault == NoFault) 1772292SN/A { 17813562Snikos.nikoleris@arm.com %(op_wb)s; 1792292SN/A } 1802292SN/A return fault; 1812292SN/A } 1822292SN/A}}; 1831060SN/A 1841060SN/A// Primary format for integer operate instructions: 1851061SN/Adef format MT_Control(code, *opt_flags) {{ 1861060SN/A inst_flags = ('IsNonSpeculative', ) 1871060SN/A op_type = 'MTOp' 1881060SN/A 1896221Snate@binkert.org for x in opt_flags: 1901061SN/A if x == 'UserMode': 1916221Snate@binkert.org op_type = 'MTUserModeOp' 1926221Snate@binkert.org else: 1931060SN/A inst_flags += (x, ) 1942292SN/A 1952292SN/A iop = InstObjParams(name, Name, op_type, code, inst_flags) 1961060SN/A header_output = BasicDeclare.subst(iop) 1972292SN/A decoder_output = BasicConstructor.subst(iop) 19814016SAndrea.Mondelli@ucf.edu decode_block = BasicDecode.subst(iop) 1996221Snate@binkert.org exec_output = MTExecute.subst(iop) 2002292SN/A}}; 2012292SN/A 2021060SN/Adef format MT_MFTR(code, *flags) {{ 2031060SN/A flags += ('IsNonSpeculative', ) 2041061SN/A# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2051060SN/A 20613429Srekai.gonzalezalberquilla@arm.com code += ''' 2071060SN/A if (MT_H) 2081060SN/A data = bits(data, 63, 32); 2091060SN/A Rd = data; 2107897Shestness@cs.utexas.edu ''' 2117897Shestness@cs.utexas.edu 2127720Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'MTOp', code, flags) 2131060SN/A header_output = BasicDeclare.subst(iop) 2141060SN/A decoder_output = BasicConstructor.subst(iop) 2151060SN/A decode_block = BasicDecode.subst(iop) 2166221Snate@binkert.org exec_output = ThreadRegisterExecute.subst(iop) 2171060SN/A}}; 2182292SN/A 2192292SN/Adef format MT_MTTR(code, *flags) {{ 2202292SN/A flags += ('IsNonSpeculative', ) 2212292SN/A# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2222292SN/A iop = InstObjParams(name, Name, 'MTOp', code, flags) 2232292SN/A header_output = BasicDeclare.subst(iop) 2241060SN/A decoder_output = BasicConstructor.subst(iop) 2251060SN/A decode_block = BasicDecode.subst(iop) 2262292SN/A exec_output = ThreadRegisterExecute.subst(iop) 2272292SN/A}}; 2282292SN/A