mt.isa revision 5269
11689SN/A// -*- mode:c++ -*- 27598Sminkyu.jeong@arm.com 37598Sminkyu.jeong@arm.com// Copyright (c) 2007 MIPS Technologies, Inc. 47598Sminkyu.jeong@arm.com// All rights reserved. 57598Sminkyu.jeong@arm.com// 67598Sminkyu.jeong@arm.com// Redistribution and use in source and binary forms, with or without 77598Sminkyu.jeong@arm.com// modification, are permitted provided that the following conditions are 87598Sminkyu.jeong@arm.com// met: redistributions of source code must retain the above copyright 97598Sminkyu.jeong@arm.com// notice, this list of conditions and the following disclaimer; 107598Sminkyu.jeong@arm.com// redistributions in binary form must reproduce the above copyright 117598Sminkyu.jeong@arm.com// notice, this list of conditions and the following disclaimer in the 127598Sminkyu.jeong@arm.com// documentation and/or other materials provided with the distribution; 137598Sminkyu.jeong@arm.com// neither the name of the copyright holders nor the names of its 142326SN/A// contributors may be used to endorse or promote products derived from 151689SN/A// this software without specific prior written permission. 161689SN/A// 171689SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 281689SN/A// 291689SN/A// Authors: Korey Sewell 301689SN/A 311689SN/A//////////////////////////////////////////////////////////////////// 321689SN/A// 331689SN/A// MT instructions 341689SN/A// 351689SN/A 361689SN/Aoutput header {{ 371689SN/A /** 381689SN/A * Base class for MIPS MT ASE operations. 392665Ssaidi@eecs.umich.edu */ 402665Ssaidi@eecs.umich.edu class MTOp : public MipsStaticInst 411689SN/A { 421689SN/A protected: 431060SN/A 441060SN/A /// Constructor 451689SN/A MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 461060SN/A MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 471060SN/A { 481060SN/A } 498230Snate@binkert.org 506658Snate@binkert.org std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 512292SN/A 521717SN/A bool user_mode; 538229Snate@binkert.org }; 548232Snate@binkert.org 558232Snate@binkert.org class MTUserModeOp : public MTOp 568232Snate@binkert.org { 575529Snate@binkert.org protected: 581060SN/A 596221Snate@binkert.org /// Constructor 606221Snate@binkert.org MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 611681SN/A MTOp(mnem, _machInst, __opClass) 625529Snate@binkert.org { 632873Sktlim@umich.edu user_mode = true; 644329Sktlim@umich.edu } 654329Sktlim@umich.edu 664329Sktlim@umich.edu //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 672292SN/A }; 682292SN/A}}; 692292SN/A 702292SN/Aoutput decoder {{ 712820Sktlim@umich.edu std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 722292SN/A { 732820Sktlim@umich.edu std::stringstream ss; 742820Sktlim@umich.edu 755529Snate@binkert.org if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) { 762307SN/A ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 771060SN/A } else if (strcmp(mnemonic,"mftgpr") == 0) { 782292SN/A ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 792292SN/A } else { 802292SN/A ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 811060SN/A } 821060SN/A 831060SN/A return ss.str(); 841060SN/A } 851060SN/A}}; 861060SN/A 871681SN/Aoutput exec {{ 886221Snate@binkert.org void getThrRegExValues(%(CPU_exec_context)s *xc, unsigned &vpe_conf0, unsigned &tc_bind_mt, unsigned &tc_bind, unsigned &vpe_control, unsigned &mvp_conf0) 896221Snate@binkert.org { 906221Snate@binkert.org vpe_conf0 = xc->readMiscReg(VPEConf0); 916221Snate@binkert.org tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag); 922292SN/A tc_bind = xc->readMiscReg(TCBind); 932292SN/A vpe_control = xc->readMiscReg(VPEControl); 942820Sktlim@umich.edu mvp_conf0 = xc->readMiscReg(MVPConf0); 952820Sktlim@umich.edu } 962292SN/A 972292SN/A void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3) 982820Sktlim@umich.edu { 992820Sktlim@umich.edu config3 = xc->readMiscReg(Config3); 1002292SN/A } 1012292SN/A}}; 1022292SN/A 1032292SN/Adef template ThreadRegisterExecute {{ 1042292SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1052292SN/A { 1062292SN/A Fault fault = NoFault; 1072292SN/A int64_t data; 1081060SN/A %(op_decl)s; 1091060SN/A %(op_rd)s; 1101681SN/A 1111062SN/A unsigned vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0; 1122292SN/A 1131062SN/A getThrRegExValues(xc, vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0); 1142301SN/A 1152301SN/A if (isCoprocessorEnabled(xc, 0)) { 1161062SN/A if (bits(vpe_conf0, VPEC0_MVP) == 0 && 1172727Sktlim@umich.edu bits(tc_bind_mt, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) != 1181062SN/A bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) { 1191062SN/A data = -1; 1201062SN/A } else if (bits(vpe_control, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO) > 1211062SN/A bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO)) { 1221062SN/A data = -1; 1231062SN/A } else { 1241062SN/A int top_bit = 0; 1251062SN/A int bottom_bit = 0; 1261062SN/A 1271062SN/A if (MT_H == 1) { 1281062SN/A top_bit = 63; 1291062SN/A bottom_bit = 32; 1301062SN/A } else { 1311062SN/A top_bit = 31; 1321062SN/A bottom_bit = 0; 1331062SN/A } 1341062SN/A 1351062SN/A %(code)s; 1361062SN/A } 1371062SN/A } else { 1381062SN/A fault = new CoprocessorUnusableFault(0); 1391062SN/A } 1401062SN/A 1411062SN/A if(fault == NoFault) 1421062SN/A { 1431062SN/A %(op_wb)s; 1441062SN/A } 1451062SN/A 1461062SN/A return fault; 1471062SN/A } 1481062SN/A}}; 1491062SN/A 1501062SN/Adef template MTExecute{{ 1511062SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const 1521062SN/A { 1531062SN/A Fault fault = NoFault; 1541062SN/A %(op_decl)s; 1551062SN/A %(op_rd)s; 1561062SN/A 1571062SN/A unsigned config3; 1581062SN/A 1592292SN/A getMTExValues(xc, config3); 1602292SN/A 1612292SN/A if (isCoprocessorEnabled(xc, 0)) { 1622292SN/A if (bits(config3, CFG3_MT) == 1) { 1631062SN/A %(code)s; 1641062SN/A } else { 1651062SN/A fault = new ReservedInstructionFault(); 1661062SN/A } 1671062SN/A } else { 1681062SN/A fault = new CoprocessorUnusableFault(0); 1691062SN/A } 1702292SN/A 1712292SN/A if(fault == NoFault) 1722292SN/A { 1732292SN/A %(op_wb)s; 1742292SN/A } 1752292SN/A return fault; 1762292SN/A } 1772292SN/A}}; 1782292SN/A 1792292SN/A// Primary format for integer operate instructions: 1802301SN/Adef format MT_Control(code, *opt_flags) {{ 1812727Sktlim@umich.edu inst_flags = ('IsNonSpeculative', ) 1822353SN/A op_type = 'MTOp' 1832727Sktlim@umich.edu 1842727Sktlim@umich.edu for x in opt_flags: 1852727Sktlim@umich.edu if x == 'UserMode': 1866221Snate@binkert.org op_type = 'MTUserModeOp' 1872353SN/A else: 1882727Sktlim@umich.edu inst_flags += (x, ) 1892727Sktlim@umich.edu 1902727Sktlim@umich.edu iop = InstObjParams(name, Name, op_type, code, inst_flags) 1912727Sktlim@umich.edu header_output = BasicDeclare.subst(iop) 1922353SN/A decoder_output = BasicConstructor.subst(iop) 1932727Sktlim@umich.edu decode_block = BasicDecode.subst(iop) 1942727Sktlim@umich.edu exec_output = MTExecute.subst(iop) 1952727Sktlim@umich.edu}}; 1966221Snate@binkert.org 1978240Snate@binkert.orgdef format MT_MFTR(code, *flags) {{ 1982301SN/A flags += ('IsNonSpeculative', ) 1992727Sktlim@umich.edu# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2002301SN/A 2012727Sktlim@umich.edu code += 'if (MT_H == 1) {\n' 2026221Snate@binkert.org code += 'data = bits(data, top_bit, bottom_bit);\n' 2038240Snate@binkert.org code += '}\n' 2042301SN/A code += 'Rd = data;\n' 2052727Sktlim@umich.edu 2062301SN/A iop = InstObjParams(name, Name, 'MTOp', code, flags) 2072727Sktlim@umich.edu header_output = BasicDeclare.subst(iop) 2086221Snate@binkert.org decoder_output = BasicConstructor.subst(iop) 2098240Snate@binkert.org decode_block = BasicDecode.subst(iop) 2102301SN/A exec_output = ThreadRegisterExecute.subst(iop) 2112727Sktlim@umich.edu}}; 2122301SN/A 2132727Sktlim@umich.edudef format MT_MTTR(code, *flags) {{ 2146221Snate@binkert.org flags += ('IsNonSpeculative', ) 2158240Snate@binkert.org# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2162301SN/A iop = InstObjParams(name, Name, 'MTOp', code, flags) 2172727Sktlim@umich.edu header_output = BasicDeclare.subst(iop) 2182301SN/A decoder_output = BasicConstructor.subst(iop) 2192301SN/A decode_block = BasicDecode.subst(iop) 2208240Snate@binkert.org exec_output = ThreadRegisterExecute.subst(iop) 2212301SN/A}}; 2222727Sktlim@umich.edu