mt.isa revision 12104
11689SN/A// -*- mode:c++ -*- 29783Sandreas.hansson@arm.com 310239Sbinhpham@cs.rutgers.edu// Copyright (c) 2007 MIPS Technologies, Inc. 47598Sminkyu.jeong@arm.com// All rights reserved. 57598Sminkyu.jeong@arm.com// 67598Sminkyu.jeong@arm.com// Redistribution and use in source and binary forms, with or without 77598Sminkyu.jeong@arm.com// modification, are permitted provided that the following conditions are 87598Sminkyu.jeong@arm.com// met: redistributions of source code must retain the above copyright 97598Sminkyu.jeong@arm.com// notice, this list of conditions and the following disclaimer; 107598Sminkyu.jeong@arm.com// redistributions in binary form must reproduce the above copyright 117598Sminkyu.jeong@arm.com// notice, this list of conditions and the following disclaimer in the 127598Sminkyu.jeong@arm.com// documentation and/or other materials provided with the distribution; 137598Sminkyu.jeong@arm.com// neither the name of the copyright holders nor the names of its 147598Sminkyu.jeong@arm.com// contributors may be used to endorse or promote products derived from 152326SN/A// this software without specific prior written permission. 161689SN/A// 171689SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 281689SN/A// 291689SN/A// Authors: Korey Sewell 301689SN/A 311689SN/A//////////////////////////////////////////////////////////////////// 321689SN/A// 331689SN/A// MT instructions 341689SN/A// 351689SN/A 361689SN/Aoutput header {{ 371689SN/A /** 381689SN/A * Base class for MIPS MT ASE operations. 391689SN/A */ 402665Ssaidi@eecs.umich.edu class MTOp : public MipsStaticInst 412665Ssaidi@eecs.umich.edu { 421689SN/A protected: 431689SN/A 449944Smatt.horsnell@ARM.com /// Constructor 459944Smatt.horsnell@ARM.com MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 469944Smatt.horsnell@ARM.com MipsStaticInst(mnem, _machInst, __opClass), user_mode(false) 471060SN/A { 481060SN/A } 491689SN/A 501060SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 511060SN/A 521060SN/A bool user_mode; 538230Snate@binkert.org }; 546658Snate@binkert.org 558887Sgeoffrey.blake@arm.com class MTUserModeOp : public MTOp 562292SN/A { 571717SN/A protected: 588229Snate@binkert.org 598232Snate@binkert.org /// Constructor 609444SAndreas.Sandberg@ARM.com MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 618232Snate@binkert.org MTOp(mnem, _machInst, __opClass) 629527SMatt.Horsnell@arm.com { 635529Snate@binkert.org user_mode = true; 641060SN/A } 656221Snate@binkert.org 666221Snate@binkert.org //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 671681SN/A }; 685529Snate@binkert.org}}; 692873Sktlim@umich.edu 704329Sktlim@umich.eduoutput decoder {{ 714329Sktlim@umich.edu std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 724329Sktlim@umich.edu { 732292SN/A std::stringstream ss; 742292SN/A 752292SN/A if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) { 762292SN/A ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL); 772820Sktlim@umich.edu } else if (strcmp(mnemonic,"mftgpr") == 0) { 782292SN/A ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT); 792820Sktlim@umich.edu } else { 809444SAndreas.Sandberg@ARM.com ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD); 811060SN/A } 8210172Sdam.sunwoo@arm.com 8310172Sdam.sunwoo@arm.com return ss.str(); 8410172Sdam.sunwoo@arm.com } 8510172Sdam.sunwoo@arm.com}}; 8610172Sdam.sunwoo@arm.com 8710172Sdam.sunwoo@arm.comoutput header {{ 8810172Sdam.sunwoo@arm.com void getThrRegExValues(%(CPU_exec_context)s *xc, 8910172Sdam.sunwoo@arm.com MipsISA::VPEConf0Reg &vpe_conf0, 9010172Sdam.sunwoo@arm.com MipsISA::TCBindReg &tc_bind_mt, 9110172Sdam.sunwoo@arm.com MipsISA::TCBindReg &tc_bind, 9210172Sdam.sunwoo@arm.com MipsISA::VPEControlReg &vpe_control, 9310172Sdam.sunwoo@arm.com MipsISA::MVPConf0Reg &mvp_conf0); 9410172Sdam.sunwoo@arm.com 952292SN/A void getMTExValues(%(CPU_exec_context)s *xc, MipsISA::Config3Reg &config3); 962292SN/A}}; 972292SN/A 981060SN/Aoutput exec {{ 991060SN/A void getThrRegExValues(CPU_EXEC_CONTEXT *xc, 1001060SN/A VPEConf0Reg &vpe_conf0, TCBindReg &tc_bind_mt, 1011060SN/A TCBindReg &tc_bind, VPEControlReg &vpe_control, 1021060SN/A MVPConf0Reg &mvp_conf0) 1031060SN/A { 1041681SN/A vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); 1056221Snate@binkert.org tc_bind_mt = xc->readRegOtherThread(RegId(MiscRegClass, 1066221Snate@binkert.org MISCREG_TC_BIND)); 1076221Snate@binkert.org tc_bind = xc->readMiscReg(MISCREG_TC_BIND); 1082292SN/A vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); 1092292SN/A mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); 1102292SN/A } 1112292SN/A 11210328Smitch.hayenga@arm.com void getMTExValues(CPU_EXEC_CONTEXT *xc, Config3Reg &config3) 1132292SN/A { 1142292SN/A config3 = xc->readMiscReg(MISCREG_CONFIG3); 1152292SN/A } 1162292SN/A}}; 1172292SN/A 1182292SN/Adef template ThreadRegisterExecute {{ 1192292SN/A Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 1201060SN/A { 1211060SN/A Fault fault = NoFault; 1221681SN/A int64_t data M5_VAR_USED; 1231062SN/A %(op_decl)s; 12410023Smatt.horsnell@ARM.com %(op_rd)s; 12510023Smatt.horsnell@ARM.com 12610023Smatt.horsnell@ARM.com VPEConf0Reg vpeConf0; 12710023Smatt.horsnell@ARM.com TCBindReg tcBindMT; 12810023Smatt.horsnell@ARM.com TCBindReg tcBind; 12910023Smatt.horsnell@ARM.com VPEControlReg vpeControl; 13010023Smatt.horsnell@ARM.com MVPConf0Reg mvpConf0; 13110023Smatt.horsnell@ARM.com 1322292SN/A getThrRegExValues(xc, vpeConf0, tcBindMT, 1331062SN/A tcBind, vpeControl, mvpConf0); 1342301SN/A 1352301SN/A if (isCoprocessorEnabled(xc, 0)) { 1361062SN/A if (vpeConf0.mvp == 0 && tcBindMT.curVPE != tcBind.curVPE) { 1372727Sktlim@umich.edu data = -1; 1381062SN/A } else if (vpeControl.targTC > mvpConf0.ptc) { 1391062SN/A data = -1; 1401062SN/A } else { 1411062SN/A %(code)s; 1421062SN/A } 1431062SN/A } else { 1441062SN/A fault = std::make_shared<CoprocessorUnusableFault>(0); 1451062SN/A } 1461062SN/A 1471062SN/A if(fault == NoFault) 1481062SN/A { 1491062SN/A %(op_wb)s; 1501062SN/A } 1511062SN/A 1521062SN/A return fault; 1531062SN/A } 1541062SN/A}}; 1551062SN/A 1561062SN/Adef template MTExecute{{ 1571062SN/A Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 1581062SN/A { 1591062SN/A Fault fault = NoFault; 1601062SN/A %(op_decl)s; 1611062SN/A %(op_rd)s; 1621062SN/A 1631062SN/A Config3Reg config3; 1641062SN/A 1651062SN/A getMTExValues(xc, config3); 1661062SN/A 1671062SN/A if (isCoprocessorEnabled(xc, 0)) { 1681062SN/A if (config3.mt == 1) { 1691062SN/A %(code)s; 1701062SN/A } else { 1711062SN/A fault = std::make_shared<ReservedInstructionFault>(); 1721062SN/A } 1731062SN/A } else { 1741062SN/A fault = std::make_shared<CoprocessorUnusableFault>(0); 1751062SN/A } 1761062SN/A 1771062SN/A if(fault == NoFault) 1781062SN/A { 1792292SN/A %(op_wb)s; 1802292SN/A } 1812292SN/A return fault; 1822292SN/A } 1831062SN/A}}; 1841062SN/A 1851062SN/A// Primary format for integer operate instructions: 1861062SN/Adef format MT_Control(code, *opt_flags) {{ 1871062SN/A inst_flags = ('IsNonSpeculative', ) 1881062SN/A op_type = 'MTOp' 1891062SN/A 1902292SN/A for x in opt_flags: 1912292SN/A if x == 'UserMode': 1922292SN/A op_type = 'MTUserModeOp' 1932292SN/A else: 1942292SN/A inst_flags += (x, ) 1952292SN/A 1962292SN/A iop = InstObjParams(name, Name, op_type, code, inst_flags) 1972292SN/A header_output = BasicDeclare.subst(iop) 1982292SN/A decoder_output = BasicConstructor.subst(iop) 1992292SN/A decode_block = BasicDecode.subst(iop) 2002301SN/A exec_output = MTExecute.subst(iop) 2012727Sktlim@umich.edu}}; 2022353SN/A 2032727Sktlim@umich.edudef format MT_MFTR(code, *flags) {{ 2042727Sktlim@umich.edu flags += ('IsNonSpeculative', ) 2052727Sktlim@umich.edu# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2066221Snate@binkert.org 2072353SN/A code += ''' 2082727Sktlim@umich.edu if (MT_H) 2092727Sktlim@umich.edu data = bits(data, 63, 32); 2102727Sktlim@umich.edu Rd = data; 2112727Sktlim@umich.edu ''' 2122353SN/A 2132727Sktlim@umich.edu iop = InstObjParams(name, Name, 'MTOp', code, flags) 2142727Sktlim@umich.edu header_output = BasicDeclare.subst(iop) 2152727Sktlim@umich.edu decoder_output = BasicConstructor.subst(iop) 2166221Snate@binkert.org decode_block = BasicDecode.subst(iop) 2178240Snate@binkert.org exec_output = ThreadRegisterExecute.subst(iop) 2182301SN/A}}; 2192727Sktlim@umich.edu 2202301SN/Adef format MT_MTTR(code, *flags) {{ 2212727Sktlim@umich.edu flags += ('IsNonSpeculative', ) 2226221Snate@binkert.org# code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code 2238240Snate@binkert.org iop = InstObjParams(name, Name, 'MTOp', code, flags) 2242301SN/A header_output = BasicDeclare.subst(iop) 2252727Sktlim@umich.edu decoder_output = BasicConstructor.subst(iop) 2262301SN/A decode_block = BasicDecode.subst(iop) 2272727Sktlim@umich.edu exec_output = ThreadRegisterExecute.subst(iop) 2286221Snate@binkert.org}}; 2298240Snate@binkert.org