mem.isa revision 8442:b1f3dfae06f1
12SN/A// -*- mode:c++ -*- 29448SAndreas.Sandberg@ARM.com 37338SAli.Saidi@ARM.com// Copyright (c) 2007 MIPS Technologies, Inc. 47338SAli.Saidi@ARM.com// All rights reserved. 57338SAli.Saidi@ARM.com// 67338SAli.Saidi@ARM.com// Redistribution and use in source and binary forms, with or without 77338SAli.Saidi@ARM.com// modification, are permitted provided that the following conditions are 87338SAli.Saidi@ARM.com// met: redistributions of source code must retain the above copyright 97338SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer; 107338SAli.Saidi@ARM.com// redistributions in binary form must reproduce the above copyright 117338SAli.Saidi@ARM.com// notice, this list of conditions and the following disclaimer in the 127338SAli.Saidi@ARM.com// documentation and/or other materials provided with the distribution; 137338SAli.Saidi@ARM.com// neither the name of the copyright holders nor the names of its 141762SN/A// contributors may be used to endorse or promote products derived from 152SN/A// this software without specific prior written permission. 162SN/A// 172SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282SN/A// 292SN/A// Authors: Steve Reinhardt 302SN/A// Korey Sewell 312SN/A 322SN/A//////////////////////////////////////////////////////////////////// 332SN/A// 342SN/A// Memory-format instructions 352SN/A// 362SN/A 372SN/Aoutput header {{ 382SN/A /** 392665Ssaidi@eecs.umich.edu * Base class for general Mips memory-format instructions. 402665Ssaidi@eecs.umich.edu */ 412SN/A class Memory : public MipsStaticInst 422SN/A { 438779Sgblack@eecs.umich.edu protected: 448779Sgblack@eecs.umich.edu /// Memory request flags. See mem_req_base.hh. 458779Sgblack@eecs.umich.edu Request::Flags memAccessFlags; 462439SN/A 478779Sgblack@eecs.umich.edu /// Displacement for EA calculation (signed). 488229Snate@binkert.org int32_t disp; 496216Snate@binkert.org 50146SN/A /// Constructor 51146SN/A Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 52146SN/A : MipsStaticInst(mnem, _machInst, __opClass), 53146SN/A disp(sext<16>(OFFSET)) 54146SN/A { 556216Snate@binkert.org } 566658Snate@binkert.org 578229Snate@binkert.org std::string 581717SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 598887Sgeoffrey.blake@arm.com }; 608887Sgeoffrey.blake@arm.com 61146SN/A /** 621977SN/A * Base class for a few miscellaneous memory-format insts 632683Sktlim@umich.edu * that don't interpret the disp field 641717SN/A */ 65146SN/A class MemoryNoDisp : public Memory 662683Sktlim@umich.edu { 678232Snate@binkert.org protected: 688232Snate@binkert.org /// Constructor 698232Snate@binkert.org MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 708779Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass) 713348Sbinkertn@umich.edu { 726105Ssteve.reinhardt@amd.com } 736216Snate@binkert.org 742036SN/A std::string 75146SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 768817Sgblack@eecs.umich.edu }; 778793Sgblack@eecs.umich.edu}}; 7856SN/A 7956SN/A 80695SN/Aoutput decoder {{ 812901Ssaidi@eecs.umich.edu std::string 822SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 832SN/A { 842449SN/A return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 851355SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 865529Snate@binkert.org } 879023Sgblack@eecs.umich.edu 88224SN/A std::string 898793Sgblack@eecs.umich.edu MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 909384SAndreas.Sandberg@arm.com { 919384SAndreas.Sandberg@arm.com return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 928793Sgblack@eecs.umich.edu flags[IsFloating] ? 'f' : 'r', 938820Sgblack@eecs.umich.edu flags[IsFloating] ? FD : RD, 949384SAndreas.Sandberg@arm.com RS, RT); 952SN/A } 966029Ssteve.reinhardt@amd.com 972672Sktlim@umich.edu}}; 982683Sktlim@umich.edu 992SN/Aoutput exec {{ 1008733Sgeoffrey.blake@arm.com /** return data in cases where there the size of data is only 1018733Sgeoffrey.blake@arm.com known in the packet 1028733Sgeoffrey.blake@arm.com */ 1038733Sgeoffrey.blake@arm.com uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) { 1048733Sgeoffrey.blake@arm.com switch (packet->getSize()) 1058733Sgeoffrey.blake@arm.com { 1068733Sgeoffrey.blake@arm.com case 1: 1078733Sgeoffrey.blake@arm.com return packet->get<uint8_t>(); 1088733Sgeoffrey.blake@arm.com 1098733Sgeoffrey.blake@arm.com case 2: 1108733Sgeoffrey.blake@arm.com return packet->get<uint16_t>(); 1112SN/A 112334SN/A case 4: 1138834Satgutier@umich.edu return packet->get<uint32_t>(); 1148834Satgutier@umich.edu 115140SN/A case 8: 116334SN/A return packet->get<uint64_t>(); 1172SN/A 1182SN/A default: 1192SN/A std::cerr << "bad store data size = " << packet->getSize() << std::endl; 1202680Sktlim@umich.edu 1214377Sgblack@eecs.umich.edu assert(0); 1225169Ssaidi@eecs.umich.edu return 0; 1234377Sgblack@eecs.umich.edu } 1244377Sgblack@eecs.umich.edu } 1252SN/A 1262SN/A 1272623SN/A}}; 1282SN/A 1292SN/Adef template LoadStoreDeclare {{ 1302SN/A /** 131180SN/A * Static instruction class for "%(mnemonic)s". 1328737Skoansin.tan@gmail.com */ 133393SN/A class %(class_name)s : public %(base_class)s 134393SN/A { 135393SN/A public: 136393SN/A 137384SN/A /// Constructor. 138384SN/A %(class_name)s(ExtMachInst machInst); 139393SN/A 1408737Skoansin.tan@gmail.com %(BasicExecDeclare)s 141393SN/A 142393SN/A %(EACompDeclare)s 143393SN/A 144393SN/A %(InitiateAccDeclare)s 145384SN/A 146189SN/A %(CompleteAccDeclare)s 147189SN/A }; 1482623SN/A}}; 1492SN/A 150729SN/Adef template EACompDeclare {{ 151334SN/A Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1522SN/A}}; 1532SN/A 1542SN/Adef template InitiateAccDeclare {{ 1558834Satgutier@umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1568834Satgutier@umich.edu}}; 1578834Satgutier@umich.edu 1588834Satgutier@umich.edu 1598834Satgutier@umich.edudef template CompleteAccDeclare {{ 1608834Satgutier@umich.edu Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1618834Satgutier@umich.edu}}; 1622SN/A 1632SN/Adef template LoadStoreConstructor {{ 1647897Shestness@cs.utexas.edu inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1657897Shestness@cs.utexas.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1667897Shestness@cs.utexas.edu { 1677897Shestness@cs.utexas.edu %(constructor)s; 1687897Shestness@cs.utexas.edu } 1697897Shestness@cs.utexas.edu}}; 1707897Shestness@cs.utexas.edu 1717897Shestness@cs.utexas.edu 1727897Shestness@cs.utexas.edudef template EACompExecute {{ 1737897Shestness@cs.utexas.edu Fault 1747897Shestness@cs.utexas.edu %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 1757897Shestness@cs.utexas.edu Trace::InstRecord *traceData) const 1767897Shestness@cs.utexas.edu { 1777897Shestness@cs.utexas.edu Addr EA; 1787897Shestness@cs.utexas.edu Fault fault = NoFault; 1797897Shestness@cs.utexas.edu 1807897Shestness@cs.utexas.edu if (this->isFloating()) { 1817897Shestness@cs.utexas.edu %(fp_enable_check)s; 1827897Shestness@cs.utexas.edu 1837897Shestness@cs.utexas.edu if(fault != NoFault) 1847897Shestness@cs.utexas.edu return fault; 1857897Shestness@cs.utexas.edu } 1867897Shestness@cs.utexas.edu 1877897Shestness@cs.utexas.edu %(op_decl)s; 1887897Shestness@cs.utexas.edu %(op_rd)s; 1897897Shestness@cs.utexas.edu %(ea_code)s; 1907897Shestness@cs.utexas.edu 1917897Shestness@cs.utexas.edu // NOTE: Trace Data is written using execute or completeAcc templates 1927897Shestness@cs.utexas.edu if (fault == NoFault) { 1937897Shestness@cs.utexas.edu xc->setEA(EA); 1947897Shestness@cs.utexas.edu } 1957897Shestness@cs.utexas.edu 1967897Shestness@cs.utexas.edu return fault; 1977897Shestness@cs.utexas.edu } 1987897Shestness@cs.utexas.edu}}; 1997897Shestness@cs.utexas.edu 2007897Shestness@cs.utexas.edudef template LoadExecute {{ 2017897Shestness@cs.utexas.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2027897Shestness@cs.utexas.edu Trace::InstRecord *traceData) const 2037897Shestness@cs.utexas.edu { 2047897Shestness@cs.utexas.edu Addr EA; 2057897Shestness@cs.utexas.edu Fault fault = NoFault; 2067897Shestness@cs.utexas.edu 2077897Shestness@cs.utexas.edu if (this->isFloating()) { 2087897Shestness@cs.utexas.edu %(fp_enable_check)s; 2097897Shestness@cs.utexas.edu 2107897Shestness@cs.utexas.edu if(fault != NoFault) 2117897Shestness@cs.utexas.edu return fault; 2127897Shestness@cs.utexas.edu } 2137897Shestness@cs.utexas.edu 2142SN/A %(op_decl)s; 2157897Shestness@cs.utexas.edu %(op_rd)s; 2167897Shestness@cs.utexas.edu %(ea_code)s; 2177897Shestness@cs.utexas.edu 2187897Shestness@cs.utexas.edu if (fault == NoFault) { 2197897Shestness@cs.utexas.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 2207897Shestness@cs.utexas.edu %(memacc_code)s; 2217897Shestness@cs.utexas.edu } 2227897Shestness@cs.utexas.edu 2237897Shestness@cs.utexas.edu if (fault == NoFault) { 2247897Shestness@cs.utexas.edu %(op_wb)s; 2257897Shestness@cs.utexas.edu } 2267897Shestness@cs.utexas.edu 2272SN/A return fault; 2282SN/A } 2291001SN/A}}; 2301001SN/A 2311001SN/A 2321001SN/Adef template LoadInitiateAcc {{ 2331001SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2342SN/A Trace::InstRecord *traceData) const 2352SN/A { 2362SN/A Addr EA; 2372SN/A Fault fault = NoFault; 2382SN/A 2397897Shestness@cs.utexas.edu if (this->isFloating()) { 2407897Shestness@cs.utexas.edu %(fp_enable_check)s; 2417897Shestness@cs.utexas.edu 2427897Shestness@cs.utexas.edu if(fault != NoFault) 2437897Shestness@cs.utexas.edu return fault; 2447897Shestness@cs.utexas.edu } 2457897Shestness@cs.utexas.edu 2467897Shestness@cs.utexas.edu %(op_src_decl)s; 2477897Shestness@cs.utexas.edu %(op_rd)s; 2487897Shestness@cs.utexas.edu %(ea_code)s; 2492SN/A 2502SN/A if (fault == NoFault) { 2512SN/A fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags); 2522SN/A } 2532SN/A 2542SN/A return fault; 2552SN/A } 2562SN/A}}; 2572SN/A 2582SN/Adef template LoadCompleteAcc {{ 2592SN/A Fault %(class_name)s::completeAcc(Packet *pkt, 2602SN/A %(CPU_exec_context)s *xc, 2612390SN/A Trace::InstRecord *traceData) const 2622390SN/A { 2632390SN/A Fault fault = NoFault; 2642390SN/A 2652390SN/A if (this->isFloating()) { 2662390SN/A %(fp_enable_check)s; 2672390SN/A 2682390SN/A if(fault != NoFault) 2692390SN/A return fault; 2702390SN/A } 2712390SN/A 2722390SN/A %(op_decl)s; 273385SN/A %(op_rd)s; 2747897Shestness@cs.utexas.edu 2757897Shestness@cs.utexas.edu getMem(pkt, Mem, traceData); 2762SN/A 2772SN/A if (fault == NoFault) { 2782SN/A %(memacc_code)s; 2792623SN/A } 280334SN/A 2812361SN/A if (fault == NoFault) { 2825496Ssaidi@eecs.umich.edu %(op_wb)s; 283334SN/A } 284334SN/A 285334SN/A return fault; 2869448SAndreas.Sandberg@ARM.com } 2872SN/A}}; 2889448SAndreas.Sandberg@ARM.com 2899448SAndreas.Sandberg@ARM.comdef template StoreExecute {{ 2909448SAndreas.Sandberg@ARM.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2912683Sktlim@umich.edu Trace::InstRecord *traceData) const 2922SN/A { 2932SN/A Addr EA; 2942SN/A Fault fault = NoFault; 2959448SAndreas.Sandberg@ARM.com 2969448SAndreas.Sandberg@ARM.com %(fp_enable_check)s; 2972SN/A %(op_decl)s; 2989448SAndreas.Sandberg@ARM.com %(op_rd)s; 2999448SAndreas.Sandberg@ARM.com %(ea_code)s; 3009448SAndreas.Sandberg@ARM.com 3012SN/A if (fault == NoFault) { 3022SN/A %(memacc_code)s; 3032SN/A } 3046221Snate@binkert.org 3052SN/A if (fault == NoFault) { 3062SN/A fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3072SN/A NULL); 3082SN/A } 3092623SN/A 3102SN/A if (fault == NoFault) { 3112680Sktlim@umich.edu %(postacc_code)s; 3122SN/A } 3132SN/A 3142SN/A if (fault == NoFault) { 3155807Snate@binkert.org %(op_wb)s; 3162SN/A } 3175807Snate@binkert.org 3185807Snate@binkert.org return fault; 3192SN/A } 3205807Snate@binkert.org}}; 3215807Snate@binkert.org 3222SN/A 3232SN/Adef template StoreFPExecute {{ 3242SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3252623SN/A Trace::InstRecord *traceData) const 3262SN/A { 3275704Snate@binkert.org Addr EA; 3285647Sgblack@eecs.umich.edu Fault fault = NoFault; 3292SN/A 3303520Sgblack@eecs.umich.edu %(fp_enable_check)s; 3317338SAli.Saidi@ARM.com if(fault != NoFault) 3325647Sgblack@eecs.umich.edu return fault; 3333520Sgblack@eecs.umich.edu %(op_decl)s; 3349023Sgblack@eecs.umich.edu %(op_rd)s; 3352SN/A %(ea_code)s; 3362SN/A 3372623SN/A if (fault == NoFault) { 3382SN/A %(memacc_code)s; 3392623SN/A } 3405894Sgblack@eecs.umich.edu 3412662Sstever@eecs.umich.edu if (fault == NoFault) { 3422623SN/A fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3437720Sgblack@eecs.umich.edu NULL); 3444495Sacolyte@umich.edu } 3452623SN/A 3467720Sgblack@eecs.umich.edu if (fault == NoFault) { 3472623SN/A %(postacc_code)s; 3487720Sgblack@eecs.umich.edu } 3498832SAli.Saidi@ARM.com 3508832SAli.Saidi@ARM.com if (fault == NoFault) { 3512623SN/A %(op_wb)s; 3522623SN/A } 3532623SN/A 3542623SN/A return fault; 3552623SN/A } 3562623SN/A}}; 3572SN/A 3582683Sktlim@umich.edudef template StoreCondExecute {{ 3592427SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3602683Sktlim@umich.edu Trace::InstRecord *traceData) const 3612427SN/A { 3622SN/A Addr EA; 3632623SN/A Fault fault = NoFault; 3642623SN/A uint64_t write_result = 0; 3657897Shestness@cs.utexas.edu 3662SN/A %(fp_enable_check)s; 3672623SN/A %(op_decl)s; 3682623SN/A %(op_rd)s; 3694377Sgblack@eecs.umich.edu %(ea_code)s; 3707720Sgblack@eecs.umich.edu 3714377Sgblack@eecs.umich.edu if (fault == NoFault) { 3727720Sgblack@eecs.umich.edu %(memacc_code)s; 3735665Sgblack@eecs.umich.edu } 3747720Sgblack@eecs.umich.edu 3757720Sgblack@eecs.umich.edu if (fault == NoFault) { 3765665Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3775665Sgblack@eecs.umich.edu &write_result); 3784181Sgblack@eecs.umich.edu } 3794181Sgblack@eecs.umich.edu 3809023Sgblack@eecs.umich.edu if (fault == NoFault) { 3819023Sgblack@eecs.umich.edu %(postacc_code)s; 3824181Sgblack@eecs.umich.edu } 3834182Sgblack@eecs.umich.edu 3847720Sgblack@eecs.umich.edu if (fault == NoFault) { 3859023Sgblack@eecs.umich.edu %(op_wb)s; 3869023Sgblack@eecs.umich.edu } 3874593Sgblack@eecs.umich.edu 3889023Sgblack@eecs.umich.edu return fault; 3894377Sgblack@eecs.umich.edu } 3909023Sgblack@eecs.umich.edu}}; 3914377Sgblack@eecs.umich.edu 3929023Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 3939023Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3944377Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3957720Sgblack@eecs.umich.edu { 3964377Sgblack@eecs.umich.edu Addr EA; 3974377Sgblack@eecs.umich.edu Fault fault = NoFault; 3984377Sgblack@eecs.umich.edu 3994377Sgblack@eecs.umich.edu %(fp_enable_check)s; 4004181Sgblack@eecs.umich.edu %(op_decl)s; 4014181Sgblack@eecs.umich.edu %(op_rd)s; 4024181Sgblack@eecs.umich.edu %(ea_code)s; 4034539Sgblack@eecs.umich.edu 4043276Sgblack@eecs.umich.edu if (fault == NoFault) { 4057720Sgblack@eecs.umich.edu %(memacc_code)s; 4063280Sgblack@eecs.umich.edu } 4073280Sgblack@eecs.umich.edu 4083276Sgblack@eecs.umich.edu if (fault == NoFault) { 4093276Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 4103276Sgblack@eecs.umich.edu NULL); 4117720Sgblack@eecs.umich.edu } 4123276Sgblack@eecs.umich.edu 4133276Sgblack@eecs.umich.edu return fault; 4144181Sgblack@eecs.umich.edu } 4158955Sgblack@eecs.umich.edu}}; 4164522Ssaidi@eecs.umich.edu 4177823Ssteve.reinhardt@amd.com 4187720Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 4192470SN/A Fault %(class_name)s::completeAcc(Packet *pkt, 4208955Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 4214181Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4224522Ssaidi@eecs.umich.edu { 4234181Sgblack@eecs.umich.edu return NoFault; 4242623SN/A } 4252623SN/A}}; 4262623SN/A 4272623SN/Adef template StoreCondCompleteAcc {{ 4282623SN/A Fault %(class_name)s::completeAcc(Packet *pkt, 4297720Sgblack@eecs.umich.edu %(CPU_exec_context)s *xc, 4307720Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4317720Sgblack@eecs.umich.edu { 4327720Sgblack@eecs.umich.edu Fault fault = NoFault; 4338780Sgblack@eecs.umich.edu 4343577Sgblack@eecs.umich.edu %(fp_enable_check)s; 4357720Sgblack@eecs.umich.edu %(op_dest_decl)s; 4365086Sgblack@eecs.umich.edu 4372623SN/A uint64_t write_result = pkt->req->getExtraData(); 4382683Sktlim@umich.edu 4392623SN/A if (fault == NoFault) { 4402SN/A %(postacc_code)s; 4412623SN/A } 4422623SN/A 4432SN/A if (fault == NoFault) { 4442SN/A %(op_wb)s; 4452623SN/A } 4462623SN/A 4472623SN/A return fault; 4482623SN/A } 4492SN/A}}; 4505953Ssaidi@eecs.umich.edu 4517720Sgblack@eecs.umich.edudef template MiscExecute {{ 4525953Ssaidi@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 4535953Ssaidi@eecs.umich.edu Trace::InstRecord *traceData) const 4547897Shestness@cs.utexas.edu { 4557897Shestness@cs.utexas.edu Addr EA M5_VAR_USED = 0; 4567897Shestness@cs.utexas.edu Fault fault = NoFault; 4577897Shestness@cs.utexas.edu 4587897Shestness@cs.utexas.edu %(fp_enable_check)s; 4597897Shestness@cs.utexas.edu %(op_decl)s; 4607897Shestness@cs.utexas.edu %(op_rd)s; 4617897Shestness@cs.utexas.edu %(ea_code)s; 4627897Shestness@cs.utexas.edu 4637897Shestness@cs.utexas.edu if (fault == NoFault) { 4647897Shestness@cs.utexas.edu %(memacc_code)s; 4657897Shestness@cs.utexas.edu } 4667897Shestness@cs.utexas.edu 4677897Shestness@cs.utexas.edu return NoFault; 4687897Shestness@cs.utexas.edu } 4697897Shestness@cs.utexas.edu}}; 4707897Shestness@cs.utexas.edu 4717897Shestness@cs.utexas.edudef template MiscInitiateAcc {{ 4727897Shestness@cs.utexas.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4737897Shestness@cs.utexas.edu Trace::InstRecord *traceData) const 4747897Shestness@cs.utexas.edu { 4757897Shestness@cs.utexas.edu panic("Misc instruction does not support split access method!"); 4767897Shestness@cs.utexas.edu return NoFault; 4777897Shestness@cs.utexas.edu } 4787897Shestness@cs.utexas.edu}}; 4797897Shestness@cs.utexas.edu 4807897Shestness@cs.utexas.edu 4817897Shestness@cs.utexas.edudef template MiscCompleteAcc {{ 4827897Shestness@cs.utexas.edu Fault %(class_name)s::completeAcc(Packet *pkt, 4837897Shestness@cs.utexas.edu %(CPU_exec_context)s *xc, 4847897Shestness@cs.utexas.edu Trace::InstRecord *traceData) const 4857897Shestness@cs.utexas.edu { 4867897Shestness@cs.utexas.edu panic("Misc instruction does not support split access method!"); 4878780Sgblack@eecs.umich.edu 4888780Sgblack@eecs.umich.edu return NoFault; 4892644Sstever@eecs.umich.edu } 4902644Sstever@eecs.umich.edu}}; 4914046Sbinkertn@umich.edu 4924046Sbinkertn@umich.edudef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4934046Sbinkertn@umich.edu mem_flags = [], inst_flags = []) {{ 4942644Sstever@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 4952623SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4962SN/A decode_template = ImmNopCheckDecode, 4972SN/A exec_template_base = 'Load') 4982623SN/A}}; 4992623SN/A 5002623SN/A 5014377Sgblack@eecs.umich.edudef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 5024377Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 5032090SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5043905Ssaidi@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5057678Sgblack@eecs.umich.edu exec_template_base = 'Store') 5069023Sgblack@eecs.umich.edu}}; 5074377Sgblack@eecs.umich.edu 5087720Sgblack@eecs.umich.edudef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5097720Sgblack@eecs.umich.edu mem_flags = [], inst_flags = []) {{ 5107720Sgblack@eecs.umich.edu inst_flags += ['IsIndexed'] 5117720Sgblack@eecs.umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5127720Sgblack@eecs.umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5137720Sgblack@eecs.umich.edu decode_template = ImmNopCheckDecode, 5143276Sgblack@eecs.umich.edu exec_template_base = 'Load') 5152SN/A}}; 5162SN/A 5172SN/Adef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5185250Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5195222Sksewell@umich.edu inst_flags += ['IsIndexed'] 5205222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5215222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5225222Sksewell@umich.edu exec_template_base = 'Store') 5235222Sksewell@umich.edu}}; 5245222Sksewell@umich.edu 5255222Sksewell@umich.edudef format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5265222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5275222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 5285222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5295222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5305222Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5315222Sksewell@umich.edu exec_template_base = 'Load') 5325222Sksewell@umich.edu}}; 5335222Sksewell@umich.edu 5345222Sksewell@umich.edudef format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5355222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5365222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 5375222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5385222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5395222Sksewell@umich.edu exec_template_base = 'Store') 5405222Sksewell@umich.edu}}; 5415222Sksewell@umich.edu 5425222Sksewell@umich.edu 5435222Sksewell@umich.edudef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5445222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5455222Sksewell@umich.edu decl_code = 'uint32_t mem_word = Mem.uw;\n' 5465222Sksewell@umich.edu decl_code += 'uint32_t unalign_addr = Rs + disp;\n' 5475222Sksewell@umich.edu decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n' 5485222Sksewell@umich.edu decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 5495222Sksewell@umich.edu decl_code += '\tbyte_offset ^= 3;\n' 5505222Sksewell@umich.edu decl_code += '#endif\n' 5515250Sksewell@umich.edu 552 memacc_code = decl_code + memacc_code 553 554 (header_output, decoder_output, decode_block, exec_output) = \ 555 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 556 decode_template = ImmNopCheckDecode, 557 exec_template_base = 'Load') 558}}; 559 560def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 561 mem_flags = [], inst_flags = []) {{ 562 decl_code = ''' 563 uint32_t mem_word = 0; 564 uint32_t unaligned_addr = Rs + disp; 565 uint32_t byte_offset = unaligned_addr & 3; 566 #if BYTE_ORDER == BIG_ENDIAN 567 byte_offset ^= 3; 568 #endif 569 fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags); 570 ''' 571 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 572 573 (header_output, decoder_output, decode_block, exec_output) = \ 574 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 575 exec_template_base = 'Store') 576}}; 577 578def format Prefetch(ea_code = {{ EA = Rs + disp; }}, 579 mem_flags = [], pf_flags = [], inst_flags = []) {{ 580 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 581 pf_inst_flags = inst_flags 582 583 (header_output, decoder_output, decode_block, exec_output) = \ 584 LoadStoreBase(name, Name, ea_code, 585 'warn_once("Prefetching not implemented for MIPS\\n");', 586 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 587 588}}; 589 590def format StoreCond(memacc_code, postacc_code, 591 ea_code = {{ EA = Rs + disp; }}, 592 mem_flags = [], inst_flags = []) {{ 593 (header_output, decoder_output, decode_block, exec_output) = \ 594 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 595 postacc_code, exec_template_base = 'StoreCond') 596}}; 597