mem.isa revision 10196 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 MIPS Technologies, Inc.
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Steve Reinhardt
30//          Korey Sewell
31
32////////////////////////////////////////////////////////////////////
33//
34// Memory-format instructions
35//
36
37output header {{
38    /**
39     * Base class for general Mips memory-format instructions.
40     */
41    class Memory : public MipsStaticInst
42    {
43      protected:
44        /// Memory request flags.  See mem_req_base.hh.
45        Request::Flags memAccessFlags;
46
47        /// Displacement for EA calculation (signed).
48        int32_t disp;
49
50        /// Constructor
51        Memory(const char *mnem, MachInst _machInst, OpClass __opClass)
52            : MipsStaticInst(mnem, _machInst, __opClass),
53              disp(sext<16>(OFFSET))
54        {
55        }
56
57        std::string
58        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
59    };
60
61     /**
62     * Base class for a few miscellaneous memory-format insts
63     * that don't interpret the disp field
64     */
65    class MemoryNoDisp : public Memory
66    {
67      protected:
68        /// Constructor
69        MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
70            : Memory(mnem, _machInst, __opClass)
71        {
72        }
73
74        std::string
75        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
76    };
77}};
78
79
80output decoder {{
81    std::string
82    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
83    {
84        return csprintf("%-10s %c%d, %d(r%d)", mnemonic,
85                        flags[IsFloating] ? 'f' : 'r', RT, disp, RS);
86    }
87
88    std::string
89    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
90    {
91        return csprintf("%-10s %c%d, r%d(r%d)", mnemonic,
92                        flags[IsFloating] ? 'f' : 'r',
93                        flags[IsFloating] ? FD : RD,
94                        RS, RT);
95    }
96
97}};
98
99output header {{
100    uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet);
101
102}};
103
104output exec {{
105    /** return data in cases where there the size of data is only
106        known in the packet
107    */
108    uint64_t getMemData(CPU_EXEC_CONTEXT *xc, Packet *packet) {
109        switch (packet->getSize())
110        {
111          case 1:
112            return packet->get<uint8_t>();
113
114          case 2:
115            return packet->get<uint16_t>();
116
117          case 4:
118            return packet->get<uint32_t>();
119
120          case 8:
121            return packet->get<uint64_t>();
122
123          default:
124            std::cerr << "bad store data size = " << packet->getSize() << std::endl;
125
126            assert(0);
127            return 0;
128        }
129    }
130
131
132}};
133
134def template LoadStoreDeclare {{
135    /**
136     * Static instruction class for "%(mnemonic)s".
137     */
138    class %(class_name)s : public %(base_class)s
139    {
140      public:
141
142        /// Constructor.
143        %(class_name)s(ExtMachInst machInst);
144
145        %(BasicExecDeclare)s
146
147        %(EACompDeclare)s
148
149        %(InitiateAccDeclare)s
150
151        %(CompleteAccDeclare)s
152    };
153}};
154
155def template EACompDeclare {{
156    Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
157}};
158
159def template InitiateAccDeclare {{
160    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
161}};
162
163
164def template CompleteAccDeclare {{
165    Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
166}};
167
168def template LoadStoreConstructor {{
169    %(class_name)s::%(class_name)s(ExtMachInst machInst)
170         : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
171    {
172        %(constructor)s;
173    }
174}};
175
176
177def template EACompExecute {{
178    Fault
179    %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
180                                   Trace::InstRecord *traceData) const
181    {
182        Addr EA;
183        Fault fault = NoFault;
184
185        if (this->isFloating()) {
186            %(fp_enable_check)s;
187
188            if(fault != NoFault)
189                return fault;
190        }
191
192        %(op_decl)s;
193        %(op_rd)s;
194        %(ea_code)s;
195
196        // NOTE: Trace Data is written using execute or completeAcc templates
197        if (fault == NoFault) {
198            xc->setEA(EA);
199        }
200
201        return fault;
202    }
203}};
204
205def template LoadExecute {{
206    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
207                                  Trace::InstRecord *traceData) const
208    {
209        Addr EA;
210        Fault fault = NoFault;
211
212        if (this->isFloating()) {
213            %(fp_enable_check)s;
214
215            if(fault != NoFault)
216                return fault;
217        }
218
219        %(op_decl)s;
220        %(op_rd)s;
221        %(ea_code)s;
222
223        if (fault == NoFault) {
224            fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
225            %(memacc_code)s;
226        }
227
228        if (fault == NoFault) {
229            %(op_wb)s;
230        }
231
232        return fault;
233    }
234}};
235
236
237def template LoadInitiateAcc {{
238    Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
239                                      Trace::InstRecord *traceData) const
240    {
241        Addr EA;
242        Fault fault = NoFault;
243
244        if (this->isFloating()) {
245            %(fp_enable_check)s;
246
247            if(fault != NoFault)
248                return fault;
249        }
250
251        %(op_src_decl)s;
252        %(op_rd)s;
253        %(ea_code)s;
254
255        if (fault == NoFault) {
256            fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
257        }
258
259        return fault;
260    }
261}};
262
263def template LoadCompleteAcc {{
264    Fault %(class_name)s::completeAcc(Packet *pkt,
265                                      CPU_EXEC_CONTEXT *xc,
266                                      Trace::InstRecord *traceData) const
267    {
268        Fault fault = NoFault;
269
270        if (this->isFloating()) {
271            %(fp_enable_check)s;
272
273            if(fault != NoFault)
274                return fault;
275        }
276
277        %(op_decl)s;
278        %(op_rd)s;
279
280        getMem(pkt, Mem, traceData);
281
282        if (fault == NoFault) {
283            %(memacc_code)s;
284        }
285
286        if (fault == NoFault) {
287            %(op_wb)s;
288        }
289
290        return fault;
291    }
292}};
293
294def template StoreExecute {{
295    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
296                                  Trace::InstRecord *traceData) const
297    {
298        Addr EA;
299        Fault fault = NoFault;
300
301        %(fp_enable_check)s;
302        %(op_decl)s;
303        %(op_rd)s;
304        %(ea_code)s;
305
306        if (fault == NoFault) {
307            %(memacc_code)s;
308        }
309
310        if (fault == NoFault) {
311            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
312                    NULL);
313        }
314
315        if (fault == NoFault) {
316            %(postacc_code)s;
317        }
318
319        if (fault == NoFault) {
320            %(op_wb)s;
321        }
322
323        return fault;
324    }
325}};
326
327
328def template StoreFPExecute {{
329    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
330                                  Trace::InstRecord *traceData) const
331    {
332        Addr EA;
333        Fault fault = NoFault;
334
335        %(fp_enable_check)s;
336        if(fault != NoFault)
337          return fault;
338        %(op_decl)s;
339        %(op_rd)s;
340        %(ea_code)s;
341
342        if (fault == NoFault) {
343            %(memacc_code)s;
344        }
345
346        if (fault == NoFault) {
347            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
348                    NULL);
349        }
350
351        if (fault == NoFault) {
352            %(postacc_code)s;
353        }
354
355        if (fault == NoFault) {
356            %(op_wb)s;
357        }
358
359        return fault;
360    }
361}};
362
363def template StoreCondExecute {{
364    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
365                                  Trace::InstRecord *traceData) const
366    {
367        Addr EA;
368        Fault fault = NoFault;
369        uint64_t write_result = 0;
370
371        %(fp_enable_check)s;
372        %(op_decl)s;
373        %(op_rd)s;
374        %(ea_code)s;
375
376        if (fault == NoFault) {
377            %(memacc_code)s;
378        }
379
380        if (fault == NoFault) {
381            fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
382                    &write_result);
383        }
384
385        if (fault == NoFault) {
386            %(postacc_code)s;
387        }
388
389        if (fault == NoFault) {
390            %(op_wb)s;
391        }
392
393        return fault;
394    }
395}};
396
397def template StoreInitiateAcc {{
398    Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
399                                      Trace::InstRecord *traceData) const
400    {
401        Addr EA;
402        Fault fault = NoFault;
403
404        %(fp_enable_check)s;
405        %(op_decl)s;
406        %(op_rd)s;
407        %(ea_code)s;
408
409        if (fault == NoFault) {
410            %(memacc_code)s;
411        }
412
413        if (fault == NoFault) {
414            fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
415                    NULL);
416        }
417
418        return fault;
419    }
420}};
421
422
423def template StoreCompleteAcc {{
424    Fault %(class_name)s::completeAcc(Packet *pkt,
425                                      CPU_EXEC_CONTEXT *xc,
426                                      Trace::InstRecord *traceData) const
427    {
428        return NoFault;
429    }
430}};
431
432def template StoreCondCompleteAcc {{
433    Fault %(class_name)s::completeAcc(Packet *pkt,
434                                      CPU_EXEC_CONTEXT *xc,
435                                      Trace::InstRecord *traceData) const
436    {
437        Fault fault = NoFault;
438
439        %(fp_enable_check)s;
440        %(op_dest_decl)s;
441
442        uint64_t write_result = pkt->req->getExtraData();
443
444        if (fault == NoFault) {
445            %(postacc_code)s;
446        }
447
448        if (fault == NoFault) {
449            %(op_wb)s;
450        }
451
452        return fault;
453    }
454}};
455
456def template MiscExecute {{
457    Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
458                                  Trace::InstRecord *traceData) const
459    {
460        Addr EA M5_VAR_USED = 0;
461        Fault fault = NoFault;
462
463        %(fp_enable_check)s;
464        %(op_decl)s;
465        %(op_rd)s;
466        %(ea_code)s;
467
468        if (fault == NoFault) {
469            %(memacc_code)s;
470        }
471
472        return NoFault;
473    }
474}};
475
476def template MiscInitiateAcc {{
477    Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
478                                      Trace::InstRecord *traceData) const
479    {
480        panic("Misc instruction does not support split access method!");
481        return NoFault;
482    }
483}};
484
485
486def template MiscCompleteAcc {{
487    Fault %(class_name)s::completeAcc(Packet *pkt,
488                                      CPU_EXEC_CONTEXT *xc,
489                                      Trace::InstRecord *traceData) const
490    {
491        panic("Misc instruction does not support split access method!");
492
493        return NoFault;
494    }
495}};
496
497def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
498                     mem_flags = [], inst_flags = []) {{
499    (header_output, decoder_output, decode_block, exec_output) = \
500        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
501                      decode_template = ImmNopCheckDecode,
502                      exec_template_base = 'Load')
503}};
504
505
506def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
507                     mem_flags = [], inst_flags = []) {{
508    (header_output, decoder_output, decode_block, exec_output) = \
509        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
510                      exec_template_base = 'Store')
511}};
512
513def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
514                     mem_flags = [], inst_flags = []) {{
515    inst_flags += ['IsIndexed']
516    (header_output, decoder_output, decode_block, exec_output) = \
517        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
518                      decode_template = ImmNopCheckDecode,
519                      exec_template_base = 'Load')
520}};
521
522def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
523                     mem_flags = [], inst_flags = []) {{
524    inst_flags += ['IsIndexed']
525    (header_output, decoder_output, decode_block, exec_output) = \
526        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
527                      exec_template_base = 'Store')
528}};
529
530def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
531                     mem_flags = [], inst_flags = []) {{
532    inst_flags += ['IsIndexed', 'IsFloating']
533    (header_output, decoder_output, decode_block, exec_output) = \
534        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
535                      decode_template = ImmNopCheckDecode,
536                      exec_template_base = 'Load')
537}};
538
539def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }},
540                     mem_flags = [], inst_flags = []) {{
541    inst_flags += ['IsIndexed', 'IsFloating']
542    (header_output, decoder_output, decode_block, exec_output) = \
543        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
544                      exec_template_base = 'Store')
545}};
546
547
548def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
549                     mem_flags = [], inst_flags = []) {{
550    decl_code = '''
551        uint32_t mem_word = Mem_uw;
552        uint32_t unalign_addr = Rs + disp;
553        uint32_t byte_offset = unalign_addr & 3;
554        if (GuestByteOrder == BigEndianByteOrder)
555            byte_offset ^= 3;
556    '''
557
558    memacc_code = decl_code + memacc_code
559
560    (header_output, decoder_output, decode_block, exec_output) = \
561        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
562                      decode_template = ImmNopCheckDecode,
563                      exec_template_base = 'Load')
564}};
565
566def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }},
567                     mem_flags = [], inst_flags = []) {{
568    decl_code = '''
569        uint32_t mem_word = 0;
570        uint32_t unaligned_addr = Rs + disp;
571        uint32_t byte_offset = unaligned_addr & 3;
572        if (GuestByteOrder == BigEndianByteOrder)
573            byte_offset ^= 3;
574        fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags);
575    '''
576    memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
577
578    (header_output, decoder_output, decode_block, exec_output) = \
579        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
580                      exec_template_base = 'Store')
581}};
582
583def format Prefetch(ea_code = {{ EA = Rs + disp; }},
584                          mem_flags = [], pf_flags = [], inst_flags = []) {{
585    pf_mem_flags = mem_flags + pf_flags + ['PREFETCH']
586    pf_inst_flags = inst_flags
587
588    (header_output, decoder_output, decode_block, exec_output) = \
589        LoadStoreBase(name, Name, ea_code,
590                      'warn_once("Prefetching not implemented for MIPS\\n");',
591                      pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc')
592
593}};
594
595def format StoreCond(memacc_code, postacc_code,
596                     ea_code = {{ EA = Rs + disp; }},
597                     mem_flags = [], inst_flags = []) {{
598    (header_output, decoder_output, decode_block, exec_output) = \
599        LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
600                      postacc_code, exec_template_base = 'StoreCond')
601}};
602