mem.isa revision 8564
110389SAndreas.Sandberg@ARM.com// -*- mode:c++ -*- 210389SAndreas.Sandberg@ARM.com 310389SAndreas.Sandberg@ARM.com// Copyright (c) 2007 MIPS Technologies, Inc. 410389SAndreas.Sandberg@ARM.com// All rights reserved. 510389SAndreas.Sandberg@ARM.com// 610389SAndreas.Sandberg@ARM.com// Redistribution and use in source and binary forms, with or without 710389SAndreas.Sandberg@ARM.com// modification, are permitted provided that the following conditions are 810389SAndreas.Sandberg@ARM.com// met: redistributions of source code must retain the above copyright 910389SAndreas.Sandberg@ARM.com// notice, this list of conditions and the following disclaimer; 1010389SAndreas.Sandberg@ARM.com// redistributions in binary form must reproduce the above copyright 1110389SAndreas.Sandberg@ARM.com// notice, this list of conditions and the following disclaimer in the 1210389SAndreas.Sandberg@ARM.com// documentation and/or other materials provided with the distribution; 1310389SAndreas.Sandberg@ARM.com// neither the name of the copyright holders nor the names of its 1410389SAndreas.Sandberg@ARM.com// contributors may be used to endorse or promote products derived from 1510389SAndreas.Sandberg@ARM.com// this software without specific prior written permission. 1610389SAndreas.Sandberg@ARM.com// 1710389SAndreas.Sandberg@ARM.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1810389SAndreas.Sandberg@ARM.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1910389SAndreas.Sandberg@ARM.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2010389SAndreas.Sandberg@ARM.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2110389SAndreas.Sandberg@ARM.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2210389SAndreas.Sandberg@ARM.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2310389SAndreas.Sandberg@ARM.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2410389SAndreas.Sandberg@ARM.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2510389SAndreas.Sandberg@ARM.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2610389SAndreas.Sandberg@ARM.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2710389SAndreas.Sandberg@ARM.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2810389SAndreas.Sandberg@ARM.com// 2910389SAndreas.Sandberg@ARM.com// Authors: Steve Reinhardt 3010389SAndreas.Sandberg@ARM.com// Korey Sewell 3110389SAndreas.Sandberg@ARM.com 3210389SAndreas.Sandberg@ARM.com//////////////////////////////////////////////////////////////////// 3310389SAndreas.Sandberg@ARM.com// 3410389SAndreas.Sandberg@ARM.com// Memory-format instructions 3510389SAndreas.Sandberg@ARM.com// 3610389SAndreas.Sandberg@ARM.com 3710389SAndreas.Sandberg@ARM.comoutput header {{ 3810389SAndreas.Sandberg@ARM.com /** 3910389SAndreas.Sandberg@ARM.com * Base class for general Mips memory-format instructions. 4011793Sbrandon.potter@amd.com */ 4111793Sbrandon.potter@amd.com class Memory : public MipsStaticInst 4210389SAndreas.Sandberg@ARM.com { 4310389SAndreas.Sandberg@ARM.com protected: 4410389SAndreas.Sandberg@ARM.com /// Memory request flags. See mem_req_base.hh. 4510389SAndreas.Sandberg@ARM.com Request::Flags memAccessFlags; 4610389SAndreas.Sandberg@ARM.com 4710389SAndreas.Sandberg@ARM.com /// Displacement for EA calculation (signed). 4810389SAndreas.Sandberg@ARM.com int32_t disp; 4910389SAndreas.Sandberg@ARM.com 5012237Sandreas.sandberg@arm.com /// Constructor 5110389SAndreas.Sandberg@ARM.com Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 5210389SAndreas.Sandberg@ARM.com : MipsStaticInst(mnem, _machInst, __opClass), 5310389SAndreas.Sandberg@ARM.com disp(sext<16>(OFFSET)) 5410389SAndreas.Sandberg@ARM.com { 5510389SAndreas.Sandberg@ARM.com } 5610389SAndreas.Sandberg@ARM.com 5710389SAndreas.Sandberg@ARM.com std::string 5812237Sandreas.sandberg@arm.com generateDisassembly(Addr pc, const SymbolTable *symtab) const; 5910389SAndreas.Sandberg@ARM.com }; 6010389SAndreas.Sandberg@ARM.com 6110389SAndreas.Sandberg@ARM.com /** 6210389SAndreas.Sandberg@ARM.com * Base class for a few miscellaneous memory-format insts 6310389SAndreas.Sandberg@ARM.com * that don't interpret the disp field 6410389SAndreas.Sandberg@ARM.com */ 6510389SAndreas.Sandberg@ARM.com class MemoryNoDisp : public Memory 6610389SAndreas.Sandberg@ARM.com { 6710389SAndreas.Sandberg@ARM.com protected: 6810389SAndreas.Sandberg@ARM.com /// Constructor 6910389SAndreas.Sandberg@ARM.com MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 7010389SAndreas.Sandberg@ARM.com : Memory(mnem, _machInst, __opClass) 7110389SAndreas.Sandberg@ARM.com { 7210389SAndreas.Sandberg@ARM.com } 7310389SAndreas.Sandberg@ARM.com 7410389SAndreas.Sandberg@ARM.com std::string 7510389SAndreas.Sandberg@ARM.com generateDisassembly(Addr pc, const SymbolTable *symtab) const; 7610389SAndreas.Sandberg@ARM.com }; 7710389SAndreas.Sandberg@ARM.com}}; 7810389SAndreas.Sandberg@ARM.com 7910389SAndreas.Sandberg@ARM.com 8010389SAndreas.Sandberg@ARM.comoutput decoder {{ 8110389SAndreas.Sandberg@ARM.com std::string 8210389SAndreas.Sandberg@ARM.com Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 8310389SAndreas.Sandberg@ARM.com { 8412237Sandreas.sandberg@arm.com return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 8510389SAndreas.Sandberg@ARM.com flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 8610389SAndreas.Sandberg@ARM.com } 8712237Sandreas.sandberg@arm.com 8812237Sandreas.sandberg@arm.com std::string 8910389SAndreas.Sandberg@ARM.com MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9010389SAndreas.Sandberg@ARM.com { 9110389SAndreas.Sandberg@ARM.com return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 9210389SAndreas.Sandberg@ARM.com flags[IsFloating] ? 'f' : 'r', 9310389SAndreas.Sandberg@ARM.com flags[IsFloating] ? FD : RD, 9410389SAndreas.Sandberg@ARM.com RS, RT); 9510389SAndreas.Sandberg@ARM.com } 9610389SAndreas.Sandberg@ARM.com 9710389SAndreas.Sandberg@ARM.com}}; 9810389SAndreas.Sandberg@ARM.com 9910389SAndreas.Sandberg@ARM.comoutput exec {{ 10010389SAndreas.Sandberg@ARM.com /** return data in cases where there the size of data is only 10110389SAndreas.Sandberg@ARM.com known in the packet 10210389SAndreas.Sandberg@ARM.com */ 10310389SAndreas.Sandberg@ARM.com uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) { 10410389SAndreas.Sandberg@ARM.com switch (packet->getSize()) 10510389SAndreas.Sandberg@ARM.com { 10610389SAndreas.Sandberg@ARM.com case 1: 10710389SAndreas.Sandberg@ARM.com return packet->get<uint8_t>(); 10810389SAndreas.Sandberg@ARM.com 10910389SAndreas.Sandberg@ARM.com case 2: 11010389SAndreas.Sandberg@ARM.com return packet->get<uint16_t>(); 11112237Sandreas.sandberg@arm.com 11210389SAndreas.Sandberg@ARM.com case 4: 11310389SAndreas.Sandberg@ARM.com return packet->get<uint32_t>(); 11410389SAndreas.Sandberg@ARM.com 11510389SAndreas.Sandberg@ARM.com case 8: 11610389SAndreas.Sandberg@ARM.com return packet->get<uint64_t>(); 11710389SAndreas.Sandberg@ARM.com 11810389SAndreas.Sandberg@ARM.com default: 11910389SAndreas.Sandberg@ARM.com std::cerr << "bad store data size = " << packet->getSize() << std::endl; 12010389SAndreas.Sandberg@ARM.com 12110389SAndreas.Sandberg@ARM.com assert(0); 12210389SAndreas.Sandberg@ARM.com return 0; 123 } 124 } 125 126 127}}; 128 129def template LoadStoreDeclare {{ 130 /** 131 * Static instruction class for "%(mnemonic)s". 132 */ 133 class %(class_name)s : public %(base_class)s 134 { 135 public: 136 137 /// Constructor. 138 %(class_name)s(ExtMachInst machInst); 139 140 %(BasicExecDeclare)s 141 142 %(EACompDeclare)s 143 144 %(InitiateAccDeclare)s 145 146 %(CompleteAccDeclare)s 147 }; 148}}; 149 150def template EACompDeclare {{ 151 Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 152}}; 153 154def template InitiateAccDeclare {{ 155 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 156}}; 157 158 159def template CompleteAccDeclare {{ 160 Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 161}}; 162 163def template LoadStoreConstructor {{ 164 inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 165 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 166 { 167 %(constructor)s; 168 } 169}}; 170 171 172def template EACompExecute {{ 173 Fault 174 %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 175 Trace::InstRecord *traceData) const 176 { 177 Addr EA; 178 Fault fault = NoFault; 179 180 if (this->isFloating()) { 181 %(fp_enable_check)s; 182 183 if(fault != NoFault) 184 return fault; 185 } 186 187 %(op_decl)s; 188 %(op_rd)s; 189 %(ea_code)s; 190 191 // NOTE: Trace Data is written using execute or completeAcc templates 192 if (fault == NoFault) { 193 xc->setEA(EA); 194 } 195 196 return fault; 197 } 198}}; 199 200def template LoadExecute {{ 201 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 202 Trace::InstRecord *traceData) const 203 { 204 Addr EA; 205 Fault fault = NoFault; 206 207 if (this->isFloating()) { 208 %(fp_enable_check)s; 209 210 if(fault != NoFault) 211 return fault; 212 } 213 214 %(op_decl)s; 215 %(op_rd)s; 216 %(ea_code)s; 217 218 if (fault == NoFault) { 219 fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 220 %(memacc_code)s; 221 } 222 223 if (fault == NoFault) { 224 %(op_wb)s; 225 } 226 227 return fault; 228 } 229}}; 230 231 232def template LoadInitiateAcc {{ 233 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 234 Trace::InstRecord *traceData) const 235 { 236 Addr EA; 237 Fault fault = NoFault; 238 239 if (this->isFloating()) { 240 %(fp_enable_check)s; 241 242 if(fault != NoFault) 243 return fault; 244 } 245 246 %(op_src_decl)s; 247 %(op_rd)s; 248 %(ea_code)s; 249 250 if (fault == NoFault) { 251 fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags); 252 } 253 254 return fault; 255 } 256}}; 257 258def template LoadCompleteAcc {{ 259 Fault %(class_name)s::completeAcc(Packet *pkt, 260 %(CPU_exec_context)s *xc, 261 Trace::InstRecord *traceData) const 262 { 263 Fault fault = NoFault; 264 265 if (this->isFloating()) { 266 %(fp_enable_check)s; 267 268 if(fault != NoFault) 269 return fault; 270 } 271 272 %(op_decl)s; 273 %(op_rd)s; 274 275 getMem(pkt, Mem, traceData); 276 277 if (fault == NoFault) { 278 %(memacc_code)s; 279 } 280 281 if (fault == NoFault) { 282 %(op_wb)s; 283 } 284 285 return fault; 286 } 287}}; 288 289def template StoreExecute {{ 290 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 291 Trace::InstRecord *traceData) const 292 { 293 Addr EA; 294 Fault fault = NoFault; 295 296 %(fp_enable_check)s; 297 %(op_decl)s; 298 %(op_rd)s; 299 %(ea_code)s; 300 301 if (fault == NoFault) { 302 %(memacc_code)s; 303 } 304 305 if (fault == NoFault) { 306 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 307 NULL); 308 } 309 310 if (fault == NoFault) { 311 %(postacc_code)s; 312 } 313 314 if (fault == NoFault) { 315 %(op_wb)s; 316 } 317 318 return fault; 319 } 320}}; 321 322 323def template StoreFPExecute {{ 324 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 325 Trace::InstRecord *traceData) const 326 { 327 Addr EA; 328 Fault fault = NoFault; 329 330 %(fp_enable_check)s; 331 if(fault != NoFault) 332 return fault; 333 %(op_decl)s; 334 %(op_rd)s; 335 %(ea_code)s; 336 337 if (fault == NoFault) { 338 %(memacc_code)s; 339 } 340 341 if (fault == NoFault) { 342 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 343 NULL); 344 } 345 346 if (fault == NoFault) { 347 %(postacc_code)s; 348 } 349 350 if (fault == NoFault) { 351 %(op_wb)s; 352 } 353 354 return fault; 355 } 356}}; 357 358def template StoreCondExecute {{ 359 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 360 Trace::InstRecord *traceData) const 361 { 362 Addr EA; 363 Fault fault = NoFault; 364 uint64_t write_result = 0; 365 366 %(fp_enable_check)s; 367 %(op_decl)s; 368 %(op_rd)s; 369 %(ea_code)s; 370 371 if (fault == NoFault) { 372 %(memacc_code)s; 373 } 374 375 if (fault == NoFault) { 376 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 377 &write_result); 378 } 379 380 if (fault == NoFault) { 381 %(postacc_code)s; 382 } 383 384 if (fault == NoFault) { 385 %(op_wb)s; 386 } 387 388 return fault; 389 } 390}}; 391 392def template StoreInitiateAcc {{ 393 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 394 Trace::InstRecord *traceData) const 395 { 396 Addr EA; 397 Fault fault = NoFault; 398 399 %(fp_enable_check)s; 400 %(op_decl)s; 401 %(op_rd)s; 402 %(ea_code)s; 403 404 if (fault == NoFault) { 405 %(memacc_code)s; 406 } 407 408 if (fault == NoFault) { 409 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 410 NULL); 411 } 412 413 return fault; 414 } 415}}; 416 417 418def template StoreCompleteAcc {{ 419 Fault %(class_name)s::completeAcc(Packet *pkt, 420 %(CPU_exec_context)s *xc, 421 Trace::InstRecord *traceData) const 422 { 423 return NoFault; 424 } 425}}; 426 427def template StoreCondCompleteAcc {{ 428 Fault %(class_name)s::completeAcc(Packet *pkt, 429 %(CPU_exec_context)s *xc, 430 Trace::InstRecord *traceData) const 431 { 432 Fault fault = NoFault; 433 434 %(fp_enable_check)s; 435 %(op_dest_decl)s; 436 437 uint64_t write_result = pkt->req->getExtraData(); 438 439 if (fault == NoFault) { 440 %(postacc_code)s; 441 } 442 443 if (fault == NoFault) { 444 %(op_wb)s; 445 } 446 447 return fault; 448 } 449}}; 450 451def template MiscExecute {{ 452 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 453 Trace::InstRecord *traceData) const 454 { 455 Addr EA M5_VAR_USED = 0; 456 Fault fault = NoFault; 457 458 %(fp_enable_check)s; 459 %(op_decl)s; 460 %(op_rd)s; 461 %(ea_code)s; 462 463 if (fault == NoFault) { 464 %(memacc_code)s; 465 } 466 467 return NoFault; 468 } 469}}; 470 471def template MiscInitiateAcc {{ 472 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 473 Trace::InstRecord *traceData) const 474 { 475 panic("Misc instruction does not support split access method!"); 476 return NoFault; 477 } 478}}; 479 480 481def template MiscCompleteAcc {{ 482 Fault %(class_name)s::completeAcc(Packet *pkt, 483 %(CPU_exec_context)s *xc, 484 Trace::InstRecord *traceData) const 485 { 486 panic("Misc instruction does not support split access method!"); 487 488 return NoFault; 489 } 490}}; 491 492def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 493 mem_flags = [], inst_flags = []) {{ 494 (header_output, decoder_output, decode_block, exec_output) = \ 495 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 496 decode_template = ImmNopCheckDecode, 497 exec_template_base = 'Load') 498}}; 499 500 501def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 502 mem_flags = [], inst_flags = []) {{ 503 (header_output, decoder_output, decode_block, exec_output) = \ 504 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 505 exec_template_base = 'Store') 506}}; 507 508def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 509 mem_flags = [], inst_flags = []) {{ 510 inst_flags += ['IsIndexed'] 511 (header_output, decoder_output, decode_block, exec_output) = \ 512 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 513 decode_template = ImmNopCheckDecode, 514 exec_template_base = 'Load') 515}}; 516 517def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 518 mem_flags = [], inst_flags = []) {{ 519 inst_flags += ['IsIndexed'] 520 (header_output, decoder_output, decode_block, exec_output) = \ 521 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 522 exec_template_base = 'Store') 523}}; 524 525def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 526 mem_flags = [], inst_flags = []) {{ 527 inst_flags += ['IsIndexed', 'IsFloating'] 528 (header_output, decoder_output, decode_block, exec_output) = \ 529 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 530 decode_template = ImmNopCheckDecode, 531 exec_template_base = 'Load') 532}}; 533 534def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 535 mem_flags = [], inst_flags = []) {{ 536 inst_flags += ['IsIndexed', 'IsFloating'] 537 (header_output, decoder_output, decode_block, exec_output) = \ 538 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 539 exec_template_base = 'Store') 540}}; 541 542 543def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 544 mem_flags = [], inst_flags = []) {{ 545 decl_code = ''' 546 uint32_t mem_word = Mem.uw; 547 uint32_t unalign_addr = Rs + disp; 548 uint32_t byte_offset = unalign_addr & 3; 549 if (GuestByteOrder == BigEndianByteOrder) 550 byte_offset ^= 3; 551 ''' 552 553 memacc_code = decl_code + memacc_code 554 555 (header_output, decoder_output, decode_block, exec_output) = \ 556 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 557 decode_template = ImmNopCheckDecode, 558 exec_template_base = 'Load') 559}}; 560 561def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 562 mem_flags = [], inst_flags = []) {{ 563 decl_code = ''' 564 uint32_t mem_word = 0; 565 uint32_t unaligned_addr = Rs + disp; 566 uint32_t byte_offset = unaligned_addr & 3; 567 if (GuestByteOrder == BigEndianByteOrder) 568 byte_offset ^= 3; 569 fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags); 570 ''' 571 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 572 573 (header_output, decoder_output, decode_block, exec_output) = \ 574 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 575 exec_template_base = 'Store') 576}}; 577 578def format Prefetch(ea_code = {{ EA = Rs + disp; }}, 579 mem_flags = [], pf_flags = [], inst_flags = []) {{ 580 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 581 pf_inst_flags = inst_flags 582 583 (header_output, decoder_output, decode_block, exec_output) = \ 584 LoadStoreBase(name, Name, ea_code, 585 'warn_once("Prefetching not implemented for MIPS\\n");', 586 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 587 588}}; 589 590def format StoreCond(memacc_code, postacc_code, 591 ea_code = {{ EA = Rs + disp; }}, 592 mem_flags = [], inst_flags = []) {{ 593 (header_output, decoder_output, decode_block, exec_output) = \ 594 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 595 postacc_code, exec_template_base = 'StoreCond') 596}}; 597