mem.isa revision 7725
11689SN/A// -*- mode:c++ -*- 29444SAndreas.Sandberg@ARM.com 37598Sminkyu.jeong@arm.com// Copyright (c) 2007 MIPS Technologies, Inc. 47598Sminkyu.jeong@arm.com// All rights reserved. 57598Sminkyu.jeong@arm.com// 67598Sminkyu.jeong@arm.com// Redistribution and use in source and binary forms, with or without 77598Sminkyu.jeong@arm.com// modification, are permitted provided that the following conditions are 87598Sminkyu.jeong@arm.com// met: redistributions of source code must retain the above copyright 97598Sminkyu.jeong@arm.com// notice, this list of conditions and the following disclaimer; 107598Sminkyu.jeong@arm.com// redistributions in binary form must reproduce the above copyright 117598Sminkyu.jeong@arm.com// notice, this list of conditions and the following disclaimer in the 127598Sminkyu.jeong@arm.com// documentation and/or other materials provided with the distribution; 137598Sminkyu.jeong@arm.com// neither the name of the copyright holders nor the names of its 142326SN/A// contributors may be used to endorse or promote products derived from 151689SN/A// this software without specific prior written permission. 161689SN/A// 171689SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 281689SN/A// 291689SN/A// Authors: Steve Reinhardt 301689SN/A// Korey Sewell 311689SN/A 321689SN/A//////////////////////////////////////////////////////////////////// 331689SN/A// 341689SN/A// Memory-format instructions 351689SN/A// 361689SN/A 371689SN/Aoutput header {{ 381689SN/A /** 392665Ssaidi@eecs.umich.edu * Base class for general Mips memory-format instructions. 402665Ssaidi@eecs.umich.edu */ 411689SN/A class Memory : public MipsStaticInst 421689SN/A { 431060SN/A protected: 441060SN/A /// Memory request flags. See mem_req_base.hh. 451689SN/A Request::Flags memAccessFlags; 461060SN/A 471060SN/A /// Displacement for EA calculation (signed). 481060SN/A int32_t disp; 498230Snate@binkert.org 506658Snate@binkert.org /// Constructor 518887Sgeoffrey.blake@arm.com Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 522292SN/A : MipsStaticInst(mnem, _machInst, __opClass), 531717SN/A disp(sext<16>(OFFSET)) 548229Snate@binkert.org { 558232Snate@binkert.org } 568232Snate@binkert.org 579444SAndreas.Sandberg@ARM.com std::string 588232Snate@binkert.org generateDisassembly(Addr pc, const SymbolTable *symtab) const; 599527SMatt.Horsnell@arm.com }; 605529Snate@binkert.org 611060SN/A /** 626221Snate@binkert.org * Base class for a few miscellaneous memory-format insts 636221Snate@binkert.org * that don't interpret the disp field 641681SN/A */ 655529Snate@binkert.org class MemoryNoDisp : public Memory 662873Sktlim@umich.edu { 674329Sktlim@umich.edu protected: 684329Sktlim@umich.edu /// Constructor 694329Sktlim@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 702292SN/A : Memory(mnem, _machInst, __opClass) 712292SN/A { 722292SN/A } 732292SN/A 742820Sktlim@umich.edu std::string 752292SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 762820Sktlim@umich.edu }; 772820Sktlim@umich.edu}}; 789444SAndreas.Sandberg@ARM.com 791060SN/A 802292SN/Aoutput decoder {{ 812292SN/A std::string 822292SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 831060SN/A { 841060SN/A return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 851060SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 861060SN/A } 871060SN/A 881060SN/A std::string 891681SN/A MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 906221Snate@binkert.org { 916221Snate@binkert.org return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 926221Snate@binkert.org flags[IsFloating] ? 'f' : 'r', 936221Snate@binkert.org flags[IsFloating] ? FD : RD, 942292SN/A RS, RT); 952292SN/A } 962820Sktlim@umich.edu 972820Sktlim@umich.edu}}; 982292SN/A 992292SN/Aoutput exec {{ 1002820Sktlim@umich.edu /** return data in cases where there the size of data is only 1012820Sktlim@umich.edu known in the packet 1022292SN/A */ 1032292SN/A uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) { 1042292SN/A switch (packet->getSize()) 1052292SN/A { 1062292SN/A case 1: 1072292SN/A return packet->get<uint8_t>(); 1082292SN/A 1092292SN/A case 2: 1101060SN/A return packet->get<uint16_t>(); 1111060SN/A 1121681SN/A case 4: 1131062SN/A return packet->get<uint32_t>(); 1142292SN/A 1151062SN/A case 8: 1162301SN/A return packet->get<uint64_t>(); 1172301SN/A 1181062SN/A default: 1192727Sktlim@umich.edu std::cerr << "bad store data size = " << packet->getSize() << std::endl; 1201062SN/A 1211062SN/A assert(0); 1221062SN/A return 0; 1231062SN/A } 1241062SN/A } 1251062SN/A 1261062SN/A 1271062SN/A}}; 1281062SN/A 1291062SN/Adef template LoadStoreDeclare {{ 1301062SN/A /** 1311062SN/A * Static instruction class for "%(mnemonic)s". 1321062SN/A */ 1331062SN/A class %(class_name)s : public %(base_class)s 1341062SN/A { 1351062SN/A public: 1361062SN/A 1371062SN/A /// Constructor. 1381062SN/A %(class_name)s(ExtMachInst machInst); 1391062SN/A 1401062SN/A %(BasicExecDeclare)s 1411062SN/A 1421062SN/A %(EACompDeclare)s 1431062SN/A 1441062SN/A %(InitiateAccDeclare)s 1451062SN/A 1461062SN/A %(CompleteAccDeclare)s 1471062SN/A }; 1481062SN/A}}; 1491062SN/A 1501062SN/Adef template EACompDeclare {{ 1511062SN/A Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1521062SN/A}}; 1531062SN/A 1541062SN/Adef template InitiateAccDeclare {{ 1551062SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1561062SN/A}}; 1571062SN/A 1581062SN/A 1591062SN/Adef template CompleteAccDeclare {{ 1601062SN/A Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1612292SN/A}}; 1622292SN/A 1632292SN/Adef template LoadStoreConstructor {{ 1642292SN/A inline %(class_name)s::%(class_name)s(ExtMachInst machInst) 1651062SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1661062SN/A { 1671062SN/A %(constructor)s; 1681062SN/A } 1691062SN/A}}; 1701062SN/A 1711062SN/A 1722292SN/Adef template EACompExecute {{ 1732292SN/A Fault 1742292SN/A %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 1752292SN/A Trace::InstRecord *traceData) const 1762292SN/A { 1772292SN/A Addr EA; 1782292SN/A Fault fault = NoFault; 1792292SN/A 1802292SN/A if (this->isFloating()) { 1812292SN/A %(fp_enable_check)s; 1822301SN/A 1832727Sktlim@umich.edu if(fault != NoFault) 1842353SN/A return fault; 1852727Sktlim@umich.edu } 1862727Sktlim@umich.edu 1872727Sktlim@umich.edu %(op_decl)s; 1886221Snate@binkert.org %(op_rd)s; 1892353SN/A %(ea_code)s; 1902727Sktlim@umich.edu 1912727Sktlim@umich.edu // NOTE: Trace Data is written using execute or completeAcc templates 1922727Sktlim@umich.edu if (fault == NoFault) { 1932727Sktlim@umich.edu xc->setEA(EA); 1942353SN/A } 1952727Sktlim@umich.edu 1962727Sktlim@umich.edu return fault; 1972727Sktlim@umich.edu } 1986221Snate@binkert.org}}; 1998240Snate@binkert.org 2002301SN/Adef template LoadExecute {{ 2012727Sktlim@umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2022301SN/A Trace::InstRecord *traceData) const 2032727Sktlim@umich.edu { 2046221Snate@binkert.org Addr EA; 2058240Snate@binkert.org Fault fault = NoFault; 2062301SN/A 2072727Sktlim@umich.edu if (this->isFloating()) { 2082301SN/A %(fp_enable_check)s; 2092727Sktlim@umich.edu 2106221Snate@binkert.org if(fault != NoFault) 2118240Snate@binkert.org return fault; 2122301SN/A } 2132727Sktlim@umich.edu 2142301SN/A %(op_decl)s; 2152727Sktlim@umich.edu %(op_rd)s; 2166221Snate@binkert.org %(ea_code)s; 2178240Snate@binkert.org 2182301SN/A if (fault == NoFault) { 2192727Sktlim@umich.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 2202301SN/A %(memacc_code)s; 2212301SN/A } 2228240Snate@binkert.org 2232301SN/A if (fault == NoFault) { 2242727Sktlim@umich.edu %(op_wb)s; 2252727Sktlim@umich.edu } 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu return fault; 2288240Snate@binkert.org } 2292727Sktlim@umich.edu}}; 2302727Sktlim@umich.edu 2312727Sktlim@umich.edu 2322727Sktlim@umich.edudef template LoadInitiateAcc {{ 2332301SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2342301SN/A Trace::InstRecord *traceData) const 2356221Snate@binkert.org { 2368240Snate@binkert.org Addr EA; 2372301SN/A Fault fault = NoFault; 2382727Sktlim@umich.edu 2392301SN/A if (this->isFloating()) { 2402326SN/A %(fp_enable_check)s; 2416221Snate@binkert.org 2428240Snate@binkert.org if(fault != NoFault) 2432301SN/A return fault; 2442727Sktlim@umich.edu } 2452301SN/A 2462326SN/A %(op_src_decl)s; 2476221Snate@binkert.org %(op_rd)s; 2488240Snate@binkert.org %(ea_code)s; 2492301SN/A 2502727Sktlim@umich.edu if (fault == NoFault) { 2512301SN/A fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 2522326SN/A } 2536221Snate@binkert.org 2548240Snate@binkert.org return fault; 2552301SN/A } 2562727Sktlim@umich.edu}}; 2572301SN/A 2582326SN/Adef template LoadCompleteAcc {{ 2596221Snate@binkert.org Fault %(class_name)s::completeAcc(Packet *pkt, 2608240Snate@binkert.org %(CPU_exec_context)s *xc, 2612301SN/A Trace::InstRecord *traceData) const 2622727Sktlim@umich.edu { 2632301SN/A Fault fault = NoFault; 2642326SN/A 2658240Snate@binkert.org if (this->isFloating()) { 2662301SN/A %(fp_enable_check)s; 2672727Sktlim@umich.edu 2682301SN/A if(fault != NoFault) 2692326SN/A return fault; 2702301SN/A } 2712326SN/A 2728240Snate@binkert.org %(op_decl)s; 2732301SN/A %(op_rd)s; 2742727Sktlim@umich.edu 2752301SN/A Mem = pkt->get<typeof(Mem)>(); 2762326SN/A 2772301SN/A if (fault == NoFault) { 2782326SN/A %(memacc_code)s; 2798240Snate@binkert.org } 2802301SN/A 2812727Sktlim@umich.edu if (fault == NoFault) { 2822326SN/A %(op_wb)s; 2831062SN/A } 2841062SN/A 2851681SN/A return fault; 2861060SN/A } 2879427SAndreas.Sandberg@ARM.com}}; 2881060SN/A 2896221Snate@binkert.orgdef template StoreExecute {{ 2902292SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2912292SN/A Trace::InstRecord *traceData) const 2922292SN/A { 2932292SN/A Addr EA; 2942292SN/A Fault fault = NoFault; 2952292SN/A 2962292SN/A %(fp_enable_check)s; 2972292SN/A %(op_decl)s; 2982292SN/A %(op_rd)s; 2998887Sgeoffrey.blake@arm.com %(ea_code)s; 3008733Sgeoffrey.blake@arm.com 3018850Sandreas.hansson@arm.com if (fault == NoFault) { 3028887Sgeoffrey.blake@arm.com %(memacc_code)s; 3038733Sgeoffrey.blake@arm.com } 3042733Sktlim@umich.edu 3051060SN/A if (fault == NoFault) { 3061060SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3071681SN/A memAccessFlags, NULL); 3081060SN/A } 3092292SN/A 3101060SN/A if (fault == NoFault) { 3111060SN/A %(postacc_code)s; 3121060SN/A } 3131060SN/A 3141060SN/A if (fault == NoFault) { 3151060SN/A %(op_wb)s; 3161060SN/A } 3171060SN/A 3181060SN/A return fault; 3192292SN/A } 3202292SN/A}}; 3211060SN/A 3221060SN/A 3231060SN/Adef template StoreFPExecute {{ 3241060SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3251681SN/A Trace::InstRecord *traceData) const 3261060SN/A { 3272292SN/A Addr EA; 3281060SN/A Fault fault = NoFault; 3291060SN/A 3301060SN/A %(fp_enable_check)s; 3311060SN/A if(fault != NoFault) 3321060SN/A return fault; 3331060SN/A %(op_decl)s; 3341060SN/A %(op_rd)s; 3351681SN/A %(ea_code)s; 3361060SN/A 3372292SN/A if (fault == NoFault) { 3381060SN/A %(memacc_code)s; 3391060SN/A } 3401060SN/A 3411060SN/A if (fault == NoFault) { 3421060SN/A fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3431060SN/A memAccessFlags, NULL); 3441060SN/A } 3451681SN/A 3461060SN/A if (fault == NoFault) { 3476221Snate@binkert.org %(postacc_code)s; 3481060SN/A } 3492292SN/A 3502292SN/A if (fault == NoFault) { 3512292SN/A %(op_wb)s; 3522292SN/A } 3531060SN/A 3541060SN/A return fault; 3551681SN/A } 3561060SN/A}}; 3572292SN/A 3581060SN/Adef template StoreCondExecute {{ 3592292SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3601060SN/A Trace::InstRecord *traceData) const 3611060SN/A { 3622307SN/A Addr EA; 3632863Sktlim@umich.edu Fault fault = NoFault; 3649444SAndreas.Sandberg@ARM.com uint64_t write_result = 0; 3652307SN/A 3669444SAndreas.Sandberg@ARM.com %(fp_enable_check)s; 3679444SAndreas.Sandberg@ARM.com %(op_decl)s; 3689444SAndreas.Sandberg@ARM.com %(op_rd)s; 3699444SAndreas.Sandberg@ARM.com %(ea_code)s; 3709444SAndreas.Sandberg@ARM.com 3719444SAndreas.Sandberg@ARM.com if (fault == NoFault) { 3729444SAndreas.Sandberg@ARM.com %(memacc_code)s; 3739444SAndreas.Sandberg@ARM.com } 3749444SAndreas.Sandberg@ARM.com 3759444SAndreas.Sandberg@ARM.com if (fault == NoFault) { 3769444SAndreas.Sandberg@ARM.com fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 3779444SAndreas.Sandberg@ARM.com memAccessFlags, &write_result); 3789444SAndreas.Sandberg@ARM.com } 3799444SAndreas.Sandberg@ARM.com 3801681SN/A if (fault == NoFault) { 3811681SN/A %(postacc_code)s; 3822316SN/A } 3831681SN/A 3849444SAndreas.Sandberg@ARM.com if (fault == NoFault) { 3852843Sktlim@umich.edu %(op_wb)s; 3869444SAndreas.Sandberg@ARM.com } 3872843Sktlim@umich.edu 3889444SAndreas.Sandberg@ARM.com return fault; 3899444SAndreas.Sandberg@ARM.com } 3909444SAndreas.Sandberg@ARM.com}}; 3911681SN/A 3921681SN/Adef template StoreInitiateAcc {{ 3932307SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3941681SN/A Trace::InstRecord *traceData) const 3952307SN/A { 3961060SN/A Addr EA; 3972348SN/A Fault fault = NoFault; 3982307SN/A 3992307SN/A %(fp_enable_check)s; 4002307SN/A %(op_decl)s; 4011060SN/A %(op_rd)s; 4022307SN/A %(ea_code)s; 4032307SN/A 4049444SAndreas.Sandberg@ARM.com if (fault == NoFault) { 4051060SN/A %(memacc_code)s; 4069427SAndreas.Sandberg@ARM.com } 4072307SN/A 4081060SN/A if (fault == NoFault) { 4096221Snate@binkert.org fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 4106221Snate@binkert.org memAccessFlags, NULL); 4116221Snate@binkert.org } 4126221Snate@binkert.org 4132307SN/A return fault; 4141060SN/A } 4152307SN/A}}; 4162307SN/A 4172873Sktlim@umich.edu 4182307SN/Adef template StoreCompleteAcc {{ 4191060SN/A Fault %(class_name)s::completeAcc(Packet *pkt, 4201060SN/A %(CPU_exec_context)s *xc, 4211060SN/A Trace::InstRecord *traceData) const 4221681SN/A { 4231060SN/A return NoFault; 4246221Snate@binkert.org } 4252107SN/A}}; 4266221Snate@binkert.org 4272107SN/Adef template StoreCondCompleteAcc {{ 4282292SN/A Fault %(class_name)s::completeAcc(Packet *pkt, 4292292SN/A %(CPU_exec_context)s *xc, 4302107SN/A Trace::InstRecord *traceData) const 4312292SN/A { 4322326SN/A Fault fault = NoFault; 4332292SN/A 4342107SN/A %(fp_enable_check)s; 4352292SN/A %(op_dest_decl)s; 4362935Sksewell@umich.edu 4374632Sgblack@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 4382935Sksewell@umich.edu 4392292SN/A if (fault == NoFault) { 4402292SN/A %(postacc_code)s; 4412292SN/A } 4422292SN/A 4432292SN/A if (fault == NoFault) { 4442107SN/A %(op_wb)s; 4452292SN/A } 4462107SN/A 4472292SN/A return fault; 4482292SN/A } 4492107SN/A}}; 4502702Sktlim@umich.edu 4512107SN/Adef template MiscExecute {{ 4522107SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 4532107SN/A Trace::InstRecord *traceData) const 4542107SN/A { 4556221Snate@binkert.org Addr EA M5_VAR_USED = 0; 4562292SN/A Fault fault = NoFault; 4577720Sgblack@eecs.umich.edu 4587720Sgblack@eecs.umich.edu %(fp_enable_check)s; 4592292SN/A %(op_decl)s; 4607852SMatt.Horsnell@arm.com %(op_rd)s; 4617852SMatt.Horsnell@arm.com %(ea_code)s; 4627852SMatt.Horsnell@arm.com 4637852SMatt.Horsnell@arm.com if (fault == NoFault) { 4647852SMatt.Horsnell@arm.com %(memacc_code)s; 4652935Sksewell@umich.edu } 4667852SMatt.Horsnell@arm.com 4677852SMatt.Horsnell@arm.com return NoFault; 4682292SN/A } 4697852SMatt.Horsnell@arm.com}}; 4707852SMatt.Horsnell@arm.com 4717852SMatt.Horsnell@arm.comdef template MiscInitiateAcc {{ 4722292SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4737852SMatt.Horsnell@arm.com Trace::InstRecord *traceData) const 4747852SMatt.Horsnell@arm.com { 4757852SMatt.Horsnell@arm.com panic("Misc instruction does not support split access method!"); 4762292SN/A return NoFault; 4772292SN/A } 4782292SN/A}}; 4792292SN/A 4806221Snate@binkert.org 4812292SN/Adef template MiscCompleteAcc {{ 4828513SGiacomo.Gabrielli@arm.com Fault %(class_name)s::completeAcc(Packet *pkt, 4838513SGiacomo.Gabrielli@arm.com %(CPU_exec_context)s *xc, 4848513SGiacomo.Gabrielli@arm.com Trace::InstRecord *traceData) const 4858513SGiacomo.Gabrielli@arm.com { 4868513SGiacomo.Gabrielli@arm.com panic("Misc instruction does not support split access method!"); 4878513SGiacomo.Gabrielli@arm.com 4888513SGiacomo.Gabrielli@arm.com return NoFault; 4898513SGiacomo.Gabrielli@arm.com } 4908513SGiacomo.Gabrielli@arm.com}}; 4918513SGiacomo.Gabrielli@arm.com 4928513SGiacomo.Gabrielli@arm.comdef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4932292SN/A mem_flags = [], inst_flags = []) {{ 4947852SMatt.Horsnell@arm.com (header_output, decoder_output, decode_block, exec_output) = \ 4958513SGiacomo.Gabrielli@arm.com LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4968137SAli.Saidi@ARM.com decode_template = ImmNopCheckDecode, 4972292SN/A exec_template_base = 'Load') 4988513SGiacomo.Gabrielli@arm.com}}; 4998513SGiacomo.Gabrielli@arm.com 5002292SN/A 5017852SMatt.Horsnell@arm.comdef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 5027852SMatt.Horsnell@arm.com mem_flags = [], inst_flags = []) {{ 5032292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5042292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5052292SN/A exec_template_base = 'Store') 5062292SN/A}}; 5076221Snate@binkert.org 5082292SN/Adef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5092292SN/A mem_flags = [], inst_flags = []) {{ 5107720Sgblack@eecs.umich.edu inst_flags += ['IsIndexed'] 5117852SMatt.Horsnell@arm.com (header_output, decoder_output, decode_block, exec_output) = \ 5127852SMatt.Horsnell@arm.com LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5137852SMatt.Horsnell@arm.com decode_template = ImmNopCheckDecode, 5142292SN/A exec_template_base = 'Load') 5157852SMatt.Horsnell@arm.com}}; 5167852SMatt.Horsnell@arm.com 5178137SAli.Saidi@ARM.comdef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5182292SN/A mem_flags = [], inst_flags = []) {{ 5197852SMatt.Horsnell@arm.com inst_flags += ['IsIndexed'] 5207852SMatt.Horsnell@arm.com (header_output, decoder_output, decode_block, exec_output) = \ 5212292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5227852SMatt.Horsnell@arm.com exec_template_base = 'Store') 5232292SN/A}}; 5247852SMatt.Horsnell@arm.com 5257852SMatt.Horsnell@arm.comdef format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5262292SN/A mem_flags = [], inst_flags = []) {{ 5272292SN/A inst_flags += ['IsIndexed', 'IsFloating'] 5282292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5292292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5306221Snate@binkert.org decode_template = ImmNopCheckDecode, 5312292SN/A exec_template_base = 'Load') 5322292SN/A}}; 5332292SN/A 5342292SN/Adef format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5352292SN/A mem_flags = [], inst_flags = []) {{ 5362292SN/A inst_flags += ['IsIndexed', 'IsFloating'] 5372292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5382292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5392292SN/A exec_template_base = 'Store') 5402292SN/A}}; 5412292SN/A 5422292SN/A 5432292SN/Adef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5442292SN/A mem_flags = [], inst_flags = []) {{ 5452292SN/A decl_code = 'uint32_t mem_word = Mem.uw;\n' 5462292SN/A decl_code += 'uint32_t unalign_addr = Rs + disp;\n' 5472292SN/A decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n' 5482292SN/A decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 5496221Snate@binkert.org decl_code += '\tbyte_offset ^= 3;\n' 5502292SN/A decl_code += '#endif\n' 5512292SN/A 5522292SN/A memacc_code = decl_code + memacc_code 5532292SN/A 5542292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5552292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5562292SN/A decode_template = ImmNopCheckDecode, 5572292SN/A exec_template_base = 'Load') 5582292SN/A}}; 5592292SN/A 5602292SN/Adef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5612292SN/A mem_flags = [], inst_flags = []) {{ 5622292SN/A decl_code = 'uint32_t mem_word = 0;\n' 5632292SN/A decl_code += 'uint32_t unaligned_addr = Rs + disp;\n' 5642292SN/A decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n' 5652292SN/A decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 5662292SN/A decl_code += '\tbyte_offset ^= 3;\n' 5671060SN/A decl_code += '#endif\n' 5681681SN/A decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n' 5691060SN/A #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);' 5701060SN/A memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 5712292SN/A 5722292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5732292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5742292SN/A exec_template_base = 'Store') 5752292SN/A}}; 5762292SN/A 5771681SN/Adef format Prefetch(ea_code = {{ EA = Rs + disp; }}, 5781681SN/A mem_flags = [], pf_flags = [], inst_flags = []) {{ 5791060SN/A pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 5802292SN/A pf_inst_flags = inst_flags 5811060SN/A 5822292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5832292SN/A LoadStoreBase(name, Name, ea_code, 5841060SN/A 'warn_once("Prefetching not implemented for MIPS\\n");', 5852292SN/A pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5862292SN/A 5872292SN/A}}; 5882292SN/A 5893221Sktlim@umich.edudef format StoreCond(memacc_code, postacc_code, 5903221Sktlim@umich.edu ea_code = {{ EA = Rs + disp; }}, 5913221Sktlim@umich.edu mem_flags = [], inst_flags = []) {{ 5923221Sktlim@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5933221Sktlim@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5942292SN/A postacc_code, exec_template_base = 'StoreCond') 5952292SN/A}}; 5962292SN/A