mem.isa revision 4056
17949SN/A// -*- mode:c++ -*- 27949SN/A 37949SN/A// Copyright (c) 2006 The Regents of The University of Michigan 47949SN/A// All rights reserved. 57949SN/A// 67949SN/A// Redistribution and use in source and binary forms, with or without 77949SN/A// modification, are permitted provided that the following conditions are 87949SN/A// met: redistributions of source code must retain the above copyright 97949SN/A// notice, this list of conditions and the following disclaimer; 107949SN/A// redistributions in binary form must reproduce the above copyright 117949SN/A// notice, this list of conditions and the following disclaimer in the 127949SN/A// documentation and/or other materials provided with the distribution; 137949SN/A// neither the name of the copyright holders nor the names of its 147949SN/A// contributors may be used to endorse or promote products derived from 157949SN/A// this software without specific prior written permission. 167949SN/A// 177949SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 187949SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 197949SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 207949SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 217949SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 227949SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 237949SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 247949SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 257949SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 267949SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 277949SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 287949SN/A// 297949SN/A// Authors: Steve Reinhardt 307949SN/A// Korey Sewell 317949SN/A 327949SN/A//////////////////////////////////////////////////////////////////// 337949SN/A// 347949SN/A// Memory-format instructions 357949SN/A// 367949SN/A 377949SN/Aoutput header {{ 387949SN/A /** 397949SN/A * Base class for general Mips memory-format instructions. 407949SN/A */ 419330Schander.sudanthi@arm.com class Memory : public MipsStaticInst 429330Schander.sudanthi@arm.com { 439338SAndreas.Sandberg@arm.com protected: 449330Schander.sudanthi@arm.com 459330Schander.sudanthi@arm.com /// Memory request flags. See mem_req_base.hh. 469330Schander.sudanthi@arm.com unsigned memAccessFlags; 477949SN/A /// Pointer to EAComp object. 489338SAndreas.Sandberg@arm.com const StaticInstPtr eaCompPtr; 497949SN/A /// Pointer to MemAcc object. 507949SN/A const StaticInstPtr memAccPtr; 51 52 /// Displacement for EA calculation (signed). 53 int32_t disp; 54 55 /// Constructor 56 Memory(const char *mnem, MachInst _machInst, OpClass __opClass, 57 StaticInstPtr _eaCompPtr = nullStaticInstPtr, 58 StaticInstPtr _memAccPtr = nullStaticInstPtr) 59 : MipsStaticInst(mnem, _machInst, __opClass), 60 memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), 61 disp(sext<16>(OFFSET)) 62 { 63 } 64 65 std::string 66 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 67 68 public: 69 70 const StaticInstPtr &eaCompInst() const { return eaCompPtr; } 71 const StaticInstPtr &memAccInst() const { return memAccPtr; } 72 }; 73 74 /** 75 * Base class for a few miscellaneous memory-format insts 76 * that don't interpret the disp field 77 */ 78 class MemoryNoDisp : public Memory 79 { 80 protected: 81 /// Constructor 82 MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 83 StaticInstPtr _eaCompPtr = nullStaticInstPtr, 84 StaticInstPtr _memAccPtr = nullStaticInstPtr) 85 : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr) 86 { 87 } 88 89 std::string 90 generateDisassembly(Addr pc, const SymbolTable *symtab) const; 91 }; 92}}; 93 94 95output decoder {{ 96 std::string 97 Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 98 { 99 return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 100 flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 101 } 102 103 std::string 104 MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 105 { 106 return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 107 flags[IsFloating] ? 'f' : 'r', 108 flags[IsFloating] ? FD : RD, 109 RS, RT); 110 } 111}}; 112 113def template LoadStoreDeclare {{ 114 /** 115 * Static instruction class for "%(mnemonic)s". 116 */ 117 class %(class_name)s : public %(base_class)s 118 { 119 protected: 120 121 /** 122 * "Fake" effective address computation class for "%(mnemonic)s". 123 */ 124 class EAComp : public %(base_class)s 125 { 126 public: 127 /// Constructor 128 EAComp(MachInst machInst); 129 130 %(BasicExecDeclare)s 131 }; 132 133 /** 134 * "Fake" memory access instruction class for "%(mnemonic)s". 135 */ 136 class MemAcc : public %(base_class)s 137 { 138 public: 139 /// Constructor 140 MemAcc(MachInst machInst); 141 142 %(BasicExecDeclare)s 143 }; 144 145 public: 146 147 /// Constructor. 148 %(class_name)s(MachInst machInst); 149 150 %(BasicExecDeclare)s 151 152 %(InitiateAccDeclare)s 153 154 %(CompleteAccDeclare)s 155 }; 156}}; 157 158 159def template InitiateAccDeclare {{ 160 Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 161}}; 162 163 164def template CompleteAccDeclare {{ 165 Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 166}}; 167 168 169def template EACompConstructor {{ 170 /** TODO: change op_class to AddrGenOp or something (requires 171 * creating new member of OpClass enum in op_class.hh, updating 172 * config files, etc.). */ 173 inline %(class_name)s::EAComp::EAComp(MachInst machInst) 174 : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) 175 { 176 %(constructor)s; 177 } 178}}; 179 180 181def template MemAccConstructor {{ 182 inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) 183 : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) 184 { 185 %(constructor)s; 186 } 187}}; 188 189 190def template LoadStoreConstructor {{ 191 inline %(class_name)s::%(class_name)s(MachInst machInst) 192 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 193 new EAComp(machInst), new MemAcc(machInst)) 194 { 195 %(constructor)s; 196 } 197}}; 198 199 200def template EACompExecute {{ 201 Fault 202 %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, 203 Trace::InstRecord *traceData) const 204 { 205 Addr EA; 206 Fault fault = NoFault; 207 208 %(fp_enable_check)s; 209 %(op_decl)s; 210 %(op_rd)s; 211 %(ea_code)s; 212 213 if (fault == NoFault) { 214 %(op_wb)s; 215 xc->setEA(EA); 216 } 217 218 return fault; 219 } 220}}; 221 222def template LoadMemAccExecute {{ 223 Fault 224 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 225 Trace::InstRecord *traceData) const 226 { 227 Addr EA; 228 Fault fault = NoFault; 229 230 %(fp_enable_check)s; 231 %(op_decl)s; 232 %(op_rd)s; 233 EA = xc->getEA(); 234 235 if (fault == NoFault) { 236 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 237 %(memacc_code)s; 238 } 239 240 if (fault == NoFault) { 241 %(op_wb)s; 242 } 243 244 return fault; 245 } 246}}; 247 248 249def template LoadExecute {{ 250 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 251 Trace::InstRecord *traceData) const 252 { 253 Addr EA; 254 Fault fault = NoFault; 255 256 %(fp_enable_check)s; 257 %(op_decl)s; 258 %(op_rd)s; 259 %(ea_code)s; 260 261 if (fault == NoFault) { 262 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 263 %(memacc_code)s; 264 } 265 266 if (fault == NoFault) { 267 %(op_wb)s; 268 } 269 270 return fault; 271 } 272}}; 273 274 275def template LoadInitiateAcc {{ 276 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 277 Trace::InstRecord *traceData) const 278 { 279 Addr EA; 280 Fault fault = NoFault; 281 282 %(fp_enable_check)s; 283 %(op_src_decl)s; 284 %(op_rd)s; 285 %(ea_code)s; 286 287 if (fault == NoFault) { 288 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 289 } 290 291 return fault; 292 } 293}}; 294 295 296def template LoadCompleteAcc {{ 297 Fault %(class_name)s::completeAcc(PacketPtr pkt, 298 %(CPU_exec_context)s *xc, 299 Trace::InstRecord *traceData) const 300 { 301 Fault fault = NoFault; 302 303 %(fp_enable_check)s; 304 %(op_decl)s; 305 306 Mem = pkt->get<typeof(Mem)>(); 307 308 if (fault == NoFault) { 309 %(memacc_code)s; 310 } 311 312 if (fault == NoFault) { 313 %(op_wb)s; 314 } 315 316 return fault; 317 } 318}}; 319 320 321def template StoreMemAccExecute {{ 322 Fault 323 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 324 Trace::InstRecord *traceData) const 325 { 326 Addr EA; 327 Fault fault = NoFault; 328 329 %(fp_enable_check)s; 330 %(op_decl)s; 331 %(op_rd)s; 332 EA = xc->getEA(); 333 334 if (fault == NoFault) { 335 %(memacc_code)s; 336 } 337 338 if (fault == NoFault) { 339 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 340 memAccessFlags, NULL); 341 if (traceData) { traceData->setData(Mem); } 342 } 343 344 if (fault == NoFault) { 345 %(postacc_code)s; 346 } 347 348 if (fault == NoFault) { 349 %(op_wb)s; 350 } 351 352 return fault; 353 } 354}}; 355 356def template StoreCondMemAccExecute {{ 357 Fault 358 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 359 Trace::InstRecord *traceData) const 360 { 361 Addr EA; 362 Fault fault = NoFault; 363 uint64_t write_result = 0; 364 365 %(fp_enable_check)s; 366 %(op_decl)s; 367 %(op_rd)s; 368 EA = xc->getEA(); 369 370 if (fault == NoFault) { 371 %(memacc_code)s; 372 } 373 374 if (fault == NoFault) { 375 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 376 memAccessFlags, &write_result); 377 if (traceData) { traceData->setData(Mem); } 378 } 379 380 if (fault == NoFault) { 381 %(postacc_code)s; 382 } 383 384 if (fault == NoFault) { 385 %(op_wb)s; 386 } 387 388 return fault; 389 } 390}}; 391 392 393def template StoreExecute {{ 394 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 395 Trace::InstRecord *traceData) const 396 { 397 Addr EA; 398 Fault fault = NoFault; 399 400 %(fp_enable_check)s; 401 %(op_decl)s; 402 %(op_rd)s; 403 %(ea_code)s; 404 405 if (fault == NoFault) { 406 %(memacc_code)s; 407 } 408 409 if (fault == NoFault) { 410 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 411 memAccessFlags, NULL); 412 if (traceData) { traceData->setData(Mem); } 413 } 414 415 if (fault == NoFault) { 416 %(postacc_code)s; 417 } 418 419 if (fault == NoFault) { 420 %(op_wb)s; 421 } 422 423 return fault; 424 } 425}}; 426 427def template StoreCondExecute {{ 428 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 429 Trace::InstRecord *traceData) const 430 { 431 Addr EA; 432 Fault fault = NoFault; 433 uint64_t write_result = 0; 434 435 %(fp_enable_check)s; 436 %(op_decl)s; 437 %(op_rd)s; 438 %(ea_code)s; 439 440 if (fault == NoFault) { 441 %(memacc_code)s; 442 } 443 444 if (fault == NoFault) { 445 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 446 memAccessFlags, &write_result); 447 if (traceData) { traceData->setData(Mem); } 448 } 449 450 if (fault == NoFault) { 451 %(postacc_code)s; 452 } 453 454 if (fault == NoFault) { 455 %(op_wb)s; 456 } 457 458 return fault; 459 } 460}}; 461 462def template StoreInitiateAcc {{ 463 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 464 Trace::InstRecord *traceData) const 465 { 466 Addr EA; 467 Fault fault = NoFault; 468 469 %(fp_enable_check)s; 470 %(op_decl)s; 471 %(op_rd)s; 472 %(ea_code)s; 473 474 if (fault == NoFault) { 475 %(memacc_code)s; 476 } 477 478 if (fault == NoFault) { 479 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 480 memAccessFlags, NULL); 481 if (traceData) { traceData->setData(Mem); } 482 } 483 484 return fault; 485 } 486}}; 487 488 489def template StoreCompleteAcc {{ 490 Fault %(class_name)s::completeAcc(PacketPtr pkt, 491 %(CPU_exec_context)s *xc, 492 Trace::InstRecord *traceData) const 493 { 494 Fault fault = NoFault; 495 496 %(fp_enable_check)s; 497 %(op_dest_decl)s; 498 499 if (fault == NoFault) { 500 %(postacc_code)s; 501 } 502 503 if (fault == NoFault) { 504 %(op_wb)s; 505 } 506 507 return fault; 508 } 509}}; 510 511def template StoreCondCompleteAcc {{ 512 Fault %(class_name)s::completeAcc(PacketPtr pkt, 513 %(CPU_exec_context)s *xc, 514 Trace::InstRecord *traceData) const 515 { 516 Fault fault = NoFault; 517 518 %(fp_enable_check)s; 519 %(op_dest_decl)s; 520 521 uint64_t write_result = pkt->req->getExtraData(); 522 523 if (fault == NoFault) { 524 %(postacc_code)s; 525 } 526 527 if (fault == NoFault) { 528 %(op_wb)s; 529 } 530 531 return fault; 532 } 533}}; 534 535 536def template MiscMemAccExecute {{ 537 Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 538 Trace::InstRecord *traceData) const 539 { 540 Addr EA; 541 Fault fault = NoFault; 542 543 %(fp_enable_check)s; 544 %(op_decl)s; 545 %(op_rd)s; 546 EA = xc->getEA(); 547 548 if (fault == NoFault) { 549 %(memacc_code)s; 550 } 551 552 return NoFault; 553 } 554}}; 555 556def template MiscExecute {{ 557 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 558 Trace::InstRecord *traceData) const 559 { 560 Addr EA; 561 Fault fault = NoFault; 562 563 %(fp_enable_check)s; 564 %(op_decl)s; 565 %(op_rd)s; 566 %(ea_code)s; 567 568 if (fault == NoFault) { 569 %(memacc_code)s; 570 } 571 572 return NoFault; 573 } 574}}; 575 576def template MiscInitiateAcc {{ 577 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 578 Trace::InstRecord *traceData) const 579 { 580 panic("Misc instruction does not support split access method!"); 581 return NoFault; 582 } 583}}; 584 585 586def template MiscCompleteAcc {{ 587 Fault %(class_name)s::completeAcc(PacketPtr pkt, 588 %(CPU_exec_context)s *xc, 589 Trace::InstRecord *traceData) const 590 { 591 panic("Misc instruction does not support split access method!"); 592 593 return NoFault; 594 } 595}}; 596 597def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 598 mem_flags = [], inst_flags = []) {{ 599 (header_output, decoder_output, decode_block, exec_output) = \ 600 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 601 decode_template = ImmNopCheckDecode, 602 exec_template_base = 'Load') 603}}; 604 605def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 606 mem_flags = [], inst_flags = []) {{ 607 (header_output, decoder_output, decode_block, exec_output) = \ 608 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 609 exec_template_base = 'Store') 610}}; 611 612def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 613 mem_flags = [], inst_flags = []) {{ 614 (header_output, decoder_output, decode_block, exec_output) = \ 615 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 616 decode_template = ImmNopCheckDecode, 617 exec_template_base = 'Load') 618}}; 619 620def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 621 mem_flags = [], inst_flags = []) {{ 622 (header_output, decoder_output, decode_block, exec_output) = \ 623 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 624 exec_template_base = 'Store') 625}}; 626 627def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 628 mem_flags = [], inst_flags = []) {{ 629 decl_code = 'uint32_t mem_word = Mem.uw;\n' 630 decl_code += 'uint32_t unalign_addr = Rs + disp;\n' 631 decl_code += 'uint32_t byte_offset = unalign_addr & 3;\n' 632 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 633 decl_code += '\tbyte_offset ^= 3;\n' 634 decl_code += '#endif\n' 635 636 memacc_code = decl_code + memacc_code 637 638 (header_output, decoder_output, decode_block, exec_output) = \ 639 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 640 decode_template = ImmNopCheckDecode, 641 exec_template_base = 'Load') 642}}; 643 644def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 645 mem_flags = [], inst_flags = []) {{ 646 decl_code = 'uint32_t mem_word = 0;\n' 647 decl_code += 'uint32_t unaligned_addr = Rs + disp;\n' 648 decl_code += 'uint32_t byte_offset = unaligned_addr & 3;\n' 649 decl_code += '#if BYTE_ORDER == BIG_ENDIAN\n' 650 decl_code += '\tbyte_offset ^= 3;\n' 651 decl_code += '#endif\n' 652 decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n' 653 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 654 655 (header_output, decoder_output, decode_block, exec_output) = \ 656 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 657 exec_template_base = 'Store') 658}}; 659 660def format Prefetch(ea_code = {{ EA = Rs + disp; }}, 661 mem_flags = [], pf_flags = [], inst_flags = []) {{ 662 pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT'] 663 pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 664 'IsDataPrefetch', 'MemReadOp'] 665 666 (header_output, decoder_output, decode_block, exec_output) = \ 667 LoadStoreBase(name, Name, ea_code, 668 'xc->prefetch(EA, memAccessFlags);', 669 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 670 671}}; 672 673def format StoreCond(memacc_code, postacc_code, 674 ea_code = {{ EA = Rs + disp; }}, 675 mem_flags = [], inst_flags = []) {{ 676 (header_output, decoder_output, decode_block, exec_output) = \ 677 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 678 postacc_code, exec_template_base = 'StoreCond') 679}}; 680