mem.isa revision 2506
18706Sandreas.hansson@arm.com// -*- mode:c++ -*- 28706Sandreas.hansson@arm.com 38706Sandreas.hansson@arm.com// Copyright (c) 2003-2005 The Regents of The University of Michigan 48706Sandreas.hansson@arm.com// All rights reserved. 58706Sandreas.hansson@arm.com// 68706Sandreas.hansson@arm.com// Redistribution and use in source and binary forms, with or without 78706Sandreas.hansson@arm.com// modification, are permitted provided that the following conditions are 88706Sandreas.hansson@arm.com// met: redistributions of source code must retain the above copyright 98706Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer; 108706Sandreas.hansson@arm.com// redistributions in binary form must reproduce the above copyright 118706Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer in the 128706Sandreas.hansson@arm.com// documentation and/or other materials provided with the distribution; 136892SBrad.Beckmann@amd.com// neither the name of the copyright holders nor the names of its 146892SBrad.Beckmann@amd.com// contributors may be used to endorse or promote products derived from 156892SBrad.Beckmann@amd.com// this software without specific prior written permission. 166892SBrad.Beckmann@amd.com// 176892SBrad.Beckmann@amd.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186892SBrad.Beckmann@amd.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196892SBrad.Beckmann@amd.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206892SBrad.Beckmann@amd.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216892SBrad.Beckmann@amd.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226892SBrad.Beckmann@amd.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236892SBrad.Beckmann@amd.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246892SBrad.Beckmann@amd.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256892SBrad.Beckmann@amd.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266892SBrad.Beckmann@amd.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276892SBrad.Beckmann@amd.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286892SBrad.Beckmann@amd.com 296892SBrad.Beckmann@amd.comoutput header {{ 306892SBrad.Beckmann@amd.com /** 316892SBrad.Beckmann@amd.com * Base class for general Mips memory-format instructions. 326892SBrad.Beckmann@amd.com */ 336892SBrad.Beckmann@amd.com class Memory : public MipsStaticInst 346892SBrad.Beckmann@amd.com { 356892SBrad.Beckmann@amd.com protected: 366892SBrad.Beckmann@amd.com 376892SBrad.Beckmann@amd.com /// Memory request flags. See mem_req_base.hh. 386892SBrad.Beckmann@amd.com unsigned memAccessFlags; 396892SBrad.Beckmann@amd.com /// Pointer to EAComp object. 406892SBrad.Beckmann@amd.com const StaticInstPtr eaCompPtr; 416892SBrad.Beckmann@amd.com /// Pointer to MemAcc object. 427563SBrad.Beckmann@amd.com const StaticInstPtr memAccPtr; 436892SBrad.Beckmann@amd.com 446892SBrad.Beckmann@amd.com /// Displacement for EA calculation (signed). 456892SBrad.Beckmann@amd.com int32_t disp; 4610118Snilay@cs.wisc.edu 4710118Snilay@cs.wisc.edu /// Constructor 4811682Sandreas.hansson@arm.com Memory(const char *mnem, MachInst _machInst, OpClass __opClass, 4911662Stushar@ece.gatech.edu StaticInstPtr _eaCompPtr = nullStaticInstPtr, 5011670Sandreas.hansson@arm.com StaticInstPtr _memAccPtr = nullStaticInstPtr) 5111670Sandreas.hansson@arm.com : MipsStaticInst(mnem, _machInst, __opClass), 526892SBrad.Beckmann@amd.com memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), 537538SBrad.Beckmann@amd.com disp(OFFSET) 548939SBrad.Beckmann@amd.com { 558939SBrad.Beckmann@amd.com //If Bit 15 is 1 then Sign Extend 568939SBrad.Beckmann@amd.com int32_t temp = disp & 0x00008000; 579791Sakash.bagdia@arm.com 589791Sakash.bagdia@arm.com if (temp > 0) { 599791Sakash.bagdia@arm.com disp |= 0xFFFF0000; 609791Sakash.bagdia@arm.com } 6110525Snilay@cs.wisc.edu } 6210525Snilay@cs.wisc.edu 6310525Snilay@cs.wisc.edu std::string 649841Snilay@cs.wisc.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 659841Snilay@cs.wisc.edu 669841Snilay@cs.wisc.edu public: 679841Snilay@cs.wisc.edu 689841Snilay@cs.wisc.edu const StaticInstPtr &eaCompInst() const { return eaCompPtr; } 6911662Stushar@ece.gatech.edu const StaticInstPtr &memAccInst() const { return memAccPtr; } 707538SBrad.Beckmann@amd.com }; 717538SBrad.Beckmann@amd.com 727917SBrad.Beckmann@amd.com}}; 737563SBrad.Beckmann@amd.com 747563SBrad.Beckmann@amd.com 757538SBrad.Beckmann@amd.comoutput decoder {{ 767566SBrad.Beckmann@amd.com std::string 777566SBrad.Beckmann@amd.com Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 787809Snilay@cs.wisc.edu { 797538SBrad.Beckmann@amd.com return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 807538SBrad.Beckmann@amd.com flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 817538SBrad.Beckmann@amd.com } 8211670Sandreas.hansson@arm.com 837538SBrad.Beckmann@amd.com}}; 8410524Snilay@cs.wisc.edu 8510524Snilay@cs.wisc.edudef format LoadAddress(code) {{ 8610524Snilay@cs.wisc.edu iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code)) 8710524Snilay@cs.wisc.edu header_output = BasicDeclare.subst(iop) 8810524Snilay@cs.wisc.edu decoder_output = BasicConstructor.subst(iop) 8910524Snilay@cs.wisc.edu decode_block = BasicDecode.subst(iop) 9010524Snilay@cs.wisc.edu exec_output = BasicExecute.subst(iop) 9110524Snilay@cs.wisc.edu}}; 9210524Snilay@cs.wisc.edu 9310524Snilay@cs.wisc.edu 9410524Snilay@cs.wisc.edudef template LoadStoreDeclare {{ 9510524Snilay@cs.wisc.edu /** 9610524Snilay@cs.wisc.edu * Static instruction class for "%(mnemonic)s". 9710524Snilay@cs.wisc.edu */ 9810524Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 9910524Snilay@cs.wisc.edu { 10010524Snilay@cs.wisc.edu protected: 10110524Snilay@cs.wisc.edu 10210524Snilay@cs.wisc.edu /** 10310524Snilay@cs.wisc.edu * "Fake" effective address computation class for "%(mnemonic)s". 10410524Snilay@cs.wisc.edu */ 10510524Snilay@cs.wisc.edu class EAComp : public %(base_class)s 10610524Snilay@cs.wisc.edu { 10710524Snilay@cs.wisc.edu public: 10810524Snilay@cs.wisc.edu /// Constructor 10910524Snilay@cs.wisc.edu EAComp(MachInst machInst); 11010524Snilay@cs.wisc.edu 11110720Sandreas.hansson@arm.com %(BasicExecDeclare)s 11210524Snilay@cs.wisc.edu }; 11310524Snilay@cs.wisc.edu 11410524Snilay@cs.wisc.edu /** 11510524Snilay@cs.wisc.edu * "Fake" memory access instruction class for "%(mnemonic)s". 11610524Snilay@cs.wisc.edu */ 11710524Snilay@cs.wisc.edu class MemAcc : public %(base_class)s 11810524Snilay@cs.wisc.edu { 11910524Snilay@cs.wisc.edu public: 12011616Sdavid.j.hashe@gmail.com /// Constructor 12111616Sdavid.j.hashe@gmail.com MemAcc(MachInst machInst); 12211616Sdavid.j.hashe@gmail.com 12310524Snilay@cs.wisc.edu %(BasicExecDeclare)s 12410524Snilay@cs.wisc.edu }; 12510524Snilay@cs.wisc.edu 12610524Snilay@cs.wisc.edu public: 12710524Snilay@cs.wisc.edu 12810524Snilay@cs.wisc.edu /// Constructor. 12910524Snilay@cs.wisc.edu %(class_name)s(MachInst machInst); 13010524Snilay@cs.wisc.edu 13110524Snilay@cs.wisc.edu %(BasicExecDeclare)s 13210524Snilay@cs.wisc.edu 13310524Snilay@cs.wisc.edu %(InitiateAccDeclare)s 13410524Snilay@cs.wisc.edu 13510524Snilay@cs.wisc.edu %(CompleteAccDeclare)s 13610524Snilay@cs.wisc.edu }; 13710524Snilay@cs.wisc.edu}}; 1389100SBrad.Beckmann@amd.com 1399100SBrad.Beckmann@amd.com 1409100SBrad.Beckmann@amd.comdef template InitiateAccDeclare {{ 1419100SBrad.Beckmann@amd.com Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1429100SBrad.Beckmann@amd.com}}; 1439100SBrad.Beckmann@amd.com 14411670Sandreas.hansson@arm.com 1459100SBrad.Beckmann@amd.comdef template CompleteAccDeclare {{ 1469100SBrad.Beckmann@amd.com Fault completeAcc(uint8_t *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1479100SBrad.Beckmann@amd.com}}; 14810519Snilay@cs.wisc.edu 1496892SBrad.Beckmann@amd.com 15010524Snilay@cs.wisc.edudef template LoadStoreConstructor {{ 1518436SBrad.Beckmann@amd.com /** TODO: change op_class to AddrGenOp or something (requires 1528436SBrad.Beckmann@amd.com * creating new member of OpClass enum in op_class.hh, updating 15311662Stushar@ece.gatech.edu * config files, etc.). */ 15411662Stushar@ece.gatech.edu inline %(class_name)s::EAComp::EAComp(MachInst machInst) 15511662Stushar@ece.gatech.edu : %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp) 15610311Snilay@cs.wisc.edu { 15710311Snilay@cs.wisc.edu %(ea_constructor)s; 15810551Ssteve.reinhardt@amd.com } 15910551Ssteve.reinhardt@amd.com 16010311Snilay@cs.wisc.edu inline %(class_name)s::MemAcc::MemAcc(MachInst machInst) 16110311Snilay@cs.wisc.edu : %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s) 16210551Ssteve.reinhardt@amd.com { 16310551Ssteve.reinhardt@amd.com %(memacc_constructor)s; 16410551Ssteve.reinhardt@amd.com } 16510311Snilay@cs.wisc.edu 16610551Ssteve.reinhardt@amd.com inline %(class_name)s::%(class_name)s(MachInst machInst) 16710311Snilay@cs.wisc.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 16810311Snilay@cs.wisc.edu new EAComp(machInst), new MemAcc(machInst)) 16911662Stushar@ece.gatech.edu { 17011662Stushar@ece.gatech.edu %(constructor)s; 17111662Stushar@ece.gatech.edu } 17211662Stushar@ece.gatech.edu}}; 17311662Stushar@ece.gatech.edu 17411662Stushar@ece.gatech.edu 17511662Stushar@ece.gatech.edudef template EACompExecute {{ 17610311Snilay@cs.wisc.edu Fault 17710311Snilay@cs.wisc.edu %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc, 17810311Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 17910311Snilay@cs.wisc.edu { 18011596Sandreas.sandberg@arm.com Addr EA; 18111596Sandreas.sandberg@arm.com Fault fault = NoFault; 18210311Snilay@cs.wisc.edu 18310311Snilay@cs.wisc.edu %(fp_enable_check)s; 18410311Snilay@cs.wisc.edu %(op_decl)s; 18510311Snilay@cs.wisc.edu %(op_rd)s; 18610311Snilay@cs.wisc.edu %(code)s; 18710311Snilay@cs.wisc.edu 18810311Snilay@cs.wisc.edu if (fault == NoFault) { 1899148Spowerjg@cs.wisc.edu %(op_wb)s; 19010524Snilay@cs.wisc.edu xc->setEA(EA); 19110116Snilay@cs.wisc.edu } 19210116Snilay@cs.wisc.edu 19310116Snilay@cs.wisc.edu return fault; 19410116Snilay@cs.wisc.edu } 19510116Snilay@cs.wisc.edu}}; 19610116Snilay@cs.wisc.edu 19710116Snilay@cs.wisc.edudef template LoadMemAccExecute {{ 19810116Snilay@cs.wisc.edu Fault 19910116Snilay@cs.wisc.edu %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 20010116Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 20111172Snilay@cs.wisc.edu { 20210120Snilay@cs.wisc.edu Addr EA; 20310012Snilay@cs.wisc.edu Fault fault = NoFault; 20410525Snilay@cs.wisc.edu 20510630Snilay@cs.wisc.edu %(fp_enable_check)s; 20610630Snilay@cs.wisc.edu %(op_decl)s; 20710706Spower.jg@gmail.com %(op_rd)s; 20810706Spower.jg@gmail.com EA = xc->getEA(); 20910630Snilay@cs.wisc.edu 21010630Snilay@cs.wisc.edu if (fault == NoFault) { 21110529Smorr@cs.wisc.edu fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 21210529Smorr@cs.wisc.edu %(code)s; 21310529Smorr@cs.wisc.edu } 21410529Smorr@cs.wisc.edu 21510529Smorr@cs.wisc.edu if (fault == NoFault) { 21610529Smorr@cs.wisc.edu %(op_wb)s; 21710529Smorr@cs.wisc.edu } 218 219 return fault; 220 } 221}}; 222 223 224def template LoadExecute {{ 225 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 226 Trace::InstRecord *traceData) const 227 { 228 Addr EA; 229 Fault fault = NoFault; 230 231 %(fp_enable_check)s; 232 %(op_decl)s; 233 %(op_rd)s; 234 %(ea_code)s; 235 236 if (fault == NoFault) { 237 fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags); 238 %(memacc_code)s; 239 } 240 241 if (fault == NoFault) { 242 %(op_wb)s; 243 } 244 245 return fault; 246 } 247}}; 248 249 250def template LoadInitiateAcc {{ 251 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 252 Trace::InstRecord *traceData) const 253 { 254 Addr EA; 255 Fault fault = NoFault; 256 257 %(fp_enable_check)s; 258 %(op_src_decl)s; 259 %(op_rd)s; 260 %(ea_code)s; 261 262 if (fault == NoFault) { 263 fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags); 264 } 265 266 return fault; 267 } 268}}; 269 270 271def template LoadCompleteAcc {{ 272 Fault %(class_name)s::completeAcc(uint8_t *data, 273 %(CPU_exec_context)s *xc, 274 Trace::InstRecord *traceData) const 275 { 276 Fault fault = NoFault; 277 278 %(fp_enable_check)s; 279 %(op_decl)s; 280 281 memcpy(&Mem, data, sizeof(Mem)); 282 283 if (fault == NoFault) { 284 %(memacc_code)s; 285 } 286 287 if (fault == NoFault) { 288 %(op_wb)s; 289 } 290 291 return fault; 292 } 293}}; 294 295 296def template StoreMemAccExecute {{ 297 Fault 298 %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc, 299 Trace::InstRecord *traceData) const 300 { 301 Addr EA; 302 Fault fault = NoFault; 303 uint64_t write_result = 0; 304 305 %(fp_enable_check)s; 306 %(op_decl)s; 307 %(op_rd)s; 308 EA = xc->getEA(); 309 310 if (fault == NoFault) { 311 %(code)s; 312 } 313 314 if (fault == NoFault) { 315 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 316 memAccessFlags, &write_result); 317 if (traceData) { traceData->setData(Mem); } 318 } 319 320 if (fault == NoFault) { 321 %(postacc_code)s; 322 } 323 324 if (fault == NoFault) { 325 %(op_wb)s; 326 } 327 328 return fault; 329 } 330}}; 331 332 333def template StoreExecute {{ 334 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 335 Trace::InstRecord *traceData) const 336 { 337 Addr EA; 338 Fault fault = NoFault; 339 uint64_t write_result = 0; 340 341 %(fp_enable_check)s; 342 %(op_decl)s; 343 %(op_rd)s; 344 %(ea_code)s; 345 346 if (fault == NoFault) { 347 %(memacc_code)s; 348 } 349 350 if (fault == NoFault) { 351 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 352 memAccessFlags, &write_result); 353 if (traceData) { traceData->setData(Mem); } 354 } 355 356 if (fault == NoFault) { 357 %(postacc_code)s; 358 } 359 360 if (fault == NoFault) { 361 %(op_wb)s; 362 } 363 364 return fault; 365 } 366}}; 367 368def template StoreInitiateAcc {{ 369 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 370 Trace::InstRecord *traceData) const 371 { 372 Addr EA; 373 Fault fault = NoFault; 374 uint64_t write_result = 0; 375 376 %(fp_enable_check)s; 377 %(op_decl)s; 378 %(op_rd)s; 379 %(ea_code)s; 380 381 if (fault == NoFault) { 382 %(memacc_code)s; 383 } 384 385 if (fault == NoFault) { 386 fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, 387 memAccessFlags, &write_result); 388 if (traceData) { traceData->setData(Mem); } 389 } 390 391 return fault; 392 } 393}}; 394 395 396def template StoreCompleteAcc {{ 397 Fault %(class_name)s::completeAcc(uint8_t *data, 398 %(CPU_exec_context)s *xc, 399 Trace::InstRecord *traceData) const 400 { 401 Fault fault = NoFault; 402 uint64_t write_result = 0; 403 404 %(fp_enable_check)s; 405 %(op_dest_decl)s; 406 407 memcpy(&write_result, data, sizeof(write_result)); 408 409 if (fault == NoFault) { 410 %(postacc_code)s; 411 } 412 413 if (fault == NoFault) { 414 %(op_wb)s; 415 } 416 417 return fault; 418 } 419}}; 420 421// load instructions use Rt as dest, so check for 422// Rt == 31 to detect nops 423def template LoadNopCheckDecode {{ 424 { 425 MipsStaticInst *i = new %(class_name)s(machInst); 426 if (RT == 0) { 427 i = makeNop(i); 428 } 429 return i; 430 } 431}}; 432 433def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 434 mem_flags = [], inst_flags = []) {{ 435 (header_output, decoder_output, decode_block, exec_output) = \ 436 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 437 decode_template = LoadNopCheckDecode, 438 exec_template_base = 'Load') 439}}; 440 441 442def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 443 mem_flags = [], inst_flags = []) {{ 444 (header_output, decoder_output, decode_block, exec_output) = \ 445 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 446 exec_template_base = 'Store') 447}}; 448 449//FP loads are offloaded to these formats for now ... 450def format LoadMemory2(ea_code = {{ EA = Rs + disp; }}, memacc_code = {{ }}, 451 mem_flags = [], inst_flags = []) {{ 452 (header_output, decoder_output, decode_block, exec_output) = \ 453 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 454 decode_template = LoadNopCheckDecode, 455 exec_template_base = 'Load') 456}}; 457 458 459//FP stores are offloaded to these formats for now ... 460def format StoreMemory2(ea_code = {{ EA = Rs + disp; }},memacc_code = {{ }}, 461 mem_flags = [], inst_flags = []) {{ 462 (header_output, decoder_output, decode_block, exec_output) = \ 463 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 464 decode_template = LoadNopCheckDecode, 465 exec_template_base = 'Store') 466}}; 467 468