mem.isa revision 12616
18706Sandreas.hansson@arm.com// -*- mode:c++ -*- 28706Sandreas.hansson@arm.com 38706Sandreas.hansson@arm.com// Copyright (c) 2007 MIPS Technologies, Inc. 48706Sandreas.hansson@arm.com// All rights reserved. 58706Sandreas.hansson@arm.com// 68706Sandreas.hansson@arm.com// Redistribution and use in source and binary forms, with or without 78706Sandreas.hansson@arm.com// modification, are permitted provided that the following conditions are 88706Sandreas.hansson@arm.com// met: redistributions of source code must retain the above copyright 98706Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer; 108706Sandreas.hansson@arm.com// redistributions in binary form must reproduce the above copyright 118706Sandreas.hansson@arm.com// notice, this list of conditions and the following disclaimer in the 128706Sandreas.hansson@arm.com// documentation and/or other materials provided with the distribution; 136892SBrad.Beckmann@amd.com// neither the name of the copyright holders nor the names of its 146892SBrad.Beckmann@amd.com// contributors may be used to endorse or promote products derived from 156892SBrad.Beckmann@amd.com// this software without specific prior written permission. 166892SBrad.Beckmann@amd.com// 176892SBrad.Beckmann@amd.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186892SBrad.Beckmann@amd.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196892SBrad.Beckmann@amd.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206892SBrad.Beckmann@amd.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216892SBrad.Beckmann@amd.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226892SBrad.Beckmann@amd.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236892SBrad.Beckmann@amd.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246892SBrad.Beckmann@amd.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256892SBrad.Beckmann@amd.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266892SBrad.Beckmann@amd.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276892SBrad.Beckmann@amd.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286892SBrad.Beckmann@amd.com// 296892SBrad.Beckmann@amd.com// Authors: Steve Reinhardt 306892SBrad.Beckmann@amd.com// Korey Sewell 316892SBrad.Beckmann@amd.com 326892SBrad.Beckmann@amd.com//////////////////////////////////////////////////////////////////// 336892SBrad.Beckmann@amd.com// 346892SBrad.Beckmann@amd.com// Memory-format instructions 356892SBrad.Beckmann@amd.com// 366892SBrad.Beckmann@amd.com 376892SBrad.Beckmann@amd.comoutput header {{ 386892SBrad.Beckmann@amd.com /** 396892SBrad.Beckmann@amd.com * Base class for general Mips memory-format instructions. 406892SBrad.Beckmann@amd.com */ 416892SBrad.Beckmann@amd.com class Memory : public MipsStaticInst 427563SBrad.Beckmann@amd.com { 436892SBrad.Beckmann@amd.com protected: 446892SBrad.Beckmann@amd.com /// Memory request flags. See mem_req_base.hh. 456892SBrad.Beckmann@amd.com Request::Flags memAccessFlags; 466892SBrad.Beckmann@amd.com 477538SBrad.Beckmann@amd.com /// Displacement for EA calculation (signed). 488939SBrad.Beckmann@amd.com int32_t disp; 498939SBrad.Beckmann@amd.com 508939SBrad.Beckmann@amd.com /// Constructor 517538SBrad.Beckmann@amd.com Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 527538SBrad.Beckmann@amd.com : MipsStaticInst(mnem, _machInst, __opClass), 537538SBrad.Beckmann@amd.com disp(sext<16>(OFFSET)) 547538SBrad.Beckmann@amd.com { 557538SBrad.Beckmann@amd.com } 567661Snate@binkert.org 577538SBrad.Beckmann@amd.com std::string generateDisassembly( 588612Stushar@csail.mit.edu Addr pc, const SymbolTable *symtab) const override; 598612Stushar@csail.mit.edu }; 607538SBrad.Beckmann@amd.com 617538SBrad.Beckmann@amd.com /** 627917SBrad.Beckmann@amd.com * Base class for a few miscellaneous memory-format insts 637563SBrad.Beckmann@amd.com * that don't interpret the disp field 647563SBrad.Beckmann@amd.com */ 657538SBrad.Beckmann@amd.com class MemoryNoDisp : public Memory 667538SBrad.Beckmann@amd.com { 677538SBrad.Beckmann@amd.com protected: 687538SBrad.Beckmann@amd.com /// Constructor 697538SBrad.Beckmann@amd.com MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 707566SBrad.Beckmann@amd.com : Memory(mnem, _machInst, __opClass) 717566SBrad.Beckmann@amd.com { 727809Snilay@cs.wisc.edu } 737809Snilay@cs.wisc.edu 747809Snilay@cs.wisc.edu std::string generateDisassembly( 757809Snilay@cs.wisc.edu Addr pc, const SymbolTable *symtab) const override; 768638Sgloh }; 778638Sgloh}}; 787538SBrad.Beckmann@amd.com 797538SBrad.Beckmann@amd.com 807538SBrad.Beckmann@amd.comoutput decoder {{ 817538SBrad.Beckmann@amd.com std::string 829100SBrad.Beckmann@amd.com Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 839100SBrad.Beckmann@amd.com { 849100SBrad.Beckmann@amd.com return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 859100SBrad.Beckmann@amd.com flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 869100SBrad.Beckmann@amd.com } 879100SBrad.Beckmann@amd.com 889100SBrad.Beckmann@amd.com std::string 899100SBrad.Beckmann@amd.com MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 909100SBrad.Beckmann@amd.com { 919100SBrad.Beckmann@amd.com return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 928929Snilay@cs.wisc.edu flags[IsFloating] ? 'f' : 'r', 936892SBrad.Beckmann@amd.com flags[IsFloating] ? FD : RD, 948638Sgloh RS, RT); 958690Snilay@cs.wisc.edu } 968690Snilay@cs.wisc.edu 978436SBrad.Beckmann@amd.com}}; 988436SBrad.Beckmann@amd.com 997032SBrad.Beckmann@amd.comoutput header {{ 1007032SBrad.Beckmann@amd.com uint64_t getMemData(ExecContext *xc, Packet *packet); 1016923SBrad.Beckmann@amd.com 1029100SBrad.Beckmann@amd.com}}; 1038929Snilay@cs.wisc.edu 1047557SBrad.Beckmann@amd.comoutput exec {{ 1056923SBrad.Beckmann@amd.com /** return data in cases where there the size of data is only 1066923SBrad.Beckmann@amd.com known in the packet 1077557SBrad.Beckmann@amd.com */ 1088257SBrad.Beckmann@amd.com uint64_t getMemData(ExecContext *xc, Packet *packet) { 1098706Sandreas.hansson@arm.com switch (packet->getSize()) 1108706Sandreas.hansson@arm.com { 1118706Sandreas.hansson@arm.com case 1: 1128923Sandreas.hansson@arm.com return packet->get<uint8_t>(); 1138706Sandreas.hansson@arm.com 1148706Sandreas.hansson@arm.com case 2: 1158706Sandreas.hansson@arm.com return packet->get<uint16_t>(); 1168706Sandreas.hansson@arm.com 1178732Sandreas.hansson@arm.com case 4: 1188839Sandreas.hansson@arm.com return packet->get<uint32_t>(); 1198732Sandreas.hansson@arm.com 1208732Sandreas.hansson@arm.com case 8: 1218257SBrad.Beckmann@amd.com return packet->get<uint64_t>(); 1228257SBrad.Beckmann@amd.com 1238257SBrad.Beckmann@amd.com default: 1248257SBrad.Beckmann@amd.com std::cerr << "bad store data size = " << packet->getSize() << std::endl; 1258257SBrad.Beckmann@amd.com 1268257SBrad.Beckmann@amd.com assert(0); 1278257SBrad.Beckmann@amd.com return 0; 1288257SBrad.Beckmann@amd.com } 1298257SBrad.Beckmann@amd.com } 1308257SBrad.Beckmann@amd.com 1318257SBrad.Beckmann@amd.com 1328257SBrad.Beckmann@amd.com}}; 1338257SBrad.Beckmann@amd.com 1348257SBrad.Beckmann@amd.comdef template LoadStoreDeclare {{ 1358257SBrad.Beckmann@amd.com /** 1368258SBrad.Beckmann@amd.com * Static instruction class for "%(mnemonic)s". 1378258SBrad.Beckmann@amd.com */ 1388257SBrad.Beckmann@amd.com class %(class_name)s : public %(base_class)s 1398257SBrad.Beckmann@amd.com { 1406892SBrad.Beckmann@amd.com public: 1419100SBrad.Beckmann@amd.com 1429100SBrad.Beckmann@amd.com /// Constructor. 1439100SBrad.Beckmann@amd.com %(class_name)s(ExtMachInst machInst); 1446892SBrad.Beckmann@amd.com 1459100SBrad.Beckmann@amd.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 1467032SBrad.Beckmann@amd.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 1479100SBrad.Beckmann@amd.com Fault completeAcc(Packet *, ExecContext *, 1489100SBrad.Beckmann@amd.com Trace::InstRecord *) const override; 1499100SBrad.Beckmann@amd.com }; 1507032SBrad.Beckmann@amd.com}}; 1519100SBrad.Beckmann@amd.com 1527557SBrad.Beckmann@amd.com 1538257SBrad.Beckmann@amd.comdef template LoadStoreConstructor {{ 1548612Stushar@csail.mit.edu %(class_name)s::%(class_name)s(ExtMachInst machInst) 1558612Stushar@csail.mit.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1568612Stushar@csail.mit.edu { 1578612Stushar@csail.mit.edu %(constructor)s; 1588612Stushar@csail.mit.edu } 1598612Stushar@csail.mit.edu}}; 1608612Stushar@csail.mit.edu 1616892SBrad.Beckmann@amd.comdef template LoadExecute {{ 1626903SBrad.Beckmann@amd.com Fault %(class_name)s::execute(ExecContext *xc, 1637563SBrad.Beckmann@amd.com Trace::InstRecord *traceData) const 1647025SBrad.Beckmann@amd.com { 1657025SBrad.Beckmann@amd.com Addr EA; 1667025SBrad.Beckmann@amd.com Fault fault = NoFault; 1677025SBrad.Beckmann@amd.com 1687563SBrad.Beckmann@amd.com if (this->isFloating()) { 1696903SBrad.Beckmann@amd.com %(fp_enable_check)s; 1706903SBrad.Beckmann@amd.com 1717563SBrad.Beckmann@amd.com if(fault != NoFault) 1727563SBrad.Beckmann@amd.com return fault; 1737563SBrad.Beckmann@amd.com } 1747563SBrad.Beckmann@amd.com 1757563SBrad.Beckmann@amd.com %(op_decl)s; 1767563SBrad.Beckmann@amd.com %(op_rd)s; 1777563SBrad.Beckmann@amd.com %(ea_code)s; 1787663SBrad.Beckmann@amd.com 1797663SBrad.Beckmann@amd.com if (fault == NoFault) { 1807663SBrad.Beckmann@amd.com fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 1817663SBrad.Beckmann@amd.com %(memacc_code)s; 1827663SBrad.Beckmann@amd.com } 1837563SBrad.Beckmann@amd.com 1846903SBrad.Beckmann@amd.com if (fault == NoFault) { 1856903SBrad.Beckmann@amd.com %(op_wb)s; 1867563SBrad.Beckmann@amd.com } 1877563SBrad.Beckmann@amd.com 1888931Sandreas.hansson@arm.com return fault; 1898931Sandreas.hansson@arm.com } 1908931Sandreas.hansson@arm.com}}; 1918931Sandreas.hansson@arm.com 1926892SBrad.Beckmann@amd.com 1938436SBrad.Beckmann@amd.comdef template LoadInitiateAcc {{ 1948436SBrad.Beckmann@amd.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 1958436SBrad.Beckmann@amd.com Trace::InstRecord *traceData) const 1968436SBrad.Beckmann@amd.com { 1978436SBrad.Beckmann@amd.com Addr EA; 1988322Ssteve.reinhardt@amd.com Fault fault = NoFault; 1997809Snilay@cs.wisc.edu 200 if (this->isFloating()) { 201 %(fp_enable_check)s; 202 203 if(fault != NoFault) 204 return fault; 205 } 206 207 %(op_src_decl)s; 208 %(op_rd)s; 209 %(ea_code)s; 210 211 if (fault == NoFault) { 212 fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); 213 } 214 215 return fault; 216 } 217}}; 218 219def template LoadCompleteAcc {{ 220 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, 221 Trace::InstRecord *traceData) const 222 { 223 Fault fault = NoFault; 224 225 if (this->isFloating()) { 226 %(fp_enable_check)s; 227 228 if(fault != NoFault) 229 return fault; 230 } 231 232 %(op_decl)s; 233 %(op_rd)s; 234 235 getMem(pkt, Mem, traceData); 236 237 if (fault == NoFault) { 238 %(memacc_code)s; 239 } 240 241 if (fault == NoFault) { 242 %(op_wb)s; 243 } 244 245 return fault; 246 } 247}}; 248 249def template StoreExecute {{ 250 Fault %(class_name)s::execute(ExecContext *xc, 251 Trace::InstRecord *traceData) const 252 { 253 Addr EA; 254 Fault fault = NoFault; 255 256 %(fp_enable_check)s; 257 %(op_decl)s; 258 %(op_rd)s; 259 %(ea_code)s; 260 261 if (fault == NoFault) { 262 %(memacc_code)s; 263 } 264 265 if (fault == NoFault) { 266 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 267 NULL); 268 } 269 270 if (fault == NoFault) { 271 %(postacc_code)s; 272 } 273 274 if (fault == NoFault) { 275 %(op_wb)s; 276 } 277 278 return fault; 279 } 280}}; 281 282 283def template StoreFPExecute {{ 284 Fault %(class_name)s::execute(ExecContext *xc, 285 Trace::InstRecord *traceData) const 286 { 287 Addr EA; 288 Fault fault = NoFault; 289 290 %(fp_enable_check)s; 291 if(fault != NoFault) 292 return fault; 293 %(op_decl)s; 294 %(op_rd)s; 295 %(ea_code)s; 296 297 if (fault == NoFault) { 298 %(memacc_code)s; 299 } 300 301 if (fault == NoFault) { 302 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 303 NULL); 304 } 305 306 if (fault == NoFault) { 307 %(postacc_code)s; 308 } 309 310 if (fault == NoFault) { 311 %(op_wb)s; 312 } 313 314 return fault; 315 } 316}}; 317 318def template StoreCondExecute {{ 319 Fault %(class_name)s::execute(ExecContext *xc, 320 Trace::InstRecord *traceData) const 321 { 322 Addr EA; 323 Fault fault = NoFault; 324 uint64_t write_result = 0; 325 326 %(fp_enable_check)s; 327 %(op_decl)s; 328 %(op_rd)s; 329 %(ea_code)s; 330 331 if (fault == NoFault) { 332 %(memacc_code)s; 333 } 334 335 if (fault == NoFault) { 336 fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 337 &write_result); 338 } 339 340 if (fault == NoFault) { 341 %(postacc_code)s; 342 } 343 344 if (fault == NoFault) { 345 %(op_wb)s; 346 } 347 348 return fault; 349 } 350}}; 351 352def template StoreInitiateAcc {{ 353 Fault %(class_name)s::initiateAcc(ExecContext *xc, 354 Trace::InstRecord *traceData) const 355 { 356 Addr EA; 357 Fault fault = NoFault; 358 359 %(fp_enable_check)s; 360 %(op_decl)s; 361 %(op_rd)s; 362 %(ea_code)s; 363 364 if (fault == NoFault) { 365 %(memacc_code)s; 366 } 367 368 if (fault == NoFault) { 369 fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 370 NULL); 371 } 372 373 return fault; 374 } 375}}; 376 377 378def template StoreCompleteAcc {{ 379 Fault %(class_name)s::completeAcc(Packet *pkt, 380 ExecContext *xc, 381 Trace::InstRecord *traceData) const 382 { 383 return NoFault; 384 } 385}}; 386 387def template StoreCondCompleteAcc {{ 388 Fault %(class_name)s::completeAcc(Packet *pkt, 389 ExecContext *xc, 390 Trace::InstRecord *traceData) const 391 { 392 Fault fault = NoFault; 393 394 %(fp_enable_check)s; 395 %(op_dest_decl)s; 396 397 uint64_t write_result = pkt->req->getExtraData(); 398 399 if (fault == NoFault) { 400 %(postacc_code)s; 401 } 402 403 if (fault == NoFault) { 404 %(op_wb)s; 405 } 406 407 return fault; 408 } 409}}; 410 411def template MiscExecute {{ 412 Fault %(class_name)s::execute(ExecContext *xc, 413 Trace::InstRecord *traceData) const 414 { 415 Addr EA M5_VAR_USED = 0; 416 Fault fault = NoFault; 417 418 %(fp_enable_check)s; 419 %(op_decl)s; 420 %(op_rd)s; 421 %(ea_code)s; 422 423 if (fault == NoFault) { 424 %(memacc_code)s; 425 } 426 427 return NoFault; 428 } 429}}; 430 431def template MiscInitiateAcc {{ 432 Fault %(class_name)s::initiateAcc(ExecContext *xc, 433 Trace::InstRecord *traceData) const 434 { 435 panic("Misc instruction does not support split access method!"); 436 return NoFault; 437 } 438}}; 439 440 441def template MiscCompleteAcc {{ 442 Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, 443 Trace::InstRecord *traceData) const 444 { 445 panic("Misc instruction does not support split access method!"); 446 447 return NoFault; 448 } 449}}; 450 451def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 452 mem_flags = [], inst_flags = []) {{ 453 (header_output, decoder_output, decode_block, exec_output) = \ 454 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 455 decode_template = ImmNopCheckDecode, 456 exec_template_base = 'Load') 457}}; 458 459 460def format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 461 mem_flags = [], inst_flags = []) {{ 462 (header_output, decoder_output, decode_block, exec_output) = \ 463 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 464 exec_template_base = 'Store') 465}}; 466 467def format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 468 mem_flags = [], inst_flags = []) {{ 469 inst_flags += ['IsIndexed'] 470 (header_output, decoder_output, decode_block, exec_output) = \ 471 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 472 decode_template = ImmNopCheckDecode, 473 exec_template_base = 'Load') 474}}; 475 476def format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 477 mem_flags = [], inst_flags = []) {{ 478 inst_flags += ['IsIndexed'] 479 (header_output, decoder_output, decode_block, exec_output) = \ 480 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 481 exec_template_base = 'Store') 482}}; 483 484def format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 485 mem_flags = [], inst_flags = []) {{ 486 inst_flags += ['IsIndexed', 'IsFloating'] 487 (header_output, decoder_output, decode_block, exec_output) = \ 488 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 489 decode_template = ImmNopCheckDecode, 490 exec_template_base = 'Load') 491}}; 492 493def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 494 mem_flags = [], inst_flags = []) {{ 495 inst_flags += ['IsIndexed', 'IsFloating'] 496 (header_output, decoder_output, decode_block, exec_output) = \ 497 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 498 exec_template_base = 'Store') 499}}; 500 501 502def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 503 mem_flags = [], inst_flags = []) {{ 504 decl_code = ''' 505 uint32_t mem_word = Mem_uw; 506 uint32_t unalign_addr = Rs + disp; 507 uint32_t byte_offset = unalign_addr & 3; 508 if (GuestByteOrder == BigEndianByteOrder) 509 byte_offset ^= 3; 510 ''' 511 512 memacc_code = decl_code + memacc_code 513 514 (header_output, decoder_output, decode_block, exec_output) = \ 515 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 516 decode_template = ImmNopCheckDecode, 517 exec_template_base = 'Load') 518}}; 519 520def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 521 mem_flags = [], inst_flags = []) {{ 522 decl_code = ''' 523 uint32_t mem_word = 0; 524 uint32_t unaligned_addr = Rs + disp; 525 uint32_t byte_offset = unaligned_addr & 3; 526 if (GuestByteOrder == BigEndianByteOrder) 527 byte_offset ^= 3; 528 fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags); 529 ''' 530 memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 531 532 (header_output, decoder_output, decode_block, exec_output) = \ 533 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 534 exec_template_base = 'Store') 535}}; 536 537def format Prefetch(ea_code = {{ EA = Rs + disp; }}, 538 mem_flags = [], pf_flags = [], inst_flags = []) {{ 539 pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 540 pf_inst_flags = inst_flags 541 542 (header_output, decoder_output, decode_block, exec_output) = \ 543 LoadStoreBase(name, Name, ea_code, 544 'warn_once("Prefetching not implemented for MIPS\\n");', 545 pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 546 547}}; 548 549def format StoreCond(memacc_code, postacc_code, 550 ea_code = {{ EA = Rs + disp; }}, 551 mem_flags = [], inst_flags = []) {{ 552 (header_output, decoder_output, decode_block, exec_output) = \ 553 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 554 postacc_code, exec_template_base = 'StoreCond') 555}}; 556