mem.isa revision 12234
12124SN/A// -*- mode:c++ -*- 22124SN/A 35268Sksewell@umich.edu// Copyright (c) 2007 MIPS Technologies, Inc. 45268Sksewell@umich.edu// All rights reserved. 55268Sksewell@umich.edu// 65268Sksewell@umich.edu// Redistribution and use in source and binary forms, with or without 75268Sksewell@umich.edu// modification, are permitted provided that the following conditions are 85268Sksewell@umich.edu// met: redistributions of source code must retain the above copyright 95268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer; 105268Sksewell@umich.edu// redistributions in binary form must reproduce the above copyright 115268Sksewell@umich.edu// notice, this list of conditions and the following disclaimer in the 125268Sksewell@umich.edu// documentation and/or other materials provided with the distribution; 135268Sksewell@umich.edu// neither the name of the copyright holders nor the names of its 145268Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 155268Sksewell@umich.edu// this software without specific prior written permission. 165268Sksewell@umich.edu// 175268Sksewell@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 185268Sksewell@umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 195268Sksewell@umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 205268Sksewell@umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 215268Sksewell@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 225268Sksewell@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 235268Sksewell@umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 245268Sksewell@umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 255268Sksewell@umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 265268Sksewell@umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 275268Sksewell@umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 285268Sksewell@umich.edu// 295268Sksewell@umich.edu// Authors: Steve Reinhardt 305268Sksewell@umich.edu// Korey Sewell 312022SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342706Sksewell@umich.edu// Memory-format instructions 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372022SN/Aoutput header {{ 382124SN/A /** 392124SN/A * Base class for general Mips memory-format instructions. 402124SN/A */ 412124SN/A class Memory : public MipsStaticInst 422124SN/A { 432124SN/A protected: 442124SN/A /// Memory request flags. See mem_req_base.hh. 455736Snate@binkert.org Request::Flags memAccessFlags; 462239SN/A 472124SN/A /// Displacement for EA calculation (signed). 482124SN/A int32_t disp; 492124SN/A 502124SN/A /// Constructor 516207Sksewell@umich.edu Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 522124SN/A : MipsStaticInst(mnem, _machInst, __opClass), 532742Sksewell@umich.edu disp(sext<16>(OFFSET)) 542022SN/A { 552124SN/A } 562022SN/A 572124SN/A std::string 582124SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 592124SN/A }; 602124SN/A 612742Sksewell@umich.edu /** 622742Sksewell@umich.edu * Base class for a few miscellaneous memory-format insts 632742Sksewell@umich.edu * that don't interpret the disp field 642742Sksewell@umich.edu */ 652742Sksewell@umich.edu class MemoryNoDisp : public Memory 662742Sksewell@umich.edu { 672742Sksewell@umich.edu protected: 682742Sksewell@umich.edu /// Constructor 696207Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 706207Sksewell@umich.edu : Memory(mnem, _machInst, __opClass) 712742Sksewell@umich.edu { 722742Sksewell@umich.edu } 732742Sksewell@umich.edu 742742Sksewell@umich.edu std::string 752742Sksewell@umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 762742Sksewell@umich.edu }; 772022SN/A}}; 782022SN/A 792124SN/A 802022SN/Aoutput decoder {{ 812124SN/A std::string 822124SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 832124SN/A { 842742Sksewell@umich.edu return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 852239SN/A flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 862124SN/A } 872124SN/A 882742Sksewell@umich.edu std::string 892742Sksewell@umich.edu MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 902742Sksewell@umich.edu { 912742Sksewell@umich.edu return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 922742Sksewell@umich.edu flags[IsFloating] ? 'f' : 'r', 932742Sksewell@umich.edu flags[IsFloating] ? FD : RD, 942742Sksewell@umich.edu RS, RT); 952742Sksewell@umich.edu } 964661Sksewell@umich.edu 974661Sksewell@umich.edu}}; 984661Sksewell@umich.edu 999554Sandreas.hansson@arm.comoutput header {{ 10012234Sgabeblack@google.com uint64_t getMemData(ExecContext *xc, Packet *packet); 1019554Sandreas.hansson@arm.com 1029554Sandreas.hansson@arm.com}}; 1039554Sandreas.hansson@arm.com 1044661Sksewell@umich.eduoutput exec {{ 1054661Sksewell@umich.edu /** return data in cases where there the size of data is only 1064661Sksewell@umich.edu known in the packet 1074661Sksewell@umich.edu */ 10812234Sgabeblack@google.com uint64_t getMemData(ExecContext *xc, Packet *packet) { 1094661Sksewell@umich.edu switch (packet->getSize()) 1104661Sksewell@umich.edu { 1115222Sksewell@umich.edu case 1: 1124661Sksewell@umich.edu return packet->get<uint8_t>(); 1134661Sksewell@umich.edu 1145222Sksewell@umich.edu case 2: 1154661Sksewell@umich.edu return packet->get<uint16_t>(); 1164661Sksewell@umich.edu 1175222Sksewell@umich.edu case 4: 1184661Sksewell@umich.edu return packet->get<uint32_t>(); 1194661Sksewell@umich.edu 1205222Sksewell@umich.edu case 8: 1214661Sksewell@umich.edu return packet->get<uint64_t>(); 1224661Sksewell@umich.edu 1234661Sksewell@umich.edu default: 1244661Sksewell@umich.edu std::cerr << "bad store data size = " << packet->getSize() << std::endl; 1254661Sksewell@umich.edu 1264661Sksewell@umich.edu assert(0); 1274661Sksewell@umich.edu return 0; 1284661Sksewell@umich.edu } 1294661Sksewell@umich.edu } 1304661Sksewell@umich.edu 1314661Sksewell@umich.edu 1322022SN/A}}; 1332022SN/A 1342124SN/Adef template LoadStoreDeclare {{ 1352124SN/A /** 1362124SN/A * Static instruction class for "%(mnemonic)s". 1372124SN/A */ 1382124SN/A class %(class_name)s : public %(base_class)s 1392124SN/A { 1402124SN/A public: 1412124SN/A 1422124SN/A /// Constructor. 1434661Sksewell@umich.edu %(class_name)s(ExtMachInst machInst); 1442124SN/A 1452124SN/A %(BasicExecDeclare)s 1462124SN/A 1476207Sksewell@umich.edu %(EACompDeclare)s 1486207Sksewell@umich.edu 1492124SN/A %(InitiateAccDeclare)s 1502124SN/A 1512124SN/A %(CompleteAccDeclare)s 1522124SN/A }; 1532022SN/A}}; 1542022SN/A 1556207Sksewell@umich.edudef template EACompDeclare {{ 15612234Sgabeblack@google.com Fault eaComp(ExecContext *, Trace::InstRecord *) const; 1576207Sksewell@umich.edu}}; 1582124SN/A 1592124SN/Adef template InitiateAccDeclare {{ 16012234Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; 1612022SN/A}}; 1622124SN/A 1632124SN/A 1642124SN/Adef template CompleteAccDeclare {{ 16512234Sgabeblack@google.com Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const; 1662124SN/A}}; 1672124SN/A 1686207Sksewell@umich.edudef template LoadStoreConstructor {{ 16910184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst) 1706207Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1712124SN/A { 1723953Sstever@eecs.umich.edu %(constructor)s; 1732124SN/A } 1743953Sstever@eecs.umich.edu}}; 1752124SN/A 1763953Sstever@eecs.umich.edu 1772124SN/Adef template EACompExecute {{ 1782132SN/A Fault 17912234Sgabeblack@google.com %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const 1802124SN/A { 1812124SN/A Addr EA; 1822132SN/A Fault fault = NoFault; 1832124SN/A 1845222Sksewell@umich.edu if (this->isFloating()) { 1855222Sksewell@umich.edu %(fp_enable_check)s; 1865222Sksewell@umich.edu 1875222Sksewell@umich.edu if(fault != NoFault) 1885222Sksewell@umich.edu return fault; 1895222Sksewell@umich.edu } 1905222Sksewell@umich.edu 1912124SN/A %(op_decl)s; 1922124SN/A %(op_rd)s; 1933953Sstever@eecs.umich.edu %(ea_code)s; 1942124SN/A 1954661Sksewell@umich.edu // NOTE: Trace Data is written using execute or completeAcc templates 1962124SN/A if (fault == NoFault) { 1972124SN/A xc->setEA(EA); 1982124SN/A } 1992124SN/A 2002124SN/A return fault; 2012124SN/A } 2022124SN/A}}; 2032124SN/A 2042124SN/Adef template LoadExecute {{ 20512234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2062124SN/A Trace::InstRecord *traceData) const 2072124SN/A { 2082124SN/A Addr EA; 2092132SN/A Fault fault = NoFault; 2102124SN/A 2115222Sksewell@umich.edu if (this->isFloating()) { 2125222Sksewell@umich.edu %(fp_enable_check)s; 2135222Sksewell@umich.edu 2145222Sksewell@umich.edu if(fault != NoFault) 2155222Sksewell@umich.edu return fault; 2165222Sksewell@umich.edu } 2175222Sksewell@umich.edu 2182124SN/A %(op_decl)s; 2192124SN/A %(op_rd)s; 2202124SN/A %(ea_code)s; 2212124SN/A 2222124SN/A if (fault == NoFault) { 2238442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 2242124SN/A %(memacc_code)s; 2252124SN/A } 2262124SN/A 2272124SN/A if (fault == NoFault) { 2282124SN/A %(op_wb)s; 2292124SN/A } 2302124SN/A 2312124SN/A return fault; 2322124SN/A } 2332124SN/A}}; 2342124SN/A 2352124SN/A 2362124SN/Adef template LoadInitiateAcc {{ 23712234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 2382124SN/A Trace::InstRecord *traceData) const 2392124SN/A { 2402239SN/A Addr EA; 2412132SN/A Fault fault = NoFault; 2422239SN/A 2435222Sksewell@umich.edu if (this->isFloating()) { 2445222Sksewell@umich.edu %(fp_enable_check)s; 2455222Sksewell@umich.edu 2465222Sksewell@umich.edu if(fault != NoFault) 2475222Sksewell@umich.edu return fault; 2485222Sksewell@umich.edu } 2495222Sksewell@umich.edu 2502239SN/A %(op_src_decl)s; 2512239SN/A %(op_rd)s; 2522239SN/A %(ea_code)s; 2532239SN/A 2542239SN/A if (fault == NoFault) { 25511303Ssteve.reinhardt@amd.com fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); 2562239SN/A } 2572239SN/A 2582124SN/A return fault; 2592124SN/A } 2602124SN/A}}; 2612124SN/A 2622124SN/Adef template LoadCompleteAcc {{ 26312234Sgabeblack@google.com Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, 2642124SN/A Trace::InstRecord *traceData) const 2652124SN/A { 2662132SN/A Fault fault = NoFault; 2672239SN/A 2685222Sksewell@umich.edu if (this->isFloating()) { 2695222Sksewell@umich.edu %(fp_enable_check)s; 2705222Sksewell@umich.edu 2715222Sksewell@umich.edu if(fault != NoFault) 2725222Sksewell@umich.edu return fault; 2735222Sksewell@umich.edu } 2745222Sksewell@umich.edu 2752506SN/A %(op_decl)s; 2764661Sksewell@umich.edu %(op_rd)s; 2772239SN/A 2788442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 2792239SN/A 2802239SN/A if (fault == NoFault) { 2812239SN/A %(memacc_code)s; 2822239SN/A } 2832239SN/A 2842239SN/A if (fault == NoFault) { 2852239SN/A %(op_wb)s; 2862239SN/A } 2872239SN/A 2882124SN/A return fault; 2892124SN/A } 2902124SN/A}}; 2912124SN/A 2922124SN/Adef template StoreExecute {{ 29312234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2942124SN/A Trace::InstRecord *traceData) const 2952124SN/A { 2962124SN/A Addr EA; 2972132SN/A Fault fault = NoFault; 2984056Sstever@eecs.umich.edu 2994056Sstever@eecs.umich.edu %(fp_enable_check)s; 3004056Sstever@eecs.umich.edu %(op_decl)s; 3014056Sstever@eecs.umich.edu %(op_rd)s; 3024056Sstever@eecs.umich.edu %(ea_code)s; 3034056Sstever@eecs.umich.edu 3044056Sstever@eecs.umich.edu if (fault == NoFault) { 3054056Sstever@eecs.umich.edu %(memacc_code)s; 3064056Sstever@eecs.umich.edu } 3074056Sstever@eecs.umich.edu 3084056Sstever@eecs.umich.edu if (fault == NoFault) { 3098442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3108442Sgblack@eecs.umich.edu NULL); 3114056Sstever@eecs.umich.edu } 3124056Sstever@eecs.umich.edu 3134056Sstever@eecs.umich.edu if (fault == NoFault) { 3144056Sstever@eecs.umich.edu %(postacc_code)s; 3154056Sstever@eecs.umich.edu } 3164056Sstever@eecs.umich.edu 3174056Sstever@eecs.umich.edu if (fault == NoFault) { 3184056Sstever@eecs.umich.edu %(op_wb)s; 3194056Sstever@eecs.umich.edu } 3204056Sstever@eecs.umich.edu 3214056Sstever@eecs.umich.edu return fault; 3224056Sstever@eecs.umich.edu } 3234056Sstever@eecs.umich.edu}}; 3244056Sstever@eecs.umich.edu 3255222Sksewell@umich.edu 3265222Sksewell@umich.edudef template StoreFPExecute {{ 32712234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 3285222Sksewell@umich.edu Trace::InstRecord *traceData) const 3295222Sksewell@umich.edu { 3305222Sksewell@umich.edu Addr EA; 3315222Sksewell@umich.edu Fault fault = NoFault; 3325222Sksewell@umich.edu 3335222Sksewell@umich.edu %(fp_enable_check)s; 3345222Sksewell@umich.edu if(fault != NoFault) 3355222Sksewell@umich.edu return fault; 3365222Sksewell@umich.edu %(op_decl)s; 3375222Sksewell@umich.edu %(op_rd)s; 3385222Sksewell@umich.edu %(ea_code)s; 3395222Sksewell@umich.edu 3405222Sksewell@umich.edu if (fault == NoFault) { 3415222Sksewell@umich.edu %(memacc_code)s; 3425222Sksewell@umich.edu } 3435222Sksewell@umich.edu 3445222Sksewell@umich.edu if (fault == NoFault) { 3458442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3468442Sgblack@eecs.umich.edu NULL); 3475222Sksewell@umich.edu } 3485222Sksewell@umich.edu 3495222Sksewell@umich.edu if (fault == NoFault) { 3505222Sksewell@umich.edu %(postacc_code)s; 3515222Sksewell@umich.edu } 3525222Sksewell@umich.edu 3535222Sksewell@umich.edu if (fault == NoFault) { 3545222Sksewell@umich.edu %(op_wb)s; 3555222Sksewell@umich.edu } 3565222Sksewell@umich.edu 3575222Sksewell@umich.edu return fault; 3585222Sksewell@umich.edu } 3595222Sksewell@umich.edu}}; 3605222Sksewell@umich.edu 3614056Sstever@eecs.umich.edudef template StoreCondExecute {{ 36212234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 3634056Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 3644056Sstever@eecs.umich.edu { 3654056Sstever@eecs.umich.edu Addr EA; 3664056Sstever@eecs.umich.edu Fault fault = NoFault; 3672124SN/A uint64_t write_result = 0; 3682124SN/A 3692124SN/A %(fp_enable_check)s; 3702124SN/A %(op_decl)s; 3712124SN/A %(op_rd)s; 3722124SN/A %(ea_code)s; 3732124SN/A 3742124SN/A if (fault == NoFault) { 3752124SN/A %(memacc_code)s; 3762124SN/A } 3772124SN/A 3782124SN/A if (fault == NoFault) { 3798442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3808442Sgblack@eecs.umich.edu &write_result); 3812124SN/A } 3822124SN/A 3832124SN/A if (fault == NoFault) { 3842124SN/A %(postacc_code)s; 3852124SN/A } 3862124SN/A 3872124SN/A if (fault == NoFault) { 3882124SN/A %(op_wb)s; 3892124SN/A } 3902124SN/A 3912124SN/A return fault; 3922124SN/A } 3932124SN/A}}; 3942124SN/A 3952124SN/Adef template StoreInitiateAcc {{ 39612234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 3972124SN/A Trace::InstRecord *traceData) const 3982124SN/A { 3992239SN/A Addr EA; 4002132SN/A Fault fault = NoFault; 4012239SN/A 4022239SN/A %(fp_enable_check)s; 4032506SN/A %(op_decl)s; 4042239SN/A %(op_rd)s; 4052239SN/A %(ea_code)s; 4062239SN/A 4072239SN/A if (fault == NoFault) { 4082239SN/A %(memacc_code)s; 4092239SN/A } 4102239SN/A 4112239SN/A if (fault == NoFault) { 4128442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 4138442Sgblack@eecs.umich.edu NULL); 4142239SN/A } 4152239SN/A 4162124SN/A return fault; 4172124SN/A } 4182124SN/A}}; 4192124SN/A 4202124SN/A 4212124SN/Adef template StoreCompleteAcc {{ 4224661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 42312234Sgabeblack@google.com ExecContext *xc, 4242124SN/A Trace::InstRecord *traceData) const 4252124SN/A { 4267712Sgblack@eecs.umich.edu return NoFault; 4272935Sksewell@umich.edu } 4282935Sksewell@umich.edu}}; 4292935Sksewell@umich.edu 4302935Sksewell@umich.edudef template StoreCondCompleteAcc {{ 4314661Sksewell@umich.edu Fault %(class_name)s::completeAcc(Packet *pkt, 43212234Sgabeblack@google.com ExecContext *xc, 4332935Sksewell@umich.edu Trace::InstRecord *traceData) const 4342935Sksewell@umich.edu { 4352935Sksewell@umich.edu Fault fault = NoFault; 4362935Sksewell@umich.edu 4372935Sksewell@umich.edu %(fp_enable_check)s; 4382935Sksewell@umich.edu %(op_dest_decl)s; 4392935Sksewell@umich.edu 4404055Ssaidi@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 4412239SN/A 4422239SN/A if (fault == NoFault) { 4432239SN/A %(postacc_code)s; 4442239SN/A } 4452239SN/A 4462239SN/A if (fault == NoFault) { 4472239SN/A %(op_wb)s; 4482239SN/A } 4492239SN/A 4502124SN/A return fault; 4512124SN/A } 4522124SN/A}}; 4532124SN/A 4542686Sksewell@umich.edudef template MiscExecute {{ 45512234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 4562686Sksewell@umich.edu Trace::InstRecord *traceData) const 4572686Sksewell@umich.edu { 4587725SAli.Saidi@ARM.com Addr EA M5_VAR_USED = 0; 4592686Sksewell@umich.edu Fault fault = NoFault; 4602686Sksewell@umich.edu 4612686Sksewell@umich.edu %(fp_enable_check)s; 4622686Sksewell@umich.edu %(op_decl)s; 4632686Sksewell@umich.edu %(op_rd)s; 4642686Sksewell@umich.edu %(ea_code)s; 4652686Sksewell@umich.edu 4662686Sksewell@umich.edu if (fault == NoFault) { 4672686Sksewell@umich.edu %(memacc_code)s; 4682686Sksewell@umich.edu } 4692686Sksewell@umich.edu 4702686Sksewell@umich.edu return NoFault; 4712686Sksewell@umich.edu } 4722686Sksewell@umich.edu}}; 4732686Sksewell@umich.edu 4742686Sksewell@umich.edudef template MiscInitiateAcc {{ 47512234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 4762686Sksewell@umich.edu Trace::InstRecord *traceData) const 4772686Sksewell@umich.edu { 4782686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4792686Sksewell@umich.edu return NoFault; 4802686Sksewell@umich.edu } 4812686Sksewell@umich.edu}}; 4822686Sksewell@umich.edu 4832686Sksewell@umich.edu 4842686Sksewell@umich.edudef template MiscCompleteAcc {{ 48512234Sgabeblack@google.com Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, 4862686Sksewell@umich.edu Trace::InstRecord *traceData) const 4872686Sksewell@umich.edu { 4882686Sksewell@umich.edu panic("Misc instruction does not support split access method!"); 4892686Sksewell@umich.edu 4902686Sksewell@umich.edu return NoFault; 4912686Sksewell@umich.edu } 4922686Sksewell@umich.edu}}; 4932686Sksewell@umich.edu 4942124SN/Adef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4952124SN/A mem_flags = [], inst_flags = []) {{ 4962124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4972124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4982750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 4992124SN/A exec_template_base = 'Load') 5002124SN/A}}; 5012124SN/A 5025222Sksewell@umich.edu 5032124SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 5042124SN/A mem_flags = [], inst_flags = []) {{ 5052124SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5062124SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5072124SN/A exec_template_base = 'Store') 5082124SN/A}}; 5092124SN/A 5102686Sksewell@umich.edudef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5112573SN/A mem_flags = [], inst_flags = []) {{ 5125222Sksewell@umich.edu inst_flags += ['IsIndexed'] 5132573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5142573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5152750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5162573SN/A exec_template_base = 'Load') 5172573SN/A}}; 5182573SN/A 5192686Sksewell@umich.edudef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5202573SN/A mem_flags = [], inst_flags = []) {{ 5215222Sksewell@umich.edu inst_flags += ['IsIndexed'] 5222573SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5232573SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5242573SN/A exec_template_base = 'Store') 5252573SN/A}}; 5262573SN/A 5275222Sksewell@umich.edudef format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5285222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5295222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 5305222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5315222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5325222Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5335222Sksewell@umich.edu exec_template_base = 'Load') 5345222Sksewell@umich.edu}}; 5355222Sksewell@umich.edu 5365222Sksewell@umich.edudef format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5375222Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5385222Sksewell@umich.edu inst_flags += ['IsIndexed', 'IsFloating'] 5395222Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5405222Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5415222Sksewell@umich.edu exec_template_base = 'Store') 5425222Sksewell@umich.edu}}; 5435222Sksewell@umich.edu 5445222Sksewell@umich.edu 5452686Sksewell@umich.edudef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5462686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5478564Sgblack@eecs.umich.edu decl_code = ''' 5488588Sgblack@eecs.umich.edu uint32_t mem_word = Mem_uw; 5498564Sgblack@eecs.umich.edu uint32_t unalign_addr = Rs + disp; 5508564Sgblack@eecs.umich.edu uint32_t byte_offset = unalign_addr & 3; 5518564Sgblack@eecs.umich.edu if (GuestByteOrder == BigEndianByteOrder) 5528564Sgblack@eecs.umich.edu byte_offset ^= 3; 5538564Sgblack@eecs.umich.edu ''' 5542573SN/A 5552686Sksewell@umich.edu memacc_code = decl_code + memacc_code 5562686Sksewell@umich.edu 5572686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5582686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5592750Sksewell@umich.edu decode_template = ImmNopCheckDecode, 5602686Sksewell@umich.edu exec_template_base = 'Load') 5612686Sksewell@umich.edu}}; 5622686Sksewell@umich.edu 5632686Sksewell@umich.edudef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5642686Sksewell@umich.edu mem_flags = [], inst_flags = []) {{ 5658442Sgblack@eecs.umich.edu decl_code = ''' 5668442Sgblack@eecs.umich.edu uint32_t mem_word = 0; 5678442Sgblack@eecs.umich.edu uint32_t unaligned_addr = Rs + disp; 5688442Sgblack@eecs.umich.edu uint32_t byte_offset = unaligned_addr & 3; 5698564Sgblack@eecs.umich.edu if (GuestByteOrder == BigEndianByteOrder) 5708442Sgblack@eecs.umich.edu byte_offset ^= 3; 5718442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags); 5728442Sgblack@eecs.umich.edu ''' 5732686Sksewell@umich.edu memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 5742686Sksewell@umich.edu 5752686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5762686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5772686Sksewell@umich.edu exec_template_base = 'Store') 5782686Sksewell@umich.edu}}; 5792686Sksewell@umich.edu 5802686Sksewell@umich.edudef format Prefetch(ea_code = {{ EA = Rs + disp; }}, 5812686Sksewell@umich.edu mem_flags = [], pf_flags = [], inst_flags = []) {{ 5826739Sgblack@eecs.umich.edu pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 5837725SAli.Saidi@ARM.com pf_inst_flags = inst_flags 5842686Sksewell@umich.edu 5852686Sksewell@umich.edu (header_output, decoder_output, decode_block, exec_output) = \ 5862686Sksewell@umich.edu LoadStoreBase(name, Name, ea_code, 5877725SAli.Saidi@ARM.com 'warn_once("Prefetching not implemented for MIPS\\n");', 5882686Sksewell@umich.edu pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5892686Sksewell@umich.edu 5902686Sksewell@umich.edu}}; 5912686Sksewell@umich.edu 5922686Sksewell@umich.edudef format StoreCond(memacc_code, postacc_code, 5932686Sksewell@umich.edu ea_code = {{ EA = Rs + disp; }}, 5942495SN/A mem_flags = [], inst_flags = []) {{ 5952495SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5962495SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5972935Sksewell@umich.edu postacc_code, exec_template_base = 'StoreCond') 5982495SN/A}}; 599