mem.isa revision 10184
11689SN/A// -*- mode:c++ -*- 27944SGiacomo.Gabrielli@arm.com 37944SGiacomo.Gabrielli@arm.com// Copyright (c) 2007 MIPS Technologies, Inc. 47944SGiacomo.Gabrielli@arm.com// All rights reserved. 57944SGiacomo.Gabrielli@arm.com// 67944SGiacomo.Gabrielli@arm.com// Redistribution and use in source and binary forms, with or without 77944SGiacomo.Gabrielli@arm.com// modification, are permitted provided that the following conditions are 87944SGiacomo.Gabrielli@arm.com// met: redistributions of source code must retain the above copyright 97944SGiacomo.Gabrielli@arm.com// notice, this list of conditions and the following disclaimer; 107944SGiacomo.Gabrielli@arm.com// redistributions in binary form must reproduce the above copyright 117944SGiacomo.Gabrielli@arm.com// notice, this list of conditions and the following disclaimer in the 127944SGiacomo.Gabrielli@arm.com// documentation and/or other materials provided with the distribution; 137944SGiacomo.Gabrielli@arm.com// neither the name of the copyright holders nor the names of its 142326SN/A// contributors may be used to endorse or promote products derived from 151689SN/A// this software without specific prior written permission. 161689SN/A// 171689SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 181689SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 191689SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 201689SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 211689SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 221689SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 231689SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 241689SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 251689SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 261689SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 271689SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 281689SN/A// 291689SN/A// Authors: Steve Reinhardt 301689SN/A// Korey Sewell 311689SN/A 321689SN/A//////////////////////////////////////////////////////////////////// 331689SN/A// 341689SN/A// Memory-format instructions 351689SN/A// 361689SN/A 371689SN/Aoutput header {{ 381689SN/A /** 392665Ssaidi@eecs.umich.edu * Base class for general Mips memory-format instructions. 402665Ssaidi@eecs.umich.edu */ 412831Sksewell@umich.edu class Memory : public MipsStaticInst 421689SN/A { 431689SN/A protected: 442064SN/A /// Memory request flags. See mem_req_base.hh. 451060SN/A Request::Flags memAccessFlags; 461060SN/A 472292SN/A /// Displacement for EA calculation (signed). 481717SN/A int32_t disp; 498232Snate@binkert.org 504762Snate@binkert.org /// Constructor 516221Snate@binkert.org Memory(const char *mnem, MachInst _machInst, OpClass __opClass) 524762Snate@binkert.org : MipsStaticInst(mnem, _machInst, __opClass), 531060SN/A disp(sext<16>(OFFSET)) 548737Skoansin.tan@gmail.com { 558737Skoansin.tan@gmail.com } 568737Skoansin.tan@gmail.com 575529Snate@binkert.org std::string 581061SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 592292SN/A }; 605606Snate@binkert.org 618581Ssteve.reinhardt@amd.com /** 628581Ssteve.reinhardt@amd.com * Base class for a few miscellaneous memory-format insts 631060SN/A * that don't interpret the disp field 642292SN/A */ 652292SN/A class MemoryNoDisp : public Memory 662292SN/A { 672292SN/A protected: 682292SN/A /// Constructor 692292SN/A MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 702326SN/A : Memory(mnem, _machInst, __opClass) 712292SN/A { 722292SN/A } 732292SN/A 742292SN/A std::string 752292SN/A generateDisassembly(Addr pc, const SymbolTable *symtab) const; 762292SN/A }; 775336Shines@cs.fsu.edu}}; 782292SN/A 794873Sstever@eecs.umich.edu 802292SN/Aoutput decoder {{ 812292SN/A std::string 822292SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 834329Sktlim@umich.edu { 845529Snate@binkert.org return csprintf("%-10s %c%d, %d(r%d)", mnemonic, 854329Sktlim@umich.edu flags[IsFloating] ? 'f' : 'r', RT, disp, RS); 864329Sktlim@umich.edu } 874329Sktlim@umich.edu 882292SN/A std::string 892292SN/A MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 902292SN/A { 912292SN/A return csprintf("%-10s %c%d, r%d(r%d)", mnemonic, 922292SN/A flags[IsFloating] ? 'f' : 'r', 932292SN/A flags[IsFloating] ? FD : RD, 942292SN/A RS, RT); 952292SN/A } 962307SN/A 972307SN/A}}; 985529Snate@binkert.org 991060SN/Aoutput header {{ 1001060SN/A uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet); 1011060SN/A 1021060SN/A}}; 1031060SN/A 1041060SN/Aoutput exec {{ 1052326SN/A /** return data in cases where there the size of data is only 1061060SN/A known in the packet 1071060SN/A */ 1081060SN/A uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet) { 1091060SN/A switch (packet->getSize()) 1102292SN/A { 1116221Snate@binkert.org case 1: 1126221Snate@binkert.org return packet->get<uint8_t>(); 1136221Snate@binkert.org 1141060SN/A case 2: 1151060SN/A return packet->get<uint16_t>(); 1162307SN/A 1172292SN/A case 4: 1182980Sgblack@eecs.umich.edu return packet->get<uint32_t>(); 1192292SN/A 1202292SN/A case 8: 1212292SN/A return packet->get<uint64_t>(); 1222292SN/A 1232292SN/A default: 1242292SN/A std::cerr << "bad store data size = " << packet->getSize() << std::endl; 1252292SN/A 1262292SN/A assert(0); 1272292SN/A return 0; 1282292SN/A } 1296221Snate@binkert.org } 1306221Snate@binkert.org 1312292SN/A 1322292SN/A}}; 1332292SN/A 1342292SN/Adef template LoadStoreDeclare {{ 1352292SN/A /** 1362292SN/A * Static instruction class for "%(mnemonic)s". 1372292SN/A */ 1382292SN/A class %(class_name)s : public %(base_class)s 1392292SN/A { 1406221Snate@binkert.org public: 1416221Snate@binkert.org 1422292SN/A /// Constructor. 1432292SN/A %(class_name)s(ExtMachInst machInst); 1442831Sksewell@umich.edu 1452292SN/A %(BasicExecDeclare)s 1462292SN/A 1472292SN/A %(EACompDeclare)s 1482292SN/A 1492292SN/A %(InitiateAccDeclare)s 1502292SN/A 1512292SN/A %(CompleteAccDeclare)s 1522292SN/A }; 1532292SN/A}}; 1546221Snate@binkert.org 1556221Snate@binkert.orgdef template EACompDeclare {{ 1562292SN/A Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1572292SN/A}}; 1582831Sksewell@umich.edu 1592292SN/Adef template InitiateAccDeclare {{ 1602292SN/A Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 1612292SN/A}}; 1622292SN/A 1632292SN/A 1642292SN/Adef template CompleteAccDeclare {{ 1652292SN/A Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; 1662292SN/A}}; 1672292SN/A 1682292SN/Adef template LoadStoreConstructor {{ 1692326SN/A %(class_name)s::%(class_name)s(ExtMachInst machInst) 1702348SN/A : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1712326SN/A { 1722326SN/A %(constructor)s; 1732348SN/A } 1742292SN/A}}; 1752292SN/A 1762292SN/A 1772292SN/Adef template EACompExecute {{ 1782292SN/A Fault 1792292SN/A %(class_name)s::eaComp(%(CPU_exec_context)s *xc, 1802292SN/A Trace::InstRecord *traceData) const 1811060SN/A { 1821060SN/A Addr EA; 1831061SN/A Fault fault = NoFault; 1841060SN/A 1851062SN/A if (this->isFloating()) { 1861062SN/A %(fp_enable_check)s; 1872301SN/A 1881062SN/A if(fault != NoFault) 1891062SN/A return fault; 1901062SN/A } 1911062SN/A 1921062SN/A %(op_decl)s; 1931062SN/A %(op_rd)s; 1941062SN/A %(ea_code)s; 1951062SN/A 1961062SN/A // NOTE: Trace Data is written using execute or completeAcc templates 1971062SN/A if (fault == NoFault) { 1982301SN/A xc->setEA(EA); 1992301SN/A } 2002301SN/A 2012301SN/A return fault; 2021062SN/A } 2031062SN/A}}; 2041062SN/A 2051062SN/Adef template LoadExecute {{ 2061062SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2071062SN/A Trace::InstRecord *traceData) const 2081062SN/A { 2091062SN/A Addr EA; 2101062SN/A Fault fault = NoFault; 2111062SN/A 2121062SN/A if (this->isFloating()) { 2131062SN/A %(fp_enable_check)s; 2141062SN/A 2151062SN/A if(fault != NoFault) 2161062SN/A return fault; 2171062SN/A } 2181062SN/A 2191062SN/A %(op_decl)s; 2201062SN/A %(op_rd)s; 2211062SN/A %(ea_code)s; 2221062SN/A 2231062SN/A if (fault == NoFault) { 2241062SN/A fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 2251062SN/A %(memacc_code)s; 2261062SN/A } 2271062SN/A 2281062SN/A if (fault == NoFault) { 2291062SN/A %(op_wb)s; 2301062SN/A } 2311062SN/A 2321062SN/A return fault; 2331062SN/A } 2341062SN/A}}; 2351062SN/A 2361062SN/A 2371062SN/Adef template LoadInitiateAcc {{ 2381062SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 2391062SN/A Trace::InstRecord *traceData) const 2401062SN/A { 2411062SN/A Addr EA; 2421062SN/A Fault fault = NoFault; 2431062SN/A 2441062SN/A if (this->isFloating()) { 2451062SN/A %(fp_enable_check)s; 2461062SN/A 2471062SN/A if(fault != NoFault) 2481062SN/A return fault; 2492361SN/A } 2502326SN/A 2512301SN/A %(op_src_decl)s; 2522301SN/A %(op_rd)s; 2532301SN/A %(ea_code)s; 2542301SN/A 2552301SN/A if (fault == NoFault) { 2562301SN/A fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags); 2572326SN/A } 2582301SN/A 2592361SN/A return fault; 2602326SN/A } 2612307SN/A}}; 2628240Snate@binkert.org 2632301SN/Adef template LoadCompleteAcc {{ 2642307SN/A Fault %(class_name)s::completeAcc(Packet *pkt, 2652301SN/A %(CPU_exec_context)s *xc, 2662301SN/A Trace::InstRecord *traceData) const 2672301SN/A { 2682301SN/A Fault fault = NoFault; 2698240Snate@binkert.org 2702301SN/A if (this->isFloating()) { 2712301SN/A %(fp_enable_check)s; 2722301SN/A 2732301SN/A if(fault != NoFault) 2742301SN/A return fault; 2752301SN/A } 2762301SN/A 2772326SN/A %(op_decl)s; 2784762Snate@binkert.org %(op_rd)s; 2798240Snate@binkert.org 2802301SN/A getMem(pkt, Mem, traceData); 2812301SN/A 2822301SN/A if (fault == NoFault) { 2834762Snate@binkert.org %(memacc_code)s; 2842301SN/A } 2852301SN/A 2862301SN/A if (fault == NoFault) { 2872301SN/A %(op_wb)s; 2882361SN/A } 2892326SN/A 2902301SN/A return fault; 2918240Snate@binkert.org } 2922301SN/A}}; 2932301SN/A 2942301SN/Adef template StoreExecute {{ 2952301SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 2962301SN/A Trace::InstRecord *traceData) const 2972980Sgblack@eecs.umich.edu { 2982301SN/A Addr EA; 2992326SN/A Fault fault = NoFault; 3002301SN/A 3012361SN/A %(fp_enable_check)s; 3022326SN/A %(op_decl)s; 3038240Snate@binkert.org %(op_rd)s; 3042301SN/A %(ea_code)s; 3052301SN/A 3062301SN/A if (fault == NoFault) { 3072326SN/A %(memacc_code)s; 3082727Sktlim@umich.edu } 3092326SN/A 3102301SN/A if (fault == NoFault) { 3118240Snate@binkert.org fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3122301SN/A NULL); 3132301SN/A } 3142301SN/A 3152301SN/A if (fault == NoFault) { 3164762Snate@binkert.org %(postacc_code)s; 3172301SN/A } 3182301SN/A 3192326SN/A if (fault == NoFault) { 3202301SN/A %(op_wb)s; 3218240Snate@binkert.org } 3222301SN/A 3232301SN/A return fault; 3242301SN/A } 3252301SN/A}}; 3262326SN/A 3278240Snate@binkert.org 3282301SN/Adef template StoreFPExecute {{ 3292301SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3302301SN/A Trace::InstRecord *traceData) const 3312326SN/A { 3322301SN/A Addr EA; 3336221Snate@binkert.org Fault fault = NoFault; 3342292SN/A 3356221Snate@binkert.org %(fp_enable_check)s; 3362292SN/A if(fault != NoFault) 3377897Shestness@cs.utexas.edu return fault; 3387897Shestness@cs.utexas.edu %(op_decl)s; 3397897Shestness@cs.utexas.edu %(op_rd)s; 3407897Shestness@cs.utexas.edu %(ea_code)s; 3417897Shestness@cs.utexas.edu 3427897Shestness@cs.utexas.edu if (fault == NoFault) { 3437897Shestness@cs.utexas.edu %(memacc_code)s; 3447897Shestness@cs.utexas.edu } 3457897Shestness@cs.utexas.edu 3467897Shestness@cs.utexas.edu if (fault == NoFault) { 3477897Shestness@cs.utexas.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3487897Shestness@cs.utexas.edu NULL); 3497897Shestness@cs.utexas.edu } 3507897Shestness@cs.utexas.edu 3517897Shestness@cs.utexas.edu if (fault == NoFault) { 3527897Shestness@cs.utexas.edu %(postacc_code)s; 3537897Shestness@cs.utexas.edu } 3547897Shestness@cs.utexas.edu 3557897Shestness@cs.utexas.edu if (fault == NoFault) { 3567897Shestness@cs.utexas.edu %(op_wb)s; 3577897Shestness@cs.utexas.edu } 3587897Shestness@cs.utexas.edu 3597897Shestness@cs.utexas.edu return fault; 3607897Shestness@cs.utexas.edu } 3617897Shestness@cs.utexas.edu}}; 3627897Shestness@cs.utexas.edu 3637897Shestness@cs.utexas.edudef template StoreCondExecute {{ 3647897Shestness@cs.utexas.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3657897Shestness@cs.utexas.edu Trace::InstRecord *traceData) const 3667897Shestness@cs.utexas.edu { 3677897Shestness@cs.utexas.edu Addr EA; 3687897Shestness@cs.utexas.edu Fault fault = NoFault; 3697897Shestness@cs.utexas.edu uint64_t write_result = 0; 3707897Shestness@cs.utexas.edu 3717897Shestness@cs.utexas.edu %(fp_enable_check)s; 3727897Shestness@cs.utexas.edu %(op_decl)s; 3737897Shestness@cs.utexas.edu %(op_rd)s; 3747897Shestness@cs.utexas.edu %(ea_code)s; 3757897Shestness@cs.utexas.edu 3767897Shestness@cs.utexas.edu if (fault == NoFault) { 3777897Shestness@cs.utexas.edu %(memacc_code)s; 3781062SN/A } 3791062SN/A 3801062SN/A if (fault == NoFault) { 3811062SN/A fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3822307SN/A &write_result); 3831060SN/A } 3842307SN/A 3856221Snate@binkert.org if (fault == NoFault) { 3866221Snate@binkert.org %(postacc_code)s; 3876221Snate@binkert.org } 3882307SN/A 3891060SN/A if (fault == NoFault) { 3902307SN/A %(op_wb)s; 3912307SN/A } 3922307SN/A 3932307SN/A return fault; 3942307SN/A } 3952307SN/A}}; 3962307SN/A 3972307SN/Adef template StoreInitiateAcc {{ 3982307SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 3992307SN/A Trace::InstRecord *traceData) const 4002307SN/A { 4012307SN/A Addr EA; 4026221Snate@binkert.org Fault fault = NoFault; 4036221Snate@binkert.org 4042307SN/A %(fp_enable_check)s; 4052307SN/A %(op_decl)s; 4062307SN/A %(op_rd)s; 4072307SN/A %(ea_code)s; 4082307SN/A 4092307SN/A if (fault == NoFault) { 4102307SN/A %(memacc_code)s; 4112307SN/A } 4122307SN/A 4132307SN/A if (fault == NoFault) { 4147944SGiacomo.Gabrielli@arm.com fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 4151060SN/A NULL); 4161060SN/A } 4171061SN/A 4181060SN/A return fault; 4196221Snate@binkert.org } 4201060SN/A}}; 4212292SN/A 4222064SN/A 4232064SN/Adef template StoreCompleteAcc {{ 4242064SN/A Fault %(class_name)s::completeAcc(Packet *pkt, 4252064SN/A %(CPU_exec_context)s *xc, 4262292SN/A Trace::InstRecord *traceData) const 4272064SN/A { 4284318Sktlim@umich.edu return NoFault; 4291060SN/A } 4301060SN/A}}; 4311061SN/A 4321060SN/Adef template StoreCondCompleteAcc {{ 4331060SN/A Fault %(class_name)s::completeAcc(Packet *pkt, 4341060SN/A %(CPU_exec_context)s *xc, 4351060SN/A Trace::InstRecord *traceData) const 4361060SN/A { 4371060SN/A Fault fault = NoFault; 4381060SN/A 4391060SN/A %(fp_enable_check)s; 4401684SN/A %(op_dest_decl)s; 4412307SN/A 4422307SN/A uint64_t write_result = pkt->req->getExtraData(); 4432307SN/A 4442367SN/A if (fault == NoFault) { 4452367SN/A %(postacc_code)s; 4462367SN/A } 4472367SN/A 4482367SN/A if (fault == NoFault) { 4492367SN/A %(op_wb)s; 4502367SN/A } 4512307SN/A 4522326SN/A return fault; 4532367SN/A } 4542307SN/A}}; 4556221Snate@binkert.org 4566221Snate@binkert.orgdef template MiscExecute {{ 4572307SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 4582307SN/A Trace::InstRecord *traceData) const 4592307SN/A { 4602307SN/A Addr EA M5_VAR_USED = 0; 4612307SN/A Fault fault = NoFault; 4622307SN/A 4632307SN/A %(fp_enable_check)s; 4642307SN/A %(op_decl)s; 4652307SN/A %(op_rd)s; 4662307SN/A %(ea_code)s; 4672307SN/A 4682292SN/A if (fault == NoFault) { 4696221Snate@binkert.org %(memacc_code)s; 4702292SN/A } 4712292SN/A 4722292SN/A return NoFault; 4732292SN/A } 4742292SN/A}}; 4752292SN/A 4762292SN/Adef template MiscInitiateAcc {{ 4772292SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, 4782292SN/A Trace::InstRecord *traceData) const 4792292SN/A { 4802292SN/A panic("Misc instruction does not support split access method!"); 4812292SN/A return NoFault; 4822292SN/A } 4832292SN/A}}; 4843867Sbinkertn@umich.edu 4852292SN/A 4866221Snate@binkert.orgdef template MiscCompleteAcc {{ 4876221Snate@binkert.org Fault %(class_name)s::completeAcc(Packet *pkt, 4882292SN/A %(CPU_exec_context)s *xc, 4893867Sbinkertn@umich.edu Trace::InstRecord *traceData) const 4906221Snate@binkert.org { 4913867Sbinkertn@umich.edu panic("Misc instruction does not support split access method!"); 4922292SN/A 4933867Sbinkertn@umich.edu return NoFault; 4942292SN/A } 4953867Sbinkertn@umich.edu}}; 4962292SN/A 4972292SN/Adef format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 4982292SN/A mem_flags = [], inst_flags = []) {{ 4992292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5002292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5012292SN/A decode_template = ImmNopCheckDecode, 5021684SN/A exec_template_base = 'Load') 5031684SN/A}}; 5041684SN/A 5051684SN/A 5061684SN/Adef format StoreMemory(memacc_code, ea_code = {{ EA = Rs + disp; }}, 5071684SN/A mem_flags = [], inst_flags = []) {{ 5082292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5092292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5106221Snate@binkert.org exec_template_base = 'Store') 5112292SN/A}}; 5122292SN/A 5132292SN/Adef format LoadIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5142292SN/A mem_flags = [], inst_flags = []) {{ 5151060SN/A inst_flags += ['IsIndexed'] 5161060SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5171061SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5181060SN/A decode_template = ImmNopCheckDecode, 5191060SN/A exec_template_base = 'Load') 5201060SN/A}}; 5211060SN/A 5221060SN/Adef format StoreIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5231060SN/A mem_flags = [], inst_flags = []) {{ 5241060SN/A inst_flags += ['IsIndexed'] 5251060SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5261060SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5271060SN/A exec_template_base = 'Store') 5281061SN/A}}; 5292292SN/A 5306221Snate@binkert.orgdef format LoadFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5312292SN/A mem_flags = [], inst_flags = []) {{ 5322292SN/A inst_flags += ['IsIndexed', 'IsFloating'] 5332292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5342292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5352292SN/A decode_template = ImmNopCheckDecode, 5362292SN/A exec_template_base = 'Load') 5372292SN/A}}; 5382292SN/A 5392292SN/Adef format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, 5402292SN/A mem_flags = [], inst_flags = []) {{ 5412292SN/A inst_flags += ['IsIndexed', 'IsFloating'] 5422292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5432292SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5442292SN/A exec_template_base = 'Store') 5452292SN/A}}; 5462292SN/A 5472292SN/A 5482292SN/Adef format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5492292SN/A mem_flags = [], inst_flags = []) {{ 5502292SN/A decl_code = ''' 5512292SN/A uint32_t mem_word = Mem_uw; 5522292SN/A uint32_t unalign_addr = Rs + disp; 5532292SN/A uint32_t byte_offset = unalign_addr & 3; 5542292SN/A if (GuestByteOrder == BigEndianByteOrder) 5552292SN/A byte_offset ^= 3; 5562292SN/A ''' 5571060SN/A 5581061SN/A memacc_code = decl_code + memacc_code 5591060SN/A 5607897Shestness@cs.utexas.edu (header_output, decoder_output, decode_block, exec_output) = \ 5611060SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5621060SN/A decode_template = ImmNopCheckDecode, 5631060SN/A exec_template_base = 'Load') 5647720Sgblack@eecs.umich.edu}}; 5657720Sgblack@eecs.umich.edu 5661060SN/Adef format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, 5671060SN/A mem_flags = [], inst_flags = []) {{ 5681060SN/A decl_code = ''' 5692292SN/A uint32_t mem_word = 0; 5701060SN/A uint32_t unaligned_addr = Rs + disp; 5712064SN/A uint32_t byte_offset = unaligned_addr & 3; 5721060SN/A if (GuestByteOrder == BigEndianByteOrder) 5732292SN/A byte_offset ^= 3; 5741060SN/A fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags); 5751060SN/A ''' 5761060SN/A memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' 5771060SN/A 5781060SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5791060SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5801060SN/A exec_template_base = 'Store') 5812326SN/A}}; 5821060SN/A 5831061SN/Adef format Prefetch(ea_code = {{ EA = Rs + disp; }}, 5842292SN/A mem_flags = [], pf_flags = [], inst_flags = []) {{ 5851062SN/A pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 5861062SN/A pf_inst_flags = inst_flags 5871061SN/A 5881061SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5891062SN/A LoadStoreBase(name, Name, ea_code, 5901060SN/A 'warn_once("Prefetching not implemented for MIPS\\n");', 5912292SN/A pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 5922292SN/A 5931060SN/A}}; 5941060SN/A 5951060SN/Adef format StoreCond(memacc_code, postacc_code, 5961061SN/A ea_code = {{ EA = Rs + disp; }}, 5971061SN/A mem_flags = [], inst_flags = []) {{ 5982292SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5991061SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 6001061SN/A postacc_code, exec_template_base = 'StoreCond') 6011061SN/A}}; 6027897Shestness@cs.utexas.edu