int.isa revision 12106:7784fac1b159
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007 MIPS Technologies, Inc. 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30 31//////////////////////////////////////////////////////////////////// 32// 33// Integer operate instructions 34// 35output header {{ 36#include <iostream> 37 using namespace std; 38 /** 39 * Base class for integer operations. 40 */ 41 class IntOp : public MipsStaticInst 42 { 43 protected: 44 45 /// Constructor 46 IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 47 MipsStaticInst(mnem, _machInst, __opClass) 48 { 49 } 50 51 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 52 }; 53 54 55 class HiLoOp: public IntOp 56 { 57 protected: 58 59 /// Constructor 60 HiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 61 IntOp(mnem, _machInst, __opClass) 62 { 63 } 64 65 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 66 }; 67 68 class HiLoRsSelOp: public HiLoOp 69 { 70 protected: 71 72 /// Constructor 73 HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 74 HiLoOp(mnem, _machInst, __opClass) 75 { 76 } 77 78 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 79 }; 80 81 class HiLoRdSelOp: public HiLoOp 82 { 83 protected: 84 85 /// Constructor 86 HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 87 HiLoOp(mnem, _machInst, __opClass) 88 { 89 } 90 91 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 92 }; 93 94 class HiLoRdSelValOp: public HiLoOp 95 { 96 protected: 97 98 /// Constructor 99 HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 100 HiLoOp(mnem, _machInst, __opClass) 101 { 102 } 103 104 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 105 }; 106 107 class IntImmOp : public MipsStaticInst 108 { 109 protected: 110 111 int16_t imm; 112 int32_t sextImm; 113 uint32_t zextImm; 114 115 /// Constructor 116 IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) : 117 MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM), 118 sextImm(INTIMM),zextImm(0x0000FFFF & INTIMM) 119 { 120 //If Bit 15 is 1 then Sign Extend 121 int32_t temp = sextImm & 0x00008000; 122 if (temp > 0 && strcmp(mnemonic,"lui") != 0) { 123 sextImm |= 0xFFFF0000; 124 } 125 } 126 127 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 128 129 130 }; 131 132}}; 133 134// HiLo instruction class execute method template. 135def template HiLoExecute {{ 136 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 137 { 138 Fault fault = NoFault; 139 140 %(fp_enable_check)s; 141 %(op_decl)s; 142 %(op_rd)s; 143 %(code)s; 144 145 if(fault == NoFault) 146 { 147 %(op_wb)s; 148 } 149 return fault; 150 } 151}}; 152 153// HiLoRsSel instruction class execute method template. 154def template HiLoRsSelExecute {{ 155 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 156 { 157 Fault fault = NoFault; 158 159 %(op_decl)s; 160 161 if( ACSRC > 0 && !isDspEnabled(xc) ) 162 { 163 fault = std::make_shared<DspStateDisabledFault>(); 164 } 165 else 166 { 167 %(op_rd)s; 168 %(code)s; 169 } 170 171 if(fault == NoFault) 172 { 173 %(op_wb)s; 174 } 175 return fault; 176 } 177}}; 178 179// HiLoRdSel instruction class execute method template. 180def template HiLoRdSelExecute {{ 181 Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const 182 { 183 Fault fault = NoFault; 184 185 %(op_decl)s; 186 187 if( ACDST > 0 && !isDspEnabled(xc) ) 188 { 189 fault = std::make_shared<DspStateDisabledFault>(); 190 } 191 else 192 { 193 %(op_rd)s; 194 %(code)s; 195 } 196 197 if(fault == NoFault) 198 { 199 %(op_wb)s; 200 } 201 return fault; 202 } 203}}; 204 205//Outputs to decoder.cc 206output decoder {{ 207 std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 208 { 209 std::stringstream ss; 210 211 ccprintf(ss, "%-10s ", mnemonic); 212 213 // just print the first dest... if there's a second one, 214 // it's generally implicit 215 if (_numDestRegs > 0) { 216 printReg(ss, _destRegIdx[0]); 217 ss << ", "; 218 } 219 220 // just print the first two source regs... if there's 221 // a third one, it's a read-modify-write dest (Rc), 222 // e.g. for CMOVxx 223 if (_numSrcRegs > 0) { 224 printReg(ss, _srcRegIdx[0]); 225 } 226 227 if (_numSrcRegs > 1) { 228 ss << ", "; 229 printReg(ss, _srcRegIdx[1]); 230 } 231 232 return ss.str(); 233 } 234 235 std::string HiLoOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 236 { 237 std::stringstream ss; 238 239 ccprintf(ss, "%-10s ", mnemonic); 240 241 //Destination Registers are implicit for HI/LO ops 242 if (_numSrcRegs > 0) { 243 printReg(ss, _srcRegIdx[0]); 244 } 245 246 if (_numSrcRegs > 1) { 247 ss << ", "; 248 printReg(ss, _srcRegIdx[1]); 249 } 250 251 return ss.str(); 252 } 253 254 std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 255 { 256 std::stringstream ss; 257 258 ccprintf(ss, "%-10s ", mnemonic); 259 260 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { 261 printReg(ss, _destRegIdx[0]); 262 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { 263 printReg(ss, _srcRegIdx[0]); 264 } 265 266 return ss.str(); 267 } 268 269 std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 270 { 271 std::stringstream ss; 272 273 ccprintf(ss, "%-10s ", mnemonic); 274 275 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { 276 printReg(ss, _destRegIdx[0]); 277 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { 278 printReg(ss, _srcRegIdx[0]); 279 } 280 281 return ss.str(); 282 } 283 284 std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 285 { 286 std::stringstream ss; 287 288 ccprintf(ss, "%-10s ", mnemonic); 289 290 if (_numDestRegs > 0 && _destRegIdx[0].index() < 32) { 291 printReg(ss, _destRegIdx[0]); 292 } else if (_numSrcRegs > 0 && _srcRegIdx[0].index() < 32) { 293 printReg(ss, _srcRegIdx[0]); 294 } 295 296 return ss.str(); 297 } 298 299 std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 300 { 301 std::stringstream ss; 302 303 ccprintf(ss, "%-10s ", mnemonic); 304 305 if (_numDestRegs > 0) { 306 printReg(ss, _destRegIdx[0]); 307 } 308 309 ss << ", "; 310 311 if (_numSrcRegs > 0) { 312 printReg(ss, _srcRegIdx[0]); 313 ss << ", "; 314 } 315 316 if(strcmp(mnemonic,"lui") == 0) 317 ccprintf(ss, "0x%x ", sextImm); 318 else 319 ss << (int) sextImm; 320 321 return ss.str(); 322 } 323 324}}; 325 326def format IntOp(code, *opt_flags) {{ 327 iop = InstObjParams(name, Name, 'IntOp', code, opt_flags) 328 header_output = BasicDeclare.subst(iop) 329 decoder_output = BasicConstructor.subst(iop) 330 decode_block = RegNopCheckDecode.subst(iop) 331 exec_output = BasicExecute.subst(iop) 332}}; 333 334def format IntImmOp(code, *opt_flags) {{ 335 iop = InstObjParams(name, Name, 'IntImmOp', code, opt_flags) 336 header_output = BasicDeclare.subst(iop) 337 decoder_output = BasicConstructor.subst(iop) 338 decode_block = ImmNopCheckDecode.subst(iop) 339 exec_output = BasicExecute.subst(iop) 340}}; 341 342def format HiLoRsSelOp(code, *opt_flags) {{ 343 iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags) 344 header_output = BasicDeclare.subst(iop) 345 decoder_output = BasicConstructor.subst(iop) 346 decode_block = BasicDecode.subst(iop) 347 exec_output = HiLoRsSelExecute.subst(iop) 348}}; 349 350def format HiLoRdSelOp(code, *opt_flags) {{ 351 iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags) 352 header_output = BasicDeclare.subst(iop) 353 decoder_output = BasicConstructor.subst(iop) 354 decode_block = BasicDecode.subst(iop) 355 exec_output = HiLoRdSelExecute.subst(iop) 356}}; 357 358def format HiLoRdSelValOp(code, *opt_flags) {{ 359 360 if '_sd' in code: 361 code = 'int64_t ' + code 362 elif '_ud' in code: 363 code = 'uint64_t ' + code 364 365 code += 'HI_RD_SEL = val<63:32>;\n' 366 code += 'LO_RD_SEL = val<31:0>;\n' 367 368 iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags) 369 header_output = BasicDeclare.subst(iop) 370 decoder_output = BasicConstructor.subst(iop) 371 decode_block = BasicDecode.subst(iop) 372 exec_output = HiLoRdSelExecute.subst(iop) 373}}; 374 375def format HiLoOp(code, *opt_flags) {{ 376 iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags) 377 header_output = BasicDeclare.subst(iop) 378 decoder_output = BasicConstructor.subst(iop) 379 decode_block = BasicDecode.subst(iop) 380 exec_output = HiLoExecute.subst(iop) 381}}; 382