decoder.isa revision 8607:5fb918115c07
19814Sandreas.hansson@arm.com// -*- mode:c++ -*- 22292SN/A 310030SAli.Saidi@ARM.com// Copyright (c) 2007 MIPS Technologies, Inc. 410239Sbinhpham@cs.rutgers.edu// All rights reserved. 57597Sminkyu.jeong@arm.com// 67597Sminkyu.jeong@arm.com// Redistribution and use in source and binary forms, with or without 77597Sminkyu.jeong@arm.com// modification, are permitted provided that the following conditions are 87597Sminkyu.jeong@arm.com// met: redistributions of source code must retain the above copyright 97597Sminkyu.jeong@arm.com// notice, this list of conditions and the following disclaimer; 107597Sminkyu.jeong@arm.com// redistributions in binary form must reproduce the above copyright 117597Sminkyu.jeong@arm.com// notice, this list of conditions and the following disclaimer in the 127597Sminkyu.jeong@arm.com// documentation and/or other materials provided with the distribution; 137597Sminkyu.jeong@arm.com// neither the name of the copyright holders nor the names of its 147597Sminkyu.jeong@arm.com// contributors may be used to endorse or promote products derived from 157597Sminkyu.jeong@arm.com// this software without specific prior written permission. 162292SN/A// 172292SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182292SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192292SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202292SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212292SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222292SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232292SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242292SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252292SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262292SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272292SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282292SN/A// 292292SN/A// Authors: Korey Sewell 302292SN/A// Brett Miller 312292SN/A// Jaidev Patwardhan 322292SN/A 332292SN/A//////////////////////////////////////////////////////////////////// 342292SN/A// 352292SN/A// The actual MIPS32 ISA decoder 362292SN/A// ----------------------------- 372292SN/A// The following instructions are specified in the MIPS32 ISA 382292SN/A// Specification. Decoding closely follows the style specified 392292SN/A// in the MIPS32 ISA specification document starting with Table 402292SN/A// A-2 (document available @ http://www.mips.com) 412689Sktlim@umich.edu// 422689Sktlim@umich.edudecode OPCODE_HI default Unknown::unknown() { 432689Sktlim@umich.edu //Table A-2 442292SN/A 0x0: decode OPCODE_LO { 452292SN/A 0x0: decode FUNCTION_HI { 469944Smatt.horsnell@ARM.com 0x0: decode FUNCTION_LO { 479944Smatt.horsnell@ARM.com 0x1: decode MOVCI { 489944Smatt.horsnell@ARM.com format BasicOp { 498591Sgblack@eecs.umich.edu 0: movf({{ 503326Sktlim@umich.edu Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; 518229Snate@binkert.org }}); 526658Snate@binkert.org 1: movt({{ 538887Sgeoffrey.blake@arm.com Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; 542907Sktlim@umich.edu }}); 552292SN/A } 568232Snate@binkert.org } 578232Snate@binkert.org 588232Snate@binkert.org format BasicOp { 599527SMatt.Horsnell@arm.com //Table A-3 Note: "Specific encodings of the rd, rs, and 602722Sktlim@umich.edu //rt fields are used to distinguish SLL, SSNOP, and EHB 612669Sktlim@umich.edu //functions 622292SN/A 0x0: decode RS { 632669Sktlim@umich.edu 0x0: decode RT_RD { 642678Sktlim@umich.edu 0x0: decode SA default Nop::nop() { 652678Sktlim@umich.edu 0x1: ssnop({{;}}); 668581Ssteve.reinhardt@amd.com 0x3: ehb({{;}}); 678581Ssteve.reinhardt@amd.com } 682292SN/A default: sll({{ Rd = Rt_uw << SA; }}); 692292SN/A } 702292SN/A } 712669Sktlim@umich.edu 722292SN/A 0x2: decode RS_SRL { 732678Sktlim@umich.edu 0x0:decode SRL { 742292SN/A 0: srl({{ Rd = Rt_uw >> SA; }}); 759444SAndreas.Sandberg@ARM.com 769444SAndreas.Sandberg@ARM.com //Hardcoded assuming 32-bit ISA, 779444SAndreas.Sandberg@ARM.com //probably need parameter here 784319Sktlim@umich.edu 1: rotr({{ 794319Sktlim@umich.edu Rd = (Rt_uw << (32 - SA)) | (Rt_uw >> SA); 804319Sktlim@umich.edu }}); 814319Sktlim@umich.edu } 824319Sktlim@umich.edu } 832678Sktlim@umich.edu 842678Sktlim@umich.edu 0x3: decode RS { 852292SN/A 0x0: sra({{ 862678Sktlim@umich.edu uint32_t temp = Rt >> SA; 872678Sktlim@umich.edu if ( (Rt & 0x80000000) > 0 ) { 885336Shines@cs.fsu.edu uint32_t mask = 0x80000000; 892678Sktlim@umich.edu for(int i=0; i < SA; i++) { 904873Sstever@eecs.umich.edu temp |= mask; 912678Sktlim@umich.edu mask = mask >> 1; 922292SN/A } 932678Sktlim@umich.edu } 942678Sktlim@umich.edu Rd = temp; 952678Sktlim@umich.edu }}); 962678Sktlim@umich.edu } 972678Sktlim@umich.edu 982678Sktlim@umich.edu 0x4: sllv({{ Rd = Rt_uw << Rs<4:0>; }}); 997852SMatt.Horsnell@arm.com 1007852SMatt.Horsnell@arm.com 0x6: decode SRLV { 1012344SN/A 0: srlv({{ Rd = Rt_uw >> Rs<4:0>; }}); 1022678Sktlim@umich.edu 1032678Sktlim@umich.edu //Hardcoded assuming 32-bit ISA, 1046974Stjones1@inf.ed.ac.uk //probably need parameter here 1056974Stjones1@inf.ed.ac.uk 1: rotrv({{ 1066974Stjones1@inf.ed.ac.uk Rd = (Rt_uw << (32 - Rs<4:0>)) | 1076974Stjones1@inf.ed.ac.uk (Rt_uw >> Rs<4:0>); 1086974Stjones1@inf.ed.ac.uk }}); 1096974Stjones1@inf.ed.ac.uk } 1106974Stjones1@inf.ed.ac.uk 1119444SAndreas.Sandberg@ARM.com 0x7: srav({{ 11210327Smitch.hayenga@arm.com int shift_amt = Rs<4:0>; 1132678Sktlim@umich.edu 1146974Stjones1@inf.ed.ac.uk uint32_t temp = Rt >> shift_amt; 1156974Stjones1@inf.ed.ac.uk 1166974Stjones1@inf.ed.ac.uk if ((Rt & 0x80000000) > 0) { 1176974Stjones1@inf.ed.ac.uk uint32_t mask = 0x80000000; 1186974Stjones1@inf.ed.ac.uk for (int i = 0; i < shift_amt; i++) { 1196974Stjones1@inf.ed.ac.uk temp |= mask; 1202678Sktlim@umich.edu mask = mask >> 1; 1212678Sktlim@umich.edu } 1222678Sktlim@umich.edu } 1232678Sktlim@umich.edu Rd = temp; 1242678Sktlim@umich.edu }}); 1252344SN/A } 1262307SN/A } 1276974Stjones1@inf.ed.ac.uk 1286974Stjones1@inf.ed.ac.uk 0x1: decode FUNCTION_LO { 1296974Stjones1@inf.ed.ac.uk //Table A-3 Note: "Specific encodings of the hint field are 1306974Stjones1@inf.ed.ac.uk //used to distinguish JR from JR.HB and JALR from JALR.HB" 13110020Smatt.horsnell@ARM.com format Jump { 13210020Smatt.horsnell@ARM.com 0x0: decode HINT { 13310023Smatt.horsnell@ARM.com 0x1: jr_hb({{ 13410023Smatt.horsnell@ARM.com Config1Reg config1 = Config1; 1352678Sktlim@umich.edu if (config1.ca == 0) { 1364032Sktlim@umich.edu NNPC = Rs; 1372678Sktlim@umich.edu } else { 1382292SN/A panic("MIPS16e not supported\n"); 1392292SN/A } 1402292SN/A }}, IsReturn, ClearHazards); 1412292SN/A default: jr({{ 1428545Ssaidi@eecs.umich.edu Config1Reg config1 = Config1; 1432678Sktlim@umich.edu if (config1.ca == 0) { 1448727Snilay@cs.wisc.edu NNPC = Rs; 1452292SN/A } else { 1462292SN/A panic("MIPS16e not supported\n"); 1472292SN/A } 1482292SN/A }}, IsReturn); 1492292SN/A } 1505529Snate@binkert.org 1515529Snate@binkert.org 0x1: decode HINT { 1525529Snate@binkert.org 0x1: jalr_hb({{ 1532292SN/A Rd = NNPC; 1544329Sktlim@umich.edu NNPC = Rs; 1554329Sktlim@umich.edu }}, IsCall, ClearHazards); 1564329Sktlim@umich.edu default: jalr({{ 1572907Sktlim@umich.edu Rd = NNPC; 1582907Sktlim@umich.edu NNPC = Rs; 1592292SN/A }}, IsCall); 1602292SN/A } 16110175SMitch.Hayenga@ARM.com } 16210175SMitch.Hayenga@ARM.com 1632329SN/A format BasicOp { 1642329SN/A 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 1652329SN/A 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 1662292SN/A 0x4: decode FULL_SYSTEM { 1679936SFaissal.Sleiman@arm.com 0: syscall_se({{ xc->syscall(R2); }}, 1689936SFaissal.Sleiman@arm.com IsSerializeAfter, IsNonSpeculative); 1699936SFaissal.Sleiman@arm.com default: syscall({{ fault = new SystemCallFault(); }}); 1709936SFaissal.Sleiman@arm.com } 1712292SN/A 0x7: sync({{ ; }}, IsMemBarrier); 1722292SN/A 0x5: break({{fault = new BreakpointFault();}}); 1732292SN/A } 1748199SAli.Saidi@ARM.com 1758199SAli.Saidi@ARM.com } 1769444SAndreas.Sandberg@ARM.com 1779444SAndreas.Sandberg@ARM.com 0x2: decode FUNCTION_LO { 1789444SAndreas.Sandberg@ARM.com 0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }}, 1799444SAndreas.Sandberg@ARM.com IntMultOp, IsIprAccess); 1809444SAndreas.Sandberg@ARM.com 0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }}); 1819444SAndreas.Sandberg@ARM.com 0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }}, 1829444SAndreas.Sandberg@ARM.com IntMultOp, IsIprAccess); 1839444SAndreas.Sandberg@ARM.com 0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }}); 1849444SAndreas.Sandberg@ARM.com } 1859444SAndreas.Sandberg@ARM.com 1869444SAndreas.Sandberg@ARM.com 0x3: decode FUNCTION_LO { 1879444SAndreas.Sandberg@ARM.com format HiLoRdSelValOp { 1888199SAli.Saidi@ARM.com 0x0: mult({{ val = Rs_sd * Rt_sd; }}, IntMultOp); 1892292SN/A 0x1: multu({{ val = Rs_ud * Rt_ud; }}, IntMultOp); 1902292SN/A } 1912292SN/A 1922292SN/A format HiLoOp { 1932292SN/A 0x2: div({{ 1942292SN/A if (Rt_sd != 0) { 1953492Sktlim@umich.edu HI0 = Rs_sd % Rt_sd; 1962329SN/A LO0 = Rs_sd / Rt_sd; 1972292SN/A } 1982292SN/A }}, IntDivOp); 1999444SAndreas.Sandberg@ARM.com 2009444SAndreas.Sandberg@ARM.com 0x3: divu({{ 2019444SAndreas.Sandberg@ARM.com if (Rt_ud != 0) { 2029444SAndreas.Sandberg@ARM.com HI0 = Rs_ud % Rt_ud; 2039444SAndreas.Sandberg@ARM.com LO0 = Rs_ud / Rt_ud; 2049814Sandreas.hansson@arm.com } 2052292SN/A }}, IntDivOp); 2062292SN/A } 2072292SN/A } 2082292SN/A 2092292SN/A 0x4: decode HINT { 2102292SN/A 0x0: decode FUNCTION_LO { 2112292SN/A format IntOp { 2122292SN/A 0x0: add({{ 2132292SN/A IntReg result; 2148247Snate@binkert.org Rd = result = Rs + Rt; 2152292SN/A if (FULL_SYSTEM && 2162292SN/A findOverflow(32, result, Rs, Rt)) { 2172292SN/A fault = new IntegerOverflowFault(); 2182292SN/A } 2192292SN/A }}); 2202727Sktlim@umich.edu 0x1: addu({{ Rd_sw = Rs_sw + Rt_sw;}}); 2212727Sktlim@umich.edu 0x2: sub({{ 2222727Sktlim@umich.edu IntReg result; 2232727Sktlim@umich.edu Rd = result = Rs - Rt; 2242727Sktlim@umich.edu if (FULL_SYSTEM && 2252727Sktlim@umich.edu findOverflow(32, result, Rs, ~Rt)) { 2262727Sktlim@umich.edu fault = new IntegerOverflowFault(); 2272727Sktlim@umich.edu } 2282727Sktlim@umich.edu }}); 2292727Sktlim@umich.edu 0x3: subu({{ Rd_sw = Rs_sw - Rt_sw; }}); 2302727Sktlim@umich.edu 0x4: and({{ Rd = Rs & Rt; }}); 2312727Sktlim@umich.edu 0x5: or({{ Rd = Rs | Rt; }}); 2322727Sktlim@umich.edu 0x6: xor({{ Rd = Rs ^ Rt; }}); 2332727Sktlim@umich.edu 0x7: nor({{ Rd = ~(Rs | Rt); }}); 2342727Sktlim@umich.edu } 2352727Sktlim@umich.edu } 2362727Sktlim@umich.edu } 2372727Sktlim@umich.edu 2382361SN/A 0x5: decode HINT { 2392361SN/A 0x0: decode FUNCTION_LO { 2402361SN/A format IntOp{ 2412361SN/A 0x2: slt({{ Rd_sw = (Rs_sw < Rt_sw) ? 1 : 0 }}); 2422727Sktlim@umich.edu 0x3: sltu({{ Rd_uw = (Rs_uw < Rt_uw) ? 1 : 0 }}); 2432727Sktlim@umich.edu } 2442727Sktlim@umich.edu } 2452727Sktlim@umich.edu } 2462727Sktlim@umich.edu 2472727Sktlim@umich.edu 0x6: decode FUNCTION_LO { 2482727Sktlim@umich.edu format Trap { 2492727Sktlim@umich.edu 0x0: tge({{ cond = (Rs_sw >= Rt_sw); }}); 2502727Sktlim@umich.edu 0x1: tgeu({{ cond = (Rs_uw >= Rt_uw); }}); 2512727Sktlim@umich.edu 0x2: tlt({{ cond = (Rs_sw < Rt_sw); }}); 2522727Sktlim@umich.edu 0x3: tltu({{ cond = (Rs_uw < Rt_uw); }}); 2532727Sktlim@umich.edu 0x4: teq({{ cond = (Rs_sw == Rt_sw); }}); 2542727Sktlim@umich.edu 0x6: tne({{ cond = (Rs_sw != Rt_sw); }}); 2552727Sktlim@umich.edu } 2562727Sktlim@umich.edu } 2572727Sktlim@umich.edu } 2582727Sktlim@umich.edu 2592727Sktlim@umich.edu 0x1: decode REGIMM_HI { 2602727Sktlim@umich.edu 0x0: decode REGIMM_LO { 2612727Sktlim@umich.edu format Branch { 2622727Sktlim@umich.edu 0x0: bltz({{ cond = (Rs_sw < 0); }}); 2632727Sktlim@umich.edu 0x1: bgez({{ cond = (Rs_sw >= 0); }}); 2642727Sktlim@umich.edu 0x2: bltzl({{ cond = (Rs_sw < 0); }}, Likely); 2658922Swilliam.wang@arm.com 0x3: bgezl({{ cond = (Rs_sw >= 0); }}, Likely); 2664329Sktlim@umich.edu } 2674329Sktlim@umich.edu } 2684329Sktlim@umich.edu 2694329Sktlim@umich.edu 0x1: decode REGIMM_LO { 2704329Sktlim@umich.edu format TrapImm { 2714329Sktlim@umich.edu 0x0: tgei( {{ cond = (Rs_sw >= (int16_t)INTIMM); }}); 2722292SN/A 0x1: tgeiu({{ 2732292SN/A cond = (Rs_uw >= (uint32_t)(int32_t)(int16_t)INTIMM); 2742292SN/A }}); 2752292SN/A 0x2: tlti( {{ cond = (Rs_sw < (int16_t)INTIMM); }}); 2762292SN/A 0x3: tltiu({{ 2772292SN/A cond = (Rs_uw < (uint32_t)(int32_t)(int16_t)INTIMM); 2782292SN/A }}); 2792292SN/A 0x4: teqi( {{ cond = (Rs_sw == (int16_t)INTIMM); }}); 2802292SN/A 0x6: tnei( {{ cond = (Rs_sw != (int16_t)INTIMM); }}); 2812292SN/A } 2822292SN/A } 2832292SN/A 2842292SN/A 0x2: decode REGIMM_LO { 2852292SN/A format Branch { 2869444SAndreas.Sandberg@ARM.com 0x0: bltzal({{ cond = (Rs_sw < 0); }}, Link); 2872307SN/A 0x1: decode RS { 2889444SAndreas.Sandberg@ARM.com 0x0: bal ({{ cond = 1; }}, IsCall, Link); 2892367SN/A default: bgezal({{ cond = (Rs_sw >= 0); }}, Link); 2902307SN/A } 2912329SN/A 0x2: bltzall({{ cond = (Rs_sw < 0); }}, Link, Likely); 2929444SAndreas.Sandberg@ARM.com 0x3: bgezall({{ cond = (Rs_sw >= 0); }}, Link, Likely); 2932307SN/A } 2942307SN/A } 2952307SN/A 2962307SN/A 0x3: decode REGIMM_LO { 2972307SN/A // from Table 5-4 MIPS32 REGIMM Encoding of rt Field 2982307SN/A // (DSP ASE MANUAL) 2999444SAndreas.Sandberg@ARM.com 0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }}); 3002307SN/A format WarnUnimpl { 3012307SN/A 0x7: synci(); 3022307SN/A } 3032307SN/A } 3042292SN/A } 3052292SN/A 3062329SN/A format Jump { 3072329SN/A 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}); 3082292SN/A 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, 3092329SN/A IsCall, Link); 3102329SN/A } 3112292SN/A 3122292SN/A format Branch { 3132292SN/A 0x4: decode RS_RT { 3142292SN/A 0x0: b({{ cond = 1; }}); 3152292SN/A default: beq({{ cond = (Rs_sw == Rt_sw); }}); 3162329SN/A } 3172292SN/A 0x5: bne({{ cond = (Rs_sw != Rt_sw); }}); 3182292SN/A 0x6: blez({{ cond = (Rs_sw <= 0); }}); 3199936SFaissal.Sleiman@arm.com 0x7: bgtz({{ cond = (Rs_sw > 0); }}); 3202292SN/A } 3212292SN/A } 3222292SN/A 3232292SN/A 0x1: decode OPCODE_LO { 3242292SN/A format IntImmOp { 3252292SN/A 0x0: addi({{ 3262329SN/A IntReg result; 3272329SN/A Rt = result = Rs + imm; 3282329SN/A if (FULL_SYSTEM && 3292292SN/A findOverflow(32, result, Rs, imm)) { 3302292SN/A fault = new IntegerOverflowFault(); 3312292SN/A } 3322292SN/A }}); 3332292SN/A 0x1: addiu({{ Rt_sw = Rs_sw + imm; }}); 3342329SN/A 0x2: slti({{ Rt_sw = (Rs_sw < imm) ? 1 : 0 }}); 3352292SN/A 0x3: sltiu({{ Rt_uw = (Rs_uw < (uint32_t)sextImm) ? 1 : 0;}}); 3369936SFaissal.Sleiman@arm.com 0x4: andi({{ Rt_sw = Rs_sw & zextImm; }}); 3379936SFaissal.Sleiman@arm.com 0x5: ori({{ Rt_sw = Rs_sw | zextImm; }}); 3382292SN/A 0x6: xori({{ Rt_sw = Rs_sw ^ zextImm; }}); 3392292SN/A 3402292SN/A 0x7: decode RS { 3412292SN/A 0x0: lui({{ Rt = imm << 16; }}); 3422292SN/A } 3432292SN/A } 3442292SN/A } 3452292SN/A 3462292SN/A 0x2: decode OPCODE_LO { 3472292SN/A //Table A-11 MIPS32 COP0 Encoding of rs Field 3482292SN/A 0x0: decode RS_MSB { 3492292SN/A 0x0: decode RS { 3502292SN/A format CP0Control { 3512292SN/A 0x0: mfc0({{ 3522292SN/A Config3Reg config3 = Config3; 3532292SN/A PageGrainReg pageGrain = PageGrain; 3542292SN/A Rt = CP0_RD_SEL; 3552292SN/A /* Hack for PageMask */ 3562292SN/A if (RD == 5) { 3572292SN/A // PageMask 3582292SN/A if (config3.sp == 0 || pageGrain.esp == 0) 3592292SN/A Rt &= 0xFFFFE7FF; 3602292SN/A } 3612329SN/A }}); 3622329SN/A 0x4: mtc0({{ 3632292SN/A CP0_RD_SEL = Rt; 3647720Sgblack@eecs.umich.edu CauseReg cause = Cause; 3657720Sgblack@eecs.umich.edu IntCtlReg intCtl = IntCtl; 3662292SN/A if (RD == 11) { 3672292SN/A // Compare 3682292SN/A if (cause.ti == 1) { 3692292SN/A cause.ti = 0; 3702292SN/A int offset = 10; // corresponding to cause.ip0 3712292SN/A offset += intCtl.ipti - 2; 3722292SN/A replaceBits(cause, offset, offset, 0); 3732292SN/A } 3742292SN/A } 3752292SN/A Cause = cause; 3762292SN/A }}); 3772292SN/A } 3782292SN/A format CP0Unimpl { 3792292SN/A 0x1: dmfc0(); 3802292SN/A 0x5: dmtc0(); 3812292SN/A default: unknown(); 3822292SN/A } 3832292SN/A format MT_MFTR { 3842292SN/A // Decode MIPS MT MFTR instruction into sub-instructions 3852292SN/A 0x8: decode MT_U { 3862292SN/A 0x0: mftc0({{ 3872292SN/A data = xc->readRegOtherThread((RT << 3 | SEL) + 3882292SN/A Ctrl_Base_DepTag); 3892292SN/A }}); 3907720Sgblack@eecs.umich.edu 0x1: decode SEL { 3917720Sgblack@eecs.umich.edu 0x0: mftgpr({{ 3922292SN/A data = xc->readRegOtherThread(RT); 3932292SN/A }}); 3942292SN/A 0x1: decode RT { 3952292SN/A 0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_LO0); }}); 3962292SN/A 0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_HI0); }}); 3972292SN/A 0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(INTREG_DSP_ACX0); }}); 3982292SN/A 0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_LO1); }}); 3992292SN/A 0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_HI1); }}); 4002292SN/A 0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(INTREG_DSP_ACX1); }}); 4012292SN/A 0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_LO2); }}); 4022292SN/A 0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_HI2); }}); 4032292SN/A 0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(INTREG_DSP_ACX2); }}); 4042292SN/A 0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_LO3); }}); 4052292SN/A 0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_HI3); }}); 4062292SN/A 0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(INTREG_DSP_ACX3); }}); 4072292SN/A 0x16: mftdsp({{ data = xc->readRegOtherThread(INTREG_DSP_CONTROL); }}); 4082292SN/A default: CP0Unimpl::unknown(); 4092292SN/A } 4102292SN/A 0x2: decode MT_H { 4112292SN/A 0x0: mftc1({{ data = xc->readRegOtherThread(RT + 4122292SN/A FP_Base_DepTag); 4132292SN/A }}); 4142292SN/A 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + 4152292SN/A FP_Base_DepTag); 41610239Sbinhpham@cs.rutgers.edu }}); 4172292SN/A } 41810239Sbinhpham@cs.rutgers.edu 0x3: cftc1({{ 41910239Sbinhpham@cs.rutgers.edu uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR + 42010239Sbinhpham@cs.rutgers.edu FP_Base_DepTag); 42110239Sbinhpham@cs.rutgers.edu switch (RT) { 42210239Sbinhpham@cs.rutgers.edu case 0: 4232292SN/A data = xc->readRegOtherThread(FLOATREG_FIR + 42410239Sbinhpham@cs.rutgers.edu Ctrl_Base_DepTag); 42510239Sbinhpham@cs.rutgers.edu break; 42610239Sbinhpham@cs.rutgers.edu case 25: 42710239Sbinhpham@cs.rutgers.edu data = (fcsr_val & 0xFE000000 >> 24) | 42810239Sbinhpham@cs.rutgers.edu (fcsr_val & 0x00800000 >> 23); 42910239Sbinhpham@cs.rutgers.edu break; 43010239Sbinhpham@cs.rutgers.edu case 26: 43110239Sbinhpham@cs.rutgers.edu data = fcsr_val & 0x0003F07C; 43210239Sbinhpham@cs.rutgers.edu break; 43310239Sbinhpham@cs.rutgers.edu case 28: 4342292SN/A data = (fcsr_val & 0x00000F80) | 4352292SN/A (fcsr_val & 0x01000000 >> 21) | 4368545Ssaidi@eecs.umich.edu (fcsr_val & 0x00000003); 4378545Ssaidi@eecs.umich.edu break; 4388545Ssaidi@eecs.umich.edu case 31: 4398545Ssaidi@eecs.umich.edu data = fcsr_val; 44010030SAli.Saidi@ARM.com break; 4418545Ssaidi@eecs.umich.edu default: 4429383SAli.Saidi@ARM.com fatal("FP Control Value (%d) Not Valid"); 4439383SAli.Saidi@ARM.com } 4449383SAli.Saidi@ARM.com }}); 4459383SAli.Saidi@ARM.com default: CP0Unimpl::unknown(); 44610030SAli.Saidi@ARM.com } 4479383SAli.Saidi@ARM.com } 4489383SAli.Saidi@ARM.com } 4499383SAli.Saidi@ARM.com 4509383SAli.Saidi@ARM.com format MT_MTTR { 4519383SAli.Saidi@ARM.com // Decode MIPS MT MTTR instruction into sub-instructions 4529383SAli.Saidi@ARM.com 0xC: decode MT_U { 4539383SAli.Saidi@ARM.com 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, 45410030SAli.Saidi@ARM.com Rt); 45510030SAli.Saidi@ARM.com }}); 45610030SAli.Saidi@ARM.com 0x1: decode SEL { 45710030SAli.Saidi@ARM.com 0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }}); 45810030SAli.Saidi@ARM.com 0x1: decode RT { 45910030SAli.Saidi@ARM.com 0x0: mttlo_dsp0({{ xc->setRegOtherThread(INTREG_DSP_LO0, Rt); 46010030SAli.Saidi@ARM.com }}); 46110030SAli.Saidi@ARM.com 0x1: mtthi_dsp0({{ xc->setRegOtherThread(INTREG_DSP_HI0, 46210030SAli.Saidi@ARM.com Rt); 46310030SAli.Saidi@ARM.com }}); 46410030SAli.Saidi@ARM.com 0x2: mttacx_dsp0({{ xc->setRegOtherThread(INTREG_DSP_ACX0, 4658545Ssaidi@eecs.umich.edu Rt); 4668545Ssaidi@eecs.umich.edu }}); 4678545Ssaidi@eecs.umich.edu 0x4: mttlo_dsp1({{ xc->setRegOtherThread(INTREG_DSP_LO1, 46810030SAli.Saidi@ARM.com Rt); 4698545Ssaidi@eecs.umich.edu }}); 4708545Ssaidi@eecs.umich.edu 0x5: mtthi_dsp1({{ xc->setRegOtherThread(INTREG_DSP_HI1, 47110149Smarco.elver@ed.ac.uk Rt); 47210149Smarco.elver@ed.ac.uk }}); 4738545Ssaidi@eecs.umich.edu 0x6: mttacx_dsp1({{ xc->setRegOtherThread(INTREG_DSP_ACX1, 4748545Ssaidi@eecs.umich.edu Rt); 4758545Ssaidi@eecs.umich.edu }}); 4769046SAli.Saidi@ARM.com 0x8: mttlo_dsp2({{ xc->setRegOtherThread(INTREG_DSP_LO2, 4778545Ssaidi@eecs.umich.edu Rt); 4788545Ssaidi@eecs.umich.edu }}); 4798545Ssaidi@eecs.umich.edu 0x9: mtthi_dsp2({{ xc->setRegOtherThread(INTREG_DSP_HI2, 4808545Ssaidi@eecs.umich.edu Rt); 4818545Ssaidi@eecs.umich.edu }}); 4828545Ssaidi@eecs.umich.edu 0x10: mttacx_dsp2({{ xc->setRegOtherThread(INTREG_DSP_ACX2, 4838545Ssaidi@eecs.umich.edu Rt); 4848545Ssaidi@eecs.umich.edu }}); 48510149Smarco.elver@ed.ac.uk 0x12: mttlo_dsp3({{ xc->setRegOtherThread(INTREG_DSP_LO3, 48610149Smarco.elver@ed.ac.uk Rt); 48710149Smarco.elver@ed.ac.uk }}); 48810149Smarco.elver@ed.ac.uk 0x13: mtthi_dsp3({{ xc->setRegOtherThread(INTREG_DSP_HI3, 48910149Smarco.elver@ed.ac.uk Rt); 49010149Smarco.elver@ed.ac.uk }}); 49110149Smarco.elver@ed.ac.uk 0x14: mttacx_dsp3({{ xc->setRegOtherThread(INTREG_DSP_ACX3, Rt); 49210149Smarco.elver@ed.ac.uk }}); 4938545Ssaidi@eecs.umich.edu 0x16: mttdsp({{ xc->setRegOtherThread(INTREG_DSP_CONTROL, Rt); }}); 49410030SAli.Saidi@ARM.com default: CP0Unimpl::unknown(); 4958545Ssaidi@eecs.umich.edu 4968545Ssaidi@eecs.umich.edu } 4978545Ssaidi@eecs.umich.edu 0x2: mttc1({{ 4988545Ssaidi@eecs.umich.edu uint64_t data = xc->readRegOtherThread(RD + 49910030SAli.Saidi@ARM.com FP_Base_DepTag); 50010030SAli.Saidi@ARM.com data = insertBits(data, MT_H ? 63 : 31, 50110030SAli.Saidi@ARM.com MT_H ? 32 : 0, Rt); 50210030SAli.Saidi@ARM.com xc->setRegOtherThread(RD + FP_Base_DepTag, 50310030SAli.Saidi@ARM.com data); 50410030SAli.Saidi@ARM.com }}); 50510030SAli.Saidi@ARM.com 0x3: cttc1({{ 50610030SAli.Saidi@ARM.com uint32_t data; 50710030SAli.Saidi@ARM.com switch (RD) { 5088545Ssaidi@eecs.umich.edu case 25: 5098545Ssaidi@eecs.umich.edu data = (Rt_uw<7:1> << 25) | // move 31-25 5108545Ssaidi@eecs.umich.edu (FCSR & 0x01000000) | // bit 24 5119046SAli.Saidi@ARM.com (FCSR & 0x004FFFFF); // bit 22-0 5128545Ssaidi@eecs.umich.edu break; 5138545Ssaidi@eecs.umich.edu case 26: 5148545Ssaidi@eecs.umich.edu data = (FCSR & 0xFFFC0000) | // move 31-18 5158545Ssaidi@eecs.umich.edu Rt_uw<17:12> << 12 | // bit 17-12 5168545Ssaidi@eecs.umich.edu (FCSR & 0x00000F80) << 7 | // bit 11-7 5178545Ssaidi@eecs.umich.edu Rt_uw<6:2> << 2 | // bit 6-2 5188545Ssaidi@eecs.umich.edu (FCSR & 0x00000002); // bit 1...0 5198545Ssaidi@eecs.umich.edu break; 5202292SN/A case 28: 5218199SAli.Saidi@ARM.com data = (FCSR & 0xFE000000) | // move 31-25 5228199SAli.Saidi@ARM.com Rt_uw<2:2> << 24 | // bit 24 5238199SAli.Saidi@ARM.com (FCSR & 0x00FFF000) << 23 | // bit 23-12 5248199SAli.Saidi@ARM.com Rt_uw<11:7> << 7 | // bit 24 5258199SAli.Saidi@ARM.com (FCSR & 0x000007E) | 5268199SAli.Saidi@ARM.com Rt_uw<1:0>; // bit 22-0 5278199SAli.Saidi@ARM.com break; 5288199SAli.Saidi@ARM.com case 31: 5298199SAli.Saidi@ARM.com data = Rt_uw; 5308199SAli.Saidi@ARM.com break; 5318199SAli.Saidi@ARM.com default: 5328199SAli.Saidi@ARM.com panic("FP Control Value (%d) " 5339046SAli.Saidi@ARM.com "Not Available. Ignoring " 5348199SAli.Saidi@ARM.com "Access to Floating Control " 5358199SAli.Saidi@ARM.com "S""tatus Register", FS); 5368199SAli.Saidi@ARM.com } 5378199SAli.Saidi@ARM.com xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); 5388199SAli.Saidi@ARM.com }}); 5398199SAli.Saidi@ARM.com default: CP0Unimpl::unknown(); 5408199SAli.Saidi@ARM.com } 5418199SAli.Saidi@ARM.com } 5428272SAli.Saidi@ARM.com } 5438545Ssaidi@eecs.umich.edu 0xB: decode RD { 5448545Ssaidi@eecs.umich.edu format MT_Control { 5458545Ssaidi@eecs.umich.edu 0x0: decode POS { 5468545Ssaidi@eecs.umich.edu 0x0: decode SEL { 5479046SAli.Saidi@ARM.com 0x1: decode SC { 5488545Ssaidi@eecs.umich.edu 0x0: dvpe({{ 5498545Ssaidi@eecs.umich.edu MVPControlReg mvpControl = MVPControl; 5508545Ssaidi@eecs.umich.edu VPEConf0Reg vpeConf0 = VPEConf0; 5518592Sgblack@eecs.umich.edu Rt = MVPControl; 5528592Sgblack@eecs.umich.edu if (vpeConf0.mvp == 1) 5538545Ssaidi@eecs.umich.edu mvpControl.evp = 0; 5548199SAli.Saidi@ARM.com MVPControl = mvpControl; 5558545Ssaidi@eecs.umich.edu }}); 5568199SAli.Saidi@ARM.com 0x1: evpe({{ 5578591Sgblack@eecs.umich.edu MVPControlReg mvpControl = MVPControl; 5588591Sgblack@eecs.umich.edu VPEConf0Reg vpeConf0 = VPEConf0; 5598591Sgblack@eecs.umich.edu Rt = MVPControl; 5608591Sgblack@eecs.umich.edu if (vpeConf0.mvp == 1) 5618545Ssaidi@eecs.umich.edu mvpControl.evp = 1; 5628545Ssaidi@eecs.umich.edu MVPControl = mvpControl; 5638199SAli.Saidi@ARM.com }}); 5648545Ssaidi@eecs.umich.edu default:CP0Unimpl::unknown(); 5658545Ssaidi@eecs.umich.edu } 5669046SAli.Saidi@ARM.com default:CP0Unimpl::unknown(); 5678545Ssaidi@eecs.umich.edu } 5688545Ssaidi@eecs.umich.edu default:CP0Unimpl::unknown(); 5698545Ssaidi@eecs.umich.edu } 5708545Ssaidi@eecs.umich.edu 0x1: decode POS { 5718545Ssaidi@eecs.umich.edu 0xF: decode SEL { 5728545Ssaidi@eecs.umich.edu 0x1: decode SC { 5738545Ssaidi@eecs.umich.edu 0x0: dmt({{ 5748545Ssaidi@eecs.umich.edu VPEControlReg vpeControl = VPEControl; 5758545Ssaidi@eecs.umich.edu Rt = vpeControl; 5768545Ssaidi@eecs.umich.edu vpeControl.te = 0; 5778592Sgblack@eecs.umich.edu VPEControl = vpeControl; 5788592Sgblack@eecs.umich.edu }}); 5798592Sgblack@eecs.umich.edu 0x1: emt({{ 5808545Ssaidi@eecs.umich.edu VPEControlReg vpeControl = VPEControl; 5818545Ssaidi@eecs.umich.edu Rt = vpeControl; 5828545Ssaidi@eecs.umich.edu vpeControl.te = 1; 5838545Ssaidi@eecs.umich.edu VPEControl = vpeControl; 5848591Sgblack@eecs.umich.edu }}); 5858591Sgblack@eecs.umich.edu default:CP0Unimpl::unknown(); 5868591Sgblack@eecs.umich.edu } 5878545Ssaidi@eecs.umich.edu default:CP0Unimpl::unknown(); 5888199SAli.Saidi@ARM.com } 5898199SAli.Saidi@ARM.com default:CP0Unimpl::unknown(); 5908199SAli.Saidi@ARM.com } 5918199SAli.Saidi@ARM.com } 5928199SAli.Saidi@ARM.com 0xC: decode POS { 5938199SAli.Saidi@ARM.com 0x0: decode SC { 5948199SAli.Saidi@ARM.com 0x0: CP0Control::di({{ 5958199SAli.Saidi@ARM.com StatusReg status = Status; 5968199SAli.Saidi@ARM.com ConfigReg config = Config; 5978199SAli.Saidi@ARM.com // Rev 2.0 or beyond? 5988199SAli.Saidi@ARM.com if (config.ar >= 1) { 5998199SAli.Saidi@ARM.com Rt = status; 6002292SN/A status.ie = 0; 6012292SN/A } else { 6024032Sktlim@umich.edu // Enable this else branch once we 6032292SN/A // actually set values for Config on init 6042292SN/A fault = new ReservedInstructionFault(); 6052292SN/A } 6067720Sgblack@eecs.umich.edu Status = status; 6077944SGiacomo.Gabrielli@arm.com }}); 6082292SN/A 0x1: CP0Control::ei({{ 6094032Sktlim@umich.edu StatusReg status = Status; 6104032Sktlim@umich.edu ConfigReg config = Config; 6112669Sktlim@umich.edu if (config.ar >= 1) { 6122292SN/A Rt = status; 6137944SGiacomo.Gabrielli@arm.com status.ie = 1; 6147944SGiacomo.Gabrielli@arm.com } else { 6157944SGiacomo.Gabrielli@arm.com fault = new ReservedInstructionFault(); 6167944SGiacomo.Gabrielli@arm.com } 6177597Sminkyu.jeong@arm.com }}); 6187597Sminkyu.jeong@arm.com default:CP0Unimpl::unknown(); 61910231Ssteve.reinhardt@amd.com } 6202329SN/A } 6212329SN/A default: CP0Unimpl::unknown(); 6222367SN/A } 6232367SN/A format CP0Control { 62410231Ssteve.reinhardt@amd.com 0xA: rdpgpr({{ 6257848SAli.Saidi@ARM.com ConfigReg config = Config; 6267600Sminkyu.jeong@arm.com if (config.ar >= 1) { 6277600Sminkyu.jeong@arm.com // Rev 2 of the architecture 6287600Sminkyu.jeong@arm.com panic("Shadow Sets Not Fully Implemented.\n"); 6294032Sktlim@umich.edu } else { 6303731Sktlim@umich.edu fault = new ReservedInstructionFault(); 6312367SN/A } 6322367SN/A }}); 6332292SN/A 0xE: wrpgpr({{ 6342292SN/A ConfigReg config = Config; 6354032Sktlim@umich.edu if (config.ar >= 1) { 6369046SAli.Saidi@ARM.com // Rev 2 of the architecture 6374032Sktlim@umich.edu panic("Shadow Sets Not Fully Implemented.\n"); 6384032Sktlim@umich.edu } else { 6394032Sktlim@umich.edu fault = new ReservedInstructionFault(); 6408199SAli.Saidi@ARM.com } 6418199SAli.Saidi@ARM.com }}); 6422292SN/A } 6432292SN/A } 6442292SN/A 6452292SN/A //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 6462292SN/A 0x1: decode FUNCTION { 6472292SN/A format CP0Control { 6482292SN/A 0x18: eret({{ 6492292SN/A StatusReg status = Status; 6502292SN/A ConfigReg config = Config; 6512292SN/A SRSCtlReg srsCtl = SRSCtl; 6522292SN/A DPRINTF(MipsPRA,"Restoring PC - %x\n",EPC); 6532292SN/A if (status.erl == 1) { 6542292SN/A status.erl = 0; 6552292SN/A NPC = ErrorEPC; 6562292SN/A // Need to adjust NNPC, otherwise things break 6577720Sgblack@eecs.umich.edu NNPC = ErrorEPC + sizeof(MachInst); 6587720Sgblack@eecs.umich.edu } else { 6592292SN/A NPC = EPC; 6604032Sktlim@umich.edu // Need to adjust NNPC, otherwise things break 6614032Sktlim@umich.edu NNPC = EPC + sizeof(MachInst); 6622292SN/A status.exl = 0; 6632292SN/A if (config.ar >=1 && 6642292SN/A srsCtl.hss > 0 && 6652292SN/A status.bev == 0) { 6662292SN/A srsCtl.css = srsCtl.pss; 6672292SN/A //xc->setShadowSet(srsCtl.pss); 6687944SGiacomo.Gabrielli@arm.com } 6697944SGiacomo.Gabrielli@arm.com } 6707944SGiacomo.Gabrielli@arm.com LLFlag = 0; 6717944SGiacomo.Gabrielli@arm.com Status = status; 67210231Ssteve.reinhardt@amd.com SRSCtl = srsCtl; 6737848SAli.Saidi@ARM.com }}, IsReturn, IsSerializing, IsERET); 6747848SAli.Saidi@ARM.com 6752329SN/A 0x1F: deret({{ 6767782Sminkyu.jeong@arm.com DebugReg debug = Debug; 6777720Sgblack@eecs.umich.edu if (debug.dm == 1) { 6782292SN/A debug.dm = 1; 6792292SN/A debug.iexi = 0; 68010231Ssteve.reinhardt@amd.com NPC = DEPC; 6817782Sminkyu.jeong@arm.com } else { 6827782Sminkyu.jeong@arm.com NPC = NPC; 6837782Sminkyu.jeong@arm.com // Undefined; 6842292SN/A } 6852292SN/A Debug = debug; 6862292SN/A }}, IsReturn, IsSerializing, IsERET); 6872292SN/A } 6882336SN/A format CP0TLB { 6892336SN/A 0x01: tlbr({{ 6902336SN/A MipsISA::PTE *PTEntry = 6912329SN/A xc->tcBase()->getITBPtr()-> 6922292SN/A getEntry(Index & 0x7FFFFFFF); 6932329SN/A if (PTEntry == NULL) { 6942292SN/A fatal("Invalid PTE Entry received on " 6952292SN/A "a TLBR instruction\n"); 6968199SAli.Saidi@ARM.com } 6972292SN/A /* Setup PageMask */ 6982292SN/A // If 1KB pages are not enabled, a read of PageMask 6992292SN/A // must return 0b00 in bits 12, 11 7002292SN/A PageMask = (PTEntry->Mask << 11); 7012292SN/A /* Setup EntryHi */ 7022292SN/A EntryHi = ((PTEntry->VPN << 11) | (PTEntry->asid)); 7032292SN/A /* Setup Entry Lo0 */ 7042292SN/A EntryLo0 = ((PTEntry->PFN0 << 6) | 7052292SN/A (PTEntry->C0 << 3) | 7067720Sgblack@eecs.umich.edu (PTEntry->D0 << 2) | 7077720Sgblack@eecs.umich.edu (PTEntry->V0 << 1) | 7082292SN/A PTEntry->G); 7092292SN/A /* Setup Entry Lo1 */ 7102292SN/A EntryLo1 = ((PTEntry->PFN1 << 6) | 7112292SN/A (PTEntry->C1 << 3) | 7122292SN/A (PTEntry->D1 << 2) | 7132292SN/A (PTEntry->V1 << 1) | 7142292SN/A PTEntry->G); 7152292SN/A }}); // Need to hook up to TLB 7162292SN/A 7172292SN/A 0x02: tlbwi({{ 7182292SN/A //Create PTE 7192292SN/A MipsISA::PTE newEntry; 7202292SN/A //Write PTE 7212292SN/A newEntry.Mask = (Addr)(PageMask >> 11); 7222292SN/A newEntry.VPN = (Addr)(EntryHi >> 11); 7232292SN/A /* PageGrain _ ESP Config3 _ SP */ 7242292SN/A if (bits(PageGrain, 28) == 0 || bits(Config3, 4) ==0) { 7252292SN/A // If 1KB pages are *NOT* enabled, lowest bits of 7262292SN/A // the mask are 0b11 for TLB writes 7272292SN/A newEntry.Mask |= 0x3; 7282292SN/A // Reset bits 0 and 1 if 1KB pages are not enabled 7292292SN/A newEntry.VPN &= 0xFFFFFFFC; 7302292SN/A } 7312292SN/A newEntry.asid = (uint8_t)(EntryHi & 0xFF); 7322292SN/A 7332292SN/A newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 7342292SN/A newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 7352292SN/A newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 7362292SN/A newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 7372329SN/A newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 7382329SN/A newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 7392292SN/A newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 7402292SN/A newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 7412292SN/A newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 7422292SN/A /* Now, compute the AddrShiftAmount and OffsetMask - 7432292SN/A TLB optimizations */ 7447720Sgblack@eecs.umich.edu /* Addr Shift Amount for 1KB or larger pages */ 7457720Sgblack@eecs.umich.edu if ((newEntry.Mask & 0xFFFF) == 3) { 7462292SN/A newEntry.AddrShiftAmount = 12; 7472292SN/A } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 7482292SN/A newEntry.AddrShiftAmount = 10; 7492292SN/A } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 7502292SN/A newEntry.AddrShiftAmount = 14; 7512292SN/A } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 7522292SN/A newEntry.AddrShiftAmount = 16; 7532292SN/A } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 7542292SN/A newEntry.AddrShiftAmount = 18; 7552292SN/A } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 7562292SN/A newEntry.AddrShiftAmount = 20; 7572292SN/A } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 7582292SN/A newEntry.AddrShiftAmount = 22; 7596974Stjones1@inf.ed.ac.uk } else if ((newEntry.Mask & 0xF000) == 0x3000) { 7606974Stjones1@inf.ed.ac.uk newEntry.AddrShiftAmount = 24; 7616974Stjones1@inf.ed.ac.uk } else if ((newEntry.Mask & 0xC000) == 0xC000) { 7626974Stjones1@inf.ed.ac.uk newEntry.AddrShiftAmount = 26; 7636974Stjones1@inf.ed.ac.uk } else if ((newEntry.Mask & 0x30000) == 0x30000) { 7646974Stjones1@inf.ed.ac.uk newEntry.AddrShiftAmount = 28; 7656974Stjones1@inf.ed.ac.uk } else { 7666974Stjones1@inf.ed.ac.uk fatal("Invalid Mask Pattern Detected!\n"); 7676974Stjones1@inf.ed.ac.uk } 7686974Stjones1@inf.ed.ac.uk newEntry.OffsetMask = 7696974Stjones1@inf.ed.ac.uk (1 << newEntry.AddrShiftAmount) - 1; 7706974Stjones1@inf.ed.ac.uk 7716974Stjones1@inf.ed.ac.uk MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 7726974Stjones1@inf.ed.ac.uk Config3Reg config3 = Config3; 7736974Stjones1@inf.ed.ac.uk PageGrainReg pageGrain = PageGrain; 7746974Stjones1@inf.ed.ac.uk int SP = 0; 7752292SN/A if (bits(config3, config3.sp) == 1 && 7762292SN/A bits(pageGrain, pageGrain.esp) == 1) { 7776974Stjones1@inf.ed.ac.uk SP = 1; 7786974Stjones1@inf.ed.ac.uk } 7796974Stjones1@inf.ed.ac.uk Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); 7806974Stjones1@inf.ed.ac.uk }}); 7816974Stjones1@inf.ed.ac.uk 0x06: tlbwr({{ 7826974Stjones1@inf.ed.ac.uk //Create PTE 7832292SN/A MipsISA::PTE newEntry; 7842292SN/A //Write PTE 7852292SN/A newEntry.Mask = (Addr)(PageMask >> 11); 7862292SN/A newEntry.VPN = (Addr)(EntryHi >> 11); 7878727Snilay@cs.wisc.edu /* PageGrain _ ESP Config3 _ SP */ 7882292SN/A if (bits(PageGrain, 28) == 0 || 7892292SN/A bits(Config3, 4) == 0) { 7902907Sktlim@umich.edu // If 1KB pages are *NOT* enabled, lowest bits of 7912678Sktlim@umich.edu // the mask are 0b11 for TLB writes 7922678Sktlim@umich.edu newEntry.Mask |= 0x3; 7932678Sktlim@umich.edu // Reset bits 0 and 1 if 1KB pages are not enabled 7942678Sktlim@umich.edu newEntry.VPN &= 0xFFFFFFFC; 7952678Sktlim@umich.edu } 7962329SN/A newEntry.asid = (uint8_t)(EntryHi & 0xFF); 7972329SN/A 7982292SN/A newEntry.PFN0 = (Addr)(EntryLo0 >> 6); 7992292SN/A newEntry.PFN1 = (Addr)(EntryLo1 >> 6); 8002292SN/A newEntry.D0 = (bool)((EntryLo0 >> 2) & 1); 8012292SN/A newEntry.D1 = (bool)((EntryLo1 >> 2) & 1); 8022292SN/A newEntry.V1 = (bool)((EntryLo1 >> 1) & 1); 8032292SN/A newEntry.V0 = (bool)((EntryLo0 >> 1) & 1); 8042292SN/A newEntry.G = (bool)((EntryLo0 & EntryLo1) & 1); 8052678Sktlim@umich.edu newEntry.C0 = (uint8_t)((EntryLo0 >> 3) & 0x7); 8062292SN/A newEntry.C1 = (uint8_t)((EntryLo1 >> 3) & 0x7); 8072292SN/A /* Now, compute the AddrShiftAmount and OffsetMask - 8082292SN/A TLB optimizations */ 8092292SN/A /* Addr Shift Amount for 1KB or larger pages */ 8102292SN/A if ((newEntry.Mask & 0xFFFF) == 3){ 8112292SN/A newEntry.AddrShiftAmount = 12; 8122292SN/A } else if ((newEntry.Mask & 0xFFFF) == 0x0000) { 8132292SN/A newEntry.AddrShiftAmount = 10; 8142292SN/A } else if ((newEntry.Mask & 0xFFFC) == 0x000C) { 8152292SN/A newEntry.AddrShiftAmount = 14; 8162292SN/A } else if ((newEntry.Mask & 0xFFF0) == 0x0030) { 8176974Stjones1@inf.ed.ac.uk newEntry.AddrShiftAmount = 16; 8186974Stjones1@inf.ed.ac.uk } else if ((newEntry.Mask & 0xFFC0) == 0x00C0) { 8196974Stjones1@inf.ed.ac.uk newEntry.AddrShiftAmount = 18; 8206974Stjones1@inf.ed.ac.uk } else if ((newEntry.Mask & 0xFF00) == 0x0300) { 8216974Stjones1@inf.ed.ac.uk newEntry.AddrShiftAmount = 20; 8222669Sktlim@umich.edu } else if ((newEntry.Mask & 0xFC00) == 0x0C00) { 8232669Sktlim@umich.edu newEntry.AddrShiftAmount = 22; 8242669Sktlim@umich.edu } else if ((newEntry.Mask & 0xF000) == 0x3000) { 8258481Sgblack@eecs.umich.edu newEntry.AddrShiftAmount = 24; 8268481Sgblack@eecs.umich.edu } else if ((newEntry.Mask & 0xC000) == 0xC000) { 8278481Sgblack@eecs.umich.edu newEntry.AddrShiftAmount = 26; 8282292SN/A } else if ((newEntry.Mask & 0x30000) == 0x30000) { 8292292SN/A newEntry.AddrShiftAmount = 28; 8302669Sktlim@umich.edu } else { 83110031SAli.Saidi@ARM.com fatal("Invalid Mask Pattern Detected!\n"); 8323772Sgblack@eecs.umich.edu } 83310031SAli.Saidi@ARM.com newEntry.OffsetMask = 83410031SAli.Saidi@ARM.com (1 << newEntry.AddrShiftAmount) - 1; 83510031SAli.Saidi@ARM.com 83610031SAli.Saidi@ARM.com MipsISA::TLB *Ptr = xc->tcBase()->getITBPtr(); 8372669Sktlim@umich.edu Config3Reg config3 = Config3; 8384878Sstever@eecs.umich.edu PageGrainReg pageGrain = PageGrain; 8394878Sstever@eecs.umich.edu int SP = 0; 8406102Sgblack@eecs.umich.edu if (bits(config3, config3.sp) == 1 && 8416974Stjones1@inf.ed.ac.uk bits(pageGrain, pageGrain.esp) == 1) { 8426974Stjones1@inf.ed.ac.uk SP = 1; 8432292SN/A } 8442678Sktlim@umich.edu Ptr->insertAt(newEntry, Random, SP); 8452678Sktlim@umich.edu }}); 8462678Sktlim@umich.edu 8472678Sktlim@umich.edu 0x08: tlbp({{ 8486974Stjones1@inf.ed.ac.uk Config3Reg config3 = Config3; 8496974Stjones1@inf.ed.ac.uk PageGrainReg pageGrain = PageGrain; 8506974Stjones1@inf.ed.ac.uk EntryHiReg entryHi = EntryHi; 8516974Stjones1@inf.ed.ac.uk int tlbIndex; 8528949Sandreas.hansson@arm.com Addr vpn; 8536974Stjones1@inf.ed.ac.uk if (pageGrain.esp == 1 && config3.sp ==1) { 8546974Stjones1@inf.ed.ac.uk vpn = EntryHi >> 11; 8556974Stjones1@inf.ed.ac.uk } else { 8566974Stjones1@inf.ed.ac.uk // Mask off lower 2 bits 8578949Sandreas.hansson@arm.com vpn = ((EntryHi >> 11) & 0xFFFFFFFC); 8588949Sandreas.hansson@arm.com } 8596974Stjones1@inf.ed.ac.uk tlbIndex = xc->tcBase()->getITBPtr()-> 8606974Stjones1@inf.ed.ac.uk probeEntry(vpn, entryHi.asid); 8616974Stjones1@inf.ed.ac.uk // Check TLB for entry matching EntryHi 8626974Stjones1@inf.ed.ac.uk if (tlbIndex != -1) { 8636974Stjones1@inf.ed.ac.uk Index = tlbIndex; 8646974Stjones1@inf.ed.ac.uk } else { 8656974Stjones1@inf.ed.ac.uk // else, set Index = 1 << 31 8666974Stjones1@inf.ed.ac.uk Index = (1 << 31); 8676974Stjones1@inf.ed.ac.uk } 8686974Stjones1@inf.ed.ac.uk }}); 8696974Stjones1@inf.ed.ac.uk } 8706974Stjones1@inf.ed.ac.uk format CP0Unimpl { 8716974Stjones1@inf.ed.ac.uk 0x20: wait(); 8726974Stjones1@inf.ed.ac.uk } 8732678Sktlim@umich.edu default: CP0Unimpl::unknown(); 8747720Sgblack@eecs.umich.edu } 8752292SN/A } 8767720Sgblack@eecs.umich.edu 8773797Sgblack@eecs.umich.edu //Table A-13 MIPS32 COP1 Encoding of rs Field 8783221Sktlim@umich.edu 0x1: decode RS_MSB { 8792292SN/A 0x0: decode RS_HI { 8802693Sktlim@umich.edu 0x0: decode RS_LO { 8814350Sgblack@eecs.umich.edu format CP1Control { 8826974Stjones1@inf.ed.ac.uk 0x0: mfc1 ({{ Rt_uw = Fs_uw; }}); 8833326Sktlim@umich.edu 8843326Sktlim@umich.edu 0x2: cfc1({{ 8853326Sktlim@umich.edu switch (FS) { 8869046SAli.Saidi@ARM.com case 0: 88710030SAli.Saidi@ARM.com Rt = FIR; 8889046SAli.Saidi@ARM.com break; 8893326Sktlim@umich.edu case 25: 8903326Sktlim@umich.edu Rt = (FCSR & 0xFE000000) >> 24 | 8913326Sktlim@umich.edu (FCSR & 0x00800000) >> 23; 8923326Sktlim@umich.edu break; 8933326Sktlim@umich.edu case 26: 8943326Sktlim@umich.edu Rt = (FCSR & 0x0003F07C); 8953326Sktlim@umich.edu break; 8967823Ssteve.reinhardt@amd.com case 28: 8978887Sgeoffrey.blake@arm.com Rt = (FCSR & 0x00000F80) | 8988887Sgeoffrey.blake@arm.com (FCSR & 0x01000000) >> 21 | 8998887Sgeoffrey.blake@arm.com (FCSR & 0x00000003); 9008887Sgeoffrey.blake@arm.com break; 9018887Sgeoffrey.blake@arm.com case 31: 9028887Sgeoffrey.blake@arm.com Rt = FCSR; 9033326Sktlim@umich.edu break; 9043326Sktlim@umich.edu default: 9053326Sktlim@umich.edu warn("FP Control Value (%d) Not Valid"); 9062693Sktlim@umich.edu } 9072693Sktlim@umich.edu }}); 9082693Sktlim@umich.edu 9092693Sktlim@umich.edu 0x3: mfhc1({{ Rt_uw = Fs_ud<63:32>; }}); 9102693Sktlim@umich.edu 9112693Sktlim@umich.edu 0x4: mtc1({{ Fs_uw = Rt_uw; }}); 9128481Sgblack@eecs.umich.edu 9138481Sgblack@eecs.umich.edu 0x6: ctc1({{ 9148481Sgblack@eecs.umich.edu switch (FS) { 9158481Sgblack@eecs.umich.edu case 25: 9168481Sgblack@eecs.umich.edu FCSR = (Rt_uw<7:1> << 25) | // move 31-25 9178481Sgblack@eecs.umich.edu (FCSR & 0x01000000) | // bit 24 9188481Sgblack@eecs.umich.edu (FCSR & 0x004FFFFF); // bit 22-0 9198481Sgblack@eecs.umich.edu break; 9208481Sgblack@eecs.umich.edu case 26: 9218481Sgblack@eecs.umich.edu FCSR = (FCSR & 0xFFFC0000) | // move 31-18 9228481Sgblack@eecs.umich.edu Rt_uw<17:12> << 12 | // bit 17-12 9238481Sgblack@eecs.umich.edu (FCSR & 0x00000F80) << 7 | // bit 11-7 9248481Sgblack@eecs.umich.edu Rt_uw<6:2> << 2 | // bit 6-2 9258481Sgblack@eecs.umich.edu (FCSR & 0x00000002); // bit 1-0 9268481Sgblack@eecs.umich.edu break; 9278481Sgblack@eecs.umich.edu case 28: 9288481Sgblack@eecs.umich.edu FCSR = (FCSR & 0xFE000000) | // move 31-25 9298481Sgblack@eecs.umich.edu Rt_uw<2:2> << 24 | // bit 24 9308481Sgblack@eecs.umich.edu (FCSR & 0x00FFF000) << 23 | // bit 23-12 9318481Sgblack@eecs.umich.edu Rt_uw<11:7> << 7 | // bit 24 9328481Sgblack@eecs.umich.edu (FCSR & 0x000007E) | 9334032Sktlim@umich.edu Rt_uw<1:0>; // bit 22-0 9343221Sktlim@umich.edu break; 9353221Sktlim@umich.edu case 31: 9366974Stjones1@inf.ed.ac.uk FCSR = Rt_uw; 9376974Stjones1@inf.ed.ac.uk break; 9388481Sgblack@eecs.umich.edu 9396974Stjones1@inf.ed.ac.uk default: 9406974Stjones1@inf.ed.ac.uk panic("FP Control Value (%d) " 9416974Stjones1@inf.ed.ac.uk "Not Available. Ignoring Access " 9422669Sktlim@umich.edu "to Floating Control Status " 9436974Stjones1@inf.ed.ac.uk "Register", FS); 9446974Stjones1@inf.ed.ac.uk } 9458481Sgblack@eecs.umich.edu }}); 9466974Stjones1@inf.ed.ac.uk 9476974Stjones1@inf.ed.ac.uk 0x7: mthc1({{ 9486974Stjones1@inf.ed.ac.uk uint64_t fs_hi = Rt_uw; 9496974Stjones1@inf.ed.ac.uk uint64_t fs_lo = Fs_ud & 0x0FFFFFFFF; 9506974Stjones1@inf.ed.ac.uk Fs_ud = (fs_hi << 32) | fs_lo; 9516974Stjones1@inf.ed.ac.uk }}); 9526974Stjones1@inf.ed.ac.uk 9536974Stjones1@inf.ed.ac.uk } 9546974Stjones1@inf.ed.ac.uk format CP1Unimpl { 9556974Stjones1@inf.ed.ac.uk 0x1: dmfc1(); 9566974Stjones1@inf.ed.ac.uk 0x5: dmtc1(); 9576974Stjones1@inf.ed.ac.uk } 9586974Stjones1@inf.ed.ac.uk } 9596974Stjones1@inf.ed.ac.uk 9606974Stjones1@inf.ed.ac.uk 0x1: decode RS_LO { 9616974Stjones1@inf.ed.ac.uk 0x0: decode ND { 9626974Stjones1@inf.ed.ac.uk format Branch { 9636974Stjones1@inf.ed.ac.uk 0x0: decode TF { 9646974Stjones1@inf.ed.ac.uk 0x0: bc1f({{ 9656974Stjones1@inf.ed.ac.uk cond = getCondCode(FCSR, BRANCH_CC) == 0; 9666974Stjones1@inf.ed.ac.uk }}); 9676974Stjones1@inf.ed.ac.uk 0x1: bc1t({{ 9686974Stjones1@inf.ed.ac.uk cond = getCondCode(FCSR, BRANCH_CC) == 1; 9696974Stjones1@inf.ed.ac.uk }}); 9702292SN/A } 9712292SN/A 0x1: decode TF { 9722292SN/A 0x0: bc1fl({{ 9732292SN/A cond = getCondCode(FCSR, BRANCH_CC) == 0; 9742292SN/A }}, Likely); 9752292SN/A 0x1: bc1tl({{ 9762292SN/A cond = getCondCode(FCSR, BRANCH_CC) == 1; 9772292SN/A }}, Likely); 9782292SN/A } 9792292SN/A } 9802292SN/A } 9812292SN/A format CP1Unimpl { 9822292SN/A 0x1: bc1any2(); 9832292SN/A 0x2: bc1any4(); 9842292SN/A default: unknown(); 9852292SN/A } 9862292SN/A } 9872292SN/A } 9882292SN/A 9892292SN/A 0x1: decode RS_HI { 9902292SN/A 0x2: decode RS_LO { 9912292SN/A //Table A-14 MIPS32 COP1 Encoding of Function Field When 9922292SN/A //rs=S (( single-precision floating point)) 9932292SN/A 0x0: decode FUNCTION_HI { 9942292SN/A 0x0: decode FUNCTION_LO { 9952292SN/A format FloatOp { 9962292SN/A 0x0: add_s({{ Fd_sf = Fs_sf + Ft_sf; }}); 9972292SN/A 0x1: sub_s({{ Fd_sf = Fs_sf - Ft_sf; }}); 9982329SN/A 0x2: mul_s({{ Fd_sf = Fs_sf * Ft_sf; }}); 9992292SN/A 0x3: div_s({{ Fd_sf = Fs_sf / Ft_sf; }}); 10002292SN/A 0x4: sqrt_s({{ Fd_sf = sqrt(Fs_sf); }}); 10012292SN/A 0x5: abs_s({{ Fd_sf = fabs(Fs_sf); }}); 10022292SN/A 0x7: neg_s({{ Fd_sf = -Fs_sf; }}); 10032292SN/A } 10047720Sgblack@eecs.umich.edu 0x6: BasicOp::mov_s({{ Fd_sf = Fs_sf; }}); 10052292SN/A } 10067720Sgblack@eecs.umich.edu 0x1: decode FUNCTION_LO { 10072292SN/A format FloatConvertOp { 10082292SN/A 0x0: round_l_s({{ val = Fs_sf; }}, 10092292SN/A ToLong, Round); 10102292SN/A 0x1: trunc_l_s({{ val = Fs_sf; }}, 10112292SN/A ToLong, Trunc); 10122292SN/A 0x2: ceil_l_s({{ val = Fs_sf;}}, 10132292SN/A ToLong, Ceil); 10142292SN/A 0x3: floor_l_s({{ val = Fs_sf; }}, 10152329SN/A ToLong, Floor); 10162731Sktlim@umich.edu 0x4: round_w_s({{ val = Fs_sf; }}, 10172292SN/A ToWord, Round); 10182292SN/A 0x5: trunc_w_s({{ val = Fs_sf; }}, 10192292SN/A ToWord, Trunc); 10202292SN/A 0x6: ceil_w_s({{ val = Fs_sf; }}, 10212292SN/A ToWord, Ceil); 10222292SN/A 0x7: floor_w_s({{ val = Fs_sf; }}, 10232292SN/A ToWord, Floor); 10242727Sktlim@umich.edu } 10252292SN/A } 10262292SN/A 10272292SN/A 0x2: decode FUNCTION_LO { 10282292SN/A 0x1: decode MOVCF { 10292292SN/A format BasicOp { 10302292SN/A 0x0: movf_s({{ 10312292SN/A Fd = (getCondCode(FCSR,CC) == 0) ? 10322292SN/A Fs : Fd; 10332292SN/A }}); 10342292SN/A 0x1: movt_s({{ 10354032Sktlim@umich.edu Fd = (getCondCode(FCSR,CC) == 1) ? 10364032Sktlim@umich.edu Fs : Fd; 10374032Sktlim@umich.edu }}); 10384032Sktlim@umich.edu } 10392292SN/A } 10402292SN/A 10412292SN/A format BasicOp { 10422292SN/A 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 10432292SN/A 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 10442329SN/A } 10452292SN/A 10462292SN/A format FloatOp { 10472292SN/A 0x5: recip_s({{ Fd = 1 / Fs; }}); 10482292SN/A 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs); }}); 10497720Sgblack@eecs.umich.edu } 10502292SN/A format CP1Unimpl { 10517720Sgblack@eecs.umich.edu default: unknown(); 10522292SN/A } 10532292SN/A } 10542329SN/A 0x3: CP1Unimpl::unknown(); 10552329SN/A 10562292SN/A 0x4: decode FUNCTION_LO { 10572292SN/A format FloatConvertOp { 10582292SN/A 0x1: cvt_d_s({{ val = Fs_sf; }}, ToDouble); 10592292SN/A 0x4: cvt_w_s({{ val = Fs_sf; }}, ToWord); 10602292SN/A 0x5: cvt_l_s({{ val = Fs_sf; }}, ToLong); 10612292SN/A } 10622292SN/A 10632329SN/A 0x6: FloatOp::cvt_ps_s({{ 10642731Sktlim@umich.edu Fd_ud = (uint64_t) Fs_uw << 32 | 10652292SN/A (uint64_t) Ft_uw; 10662292SN/A }}); 10672292SN/A format CP1Unimpl { 10684032Sktlim@umich.edu default: unknown(); 10694032Sktlim@umich.edu } 10704032Sktlim@umich.edu } 10714032Sktlim@umich.edu 0x5: CP1Unimpl::unknown(); 10726974Stjones1@inf.ed.ac.uk 10736974Stjones1@inf.ed.ac.uk 0x6: decode FUNCTION_LO { 10746974Stjones1@inf.ed.ac.uk format FloatCompareOp { 10756974Stjones1@inf.ed.ac.uk 0x0: c_f_s({{ cond = 0; }}, 10766974Stjones1@inf.ed.ac.uk SinglePrecision, UnorderedFalse); 10776974Stjones1@inf.ed.ac.uk 0x1: c_un_s({{ cond = 0; }}, 10786974Stjones1@inf.ed.ac.uk SinglePrecision, UnorderedTrue); 10794032Sktlim@umich.edu 0x2: c_eq_s({{ cond = (Fs_sf == Ft_sf); }}, 10802292SN/A UnorderedFalse); 10812292SN/A 0x3: c_ueq_s({{ cond = (Fs_sf == Ft_sf); }}, 10822292SN/A UnorderedTrue); 10832292SN/A 0x4: c_olt_s({{ cond = (Fs_sf < Ft_sf); }}, 10842292SN/A UnorderedFalse); 10852292SN/A 0x5: c_ult_s({{ cond = (Fs_sf < Ft_sf); }}, 10862292SN/A UnorderedTrue); 10872727Sktlim@umich.edu 0x6: c_ole_s({{ cond = (Fs_sf <= Ft_sf); }}, 10882292SN/A UnorderedFalse); 10892292SN/A 0x7: c_ule_s({{ cond = (Fs_sf <= Ft_sf); }}, 10902292SN/A UnorderedTrue); 10912292SN/A } 10922292SN/A } 10933349Sbinkertn@umich.edu 10942693Sktlim@umich.edu 0x7: decode FUNCTION_LO { 10952693Sktlim@umich.edu format FloatCompareOp { 10962693Sktlim@umich.edu 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 10972693Sktlim@umich.edu UnorderedFalse, QnanException); 10982693Sktlim@umich.edu 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 10992693Sktlim@umich.edu UnorderedTrue, QnanException); 11002693Sktlim@umich.edu 0x2: c_seq_s({{ cond = (Fs_sf == Ft_sf); }}, 11012693Sktlim@umich.edu UnorderedFalse, QnanException); 11022693Sktlim@umich.edu 0x3: c_ngl_s({{ cond = (Fs_sf == Ft_sf); }}, 11032693Sktlim@umich.edu UnorderedTrue, QnanException); 11042693Sktlim@umich.edu 0x4: c_lt_s({{ cond = (Fs_sf < Ft_sf); }}, 11052693Sktlim@umich.edu UnorderedFalse, QnanException); 11062693Sktlim@umich.edu 0x5: c_nge_s({{ cond = (Fs_sf < Ft_sf); }}, 11072693Sktlim@umich.edu UnorderedTrue, QnanException); 11082693Sktlim@umich.edu 0x6: c_le_s({{ cond = (Fs_sf <= Ft_sf); }}, 11092693Sktlim@umich.edu UnorderedFalse, QnanException); 11108887Sgeoffrey.blake@arm.com 0x7: c_ngt_s({{ cond = (Fs_sf <= Ft_sf); }}, 11112693Sktlim@umich.edu UnorderedTrue, QnanException); 11122732Sktlim@umich.edu } 11132693Sktlim@umich.edu } 11142693Sktlim@umich.edu } 11152693Sktlim@umich.edu 11168727Snilay@cs.wisc.edu //Table A-15 MIPS32 COP1 Encoding of Function Field When 11178727Snilay@cs.wisc.edu //rs=D 11188727Snilay@cs.wisc.edu 0x1: decode FUNCTION_HI { 11198727Snilay@cs.wisc.edu 0x0: decode FUNCTION_LO { 11202693Sktlim@umich.edu format FloatOp { 11212693Sktlim@umich.edu 0x0: add_d({{ Fd_df = Fs_df + Ft_df; }}); 11222693Sktlim@umich.edu 0x1: sub_d({{ Fd_df = Fs_df - Ft_df; }}); 11232693Sktlim@umich.edu 0x2: mul_d({{ Fd_df = Fs_df * Ft_df; }}); 11242693Sktlim@umich.edu 0x3: div_d({{ Fd_df = Fs_df / Ft_df; }}); 11252678Sktlim@umich.edu 0x4: sqrt_d({{ Fd_df = sqrt(Fs_df); }}); 11262678Sktlim@umich.edu 0x5: abs_d({{ Fd_df = fabs(Fs_df); }}); 11272678Sktlim@umich.edu 0x7: neg_d({{ Fd_df = -1 * Fs_df; }}); 11282678Sktlim@umich.edu } 11292678Sktlim@umich.edu 0x6: BasicOp::mov_d({{ Fd_df = Fs_df; }}); 11302678Sktlim@umich.edu } 11312678Sktlim@umich.edu 11322727Sktlim@umich.edu 0x1: decode FUNCTION_LO { 11332678Sktlim@umich.edu format FloatConvertOp { 11342678Sktlim@umich.edu 0x0: round_l_d({{ val = Fs_df; }}, 11352678Sktlim@umich.edu ToLong, Round); 11362678Sktlim@umich.edu 0x1: trunc_l_d({{ val = Fs_df; }}, 11372678Sktlim@umich.edu ToLong, Trunc); 11382678Sktlim@umich.edu 0x2: ceil_l_d({{ val = Fs_df; }}, 11392678Sktlim@umich.edu ToLong, Ceil); 11402678Sktlim@umich.edu 0x3: floor_l_d({{ val = Fs_df; }}, 11412678Sktlim@umich.edu ToLong, Floor); 11422678Sktlim@umich.edu 0x4: round_w_d({{ val = Fs_df; }}, 11432678Sktlim@umich.edu ToWord, Round); 11442678Sktlim@umich.edu 0x5: trunc_w_d({{ val = Fs_df; }}, 11452678Sktlim@umich.edu ToWord, Trunc); 11462678Sktlim@umich.edu 0x6: ceil_w_d({{ val = Fs_df; }}, 11477598Sminkyu.jeong@arm.com ToWord, Ceil); 11487598Sminkyu.jeong@arm.com 0x7: floor_w_d({{ val = Fs_df; }}, 11497598Sminkyu.jeong@arm.com ToWord, Floor); 11502678Sktlim@umich.edu } 11512678Sktlim@umich.edu } 11522678Sktlim@umich.edu 11532678Sktlim@umich.edu 0x2: decode FUNCTION_LO { 11542292SN/A 0x1: decode MOVCF { 11552292SN/A format BasicOp { 11562292SN/A 0x0: movf_d({{ 11572292SN/A Fd_df = (getCondCode(FCSR,CC) == 0) ? 11582292SN/A Fs_df : Fd_df; 11592292SN/A }}); 11602292SN/A 0x1: movt_d({{ 11612292SN/A Fd_df = (getCondCode(FCSR,CC) == 1) ? 11623126Sktlim@umich.edu Fs_df : Fd_df; 11632292SN/A }}); 11642292SN/A } 11652292SN/A } 11662292SN/A 11672292SN/A format BasicOp { 11682292SN/A 0x2: movz_d({{ 11692292SN/A Fd_df = (Rt == 0) ? Fs_df : Fd_df; 11702292SN/A }}); 11712292SN/A 0x3: movn_d({{ 11722292SN/A Fd_df = (Rt != 0) ? Fs_df : Fd_df; 11732292SN/A }}); 11742292SN/A } 11752292SN/A 11762329SN/A format FloatOp { 11772329SN/A 0x5: recip_d({{ Fd_df = 1 / Fs_df; }}); 11782329SN/A 0x6: rsqrt_d({{ Fd_df = 1 / sqrt(Fs_df); }}); 11792292SN/A } 11809527SMatt.Horsnell@arm.com format CP1Unimpl { 11819527SMatt.Horsnell@arm.com default: unknown(); 11829527SMatt.Horsnell@arm.com } 11839527SMatt.Horsnell@arm.com 11849527SMatt.Horsnell@arm.com } 11859527SMatt.Horsnell@arm.com 0x4: decode FUNCTION_LO { 11869527SMatt.Horsnell@arm.com format FloatConvertOp { 11872292SN/A 0x0: cvt_s_d({{ val = Fs_df; }}, ToSingle); 11882292SN/A 0x4: cvt_w_d({{ val = Fs_df; }}, ToWord); 11892292SN/A 0x5: cvt_l_d({{ val = Fs_df; }}, ToLong); 11902292SN/A } 11912292SN/A default: CP1Unimpl::unknown(); 11922292SN/A } 11932292SN/A 11942292SN/A 0x6: decode FUNCTION_LO { 11952292SN/A format FloatCompareOp { 11962316SN/A 0x0: c_f_d({{ cond = 0; }}, 11972316SN/A DoublePrecision, UnorderedFalse); 11982329SN/A 0x1: c_un_d({{ cond = 0; }}, 11998727Snilay@cs.wisc.edu DoublePrecision, UnorderedTrue); 12008727Snilay@cs.wisc.edu 0x2: c_eq_d({{ cond = (Fs_df == Ft_df); }}, 12018727Snilay@cs.wisc.edu UnorderedFalse); 12028727Snilay@cs.wisc.edu 0x3: c_ueq_d({{ cond = (Fs_df == Ft_df); }}, 12032329SN/A UnorderedTrue); 12042329SN/A 0x4: c_olt_d({{ cond = (Fs_df < Ft_df); }}, 12052329SN/A UnorderedFalse); 12062316SN/A 0x5: c_ult_d({{ cond = (Fs_df < Ft_df); }}, 12072732Sktlim@umich.edu UnorderedTrue); 12082316SN/A 0x6: c_ole_d({{ cond = (Fs_df <= Ft_df); }}, 12092292SN/A UnorderedFalse); 12102292SN/A 0x7: c_ule_d({{ cond = (Fs_df <= Ft_df); }}, 12112292SN/A UnorderedTrue); 12126974Stjones1@inf.ed.ac.uk } 12136974Stjones1@inf.ed.ac.uk } 12146974Stjones1@inf.ed.ac.uk 12158975Sandreas.hansson@arm.com 0x7: decode FUNCTION_LO { 12166974Stjones1@inf.ed.ac.uk format FloatCompareOp { 12176974Stjones1@inf.ed.ac.uk 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 12186974Stjones1@inf.ed.ac.uk UnorderedFalse, QnanException); 12196974Stjones1@inf.ed.ac.uk 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 12206974Stjones1@inf.ed.ac.uk UnorderedTrue, QnanException); 12216974Stjones1@inf.ed.ac.uk 0x2: c_seq_d({{ cond = (Fs_df == Ft_df); }}, 12226974Stjones1@inf.ed.ac.uk UnorderedFalse, QnanException); 12236974Stjones1@inf.ed.ac.uk 0x3: c_ngl_d({{ cond = (Fs_df == Ft_df); }}, 12246974Stjones1@inf.ed.ac.uk UnorderedTrue, QnanException); 12256974Stjones1@inf.ed.ac.uk 0x4: c_lt_d({{ cond = (Fs_df < Ft_df); }}, 12266974Stjones1@inf.ed.ac.uk UnorderedFalse, QnanException); 12276974Stjones1@inf.ed.ac.uk 0x5: c_nge_d({{ cond = (Fs_df < Ft_df); }}, 12282693Sktlim@umich.edu UnorderedTrue, QnanException); 12292693Sktlim@umich.edu 0x6: c_le_d({{ cond = (Fs_df <= Ft_df); }}, 12302693Sktlim@umich.edu UnorderedFalse, QnanException); 12312698Sktlim@umich.edu 0x7: c_ngt_d({{ cond = (Fs_df <= Ft_df); }}, 12324985Sktlim@umich.edu UnorderedTrue, QnanException); 12332698Sktlim@umich.edu } 12342693Sktlim@umich.edu } 12358587Snilay@cs.wisc.edu default: CP1Unimpl::unknown(); 12368587Snilay@cs.wisc.edu } 12378587Snilay@cs.wisc.edu 0x2: CP1Unimpl::unknown(); 12388975Sandreas.hansson@arm.com 0x3: CP1Unimpl::unknown(); 12396974Stjones1@inf.ed.ac.uk 0x7: CP1Unimpl::unknown(); 12408133SAli.Saidi@ARM.com 12418133SAli.Saidi@ARM.com //Table A-16 MIPS32 COP1 Encoding of Function 12428133SAli.Saidi@ARM.com //Field When rs=W 12436974Stjones1@inf.ed.ac.uk 0x4: decode FUNCTION { 12446974Stjones1@inf.ed.ac.uk format FloatConvertOp { 12452699Sktlim@umich.edu 0x20: cvt_s_w({{ val = Fs_uw; }}, ToSingle); 12462693Sktlim@umich.edu 0x21: cvt_d_w({{ val = Fs_uw; }}, ToDouble); 12476221Snate@binkert.org 0x26: CP1Unimpl::cvt_ps_w(); 12486974Stjones1@inf.ed.ac.uk } 12496974Stjones1@inf.ed.ac.uk default: CP1Unimpl::unknown(); 12506974Stjones1@inf.ed.ac.uk } 12516974Stjones1@inf.ed.ac.uk 12526974Stjones1@inf.ed.ac.uk //Table A-16 MIPS32 COP1 Encoding of Function Field 12536974Stjones1@inf.ed.ac.uk //When rs=L1 12546974Stjones1@inf.ed.ac.uk //Note: "1. Format type L is legal only if 64-bit 12556974Stjones1@inf.ed.ac.uk //floating point operations are enabled." 12562693Sktlim@umich.edu 0x5: decode FUNCTION_HI { 12572693Sktlim@umich.edu format FloatConvertOp { 12582727Sktlim@umich.edu 0x20: cvt_s_l({{ val = Fs_ud; }}, ToSingle); 12592907Sktlim@umich.edu 0x21: cvt_d_l({{ val = Fs_ud; }}, ToDouble); 12602693Sktlim@umich.edu 0x26: CP1Unimpl::cvt_ps_l(); 12612693Sktlim@umich.edu } 12622693Sktlim@umich.edu default: CP1Unimpl::unknown(); 12632693Sktlim@umich.edu } 12642693Sktlim@umich.edu 12652693Sktlim@umich.edu //Table A-17 MIPS64 COP1 Encoding of Function Field 12662693Sktlim@umich.edu //When rs=PS1 12672693Sktlim@umich.edu //Note: "1. Format type PS is legal only if 64-bit 12682693Sktlim@umich.edu //floating point operations are enabled. " 12692693Sktlim@umich.edu 0x6: decode FUNCTION_HI { 12702292SN/A 0x0: decode FUNCTION_LO { 12719440SAndreas.Sandberg@ARM.com format Float64Op { 12722292SN/A 0x0: add_ps({{ 12732292SN/A Fd1_sf = Fs1_sf + Ft2_sf; 12742292SN/A Fd2_sf = Fs2_sf + Ft2_sf; 12752292SN/A }}); 12762292SN/A 0x1: sub_ps({{ 12772292SN/A Fd1_sf = Fs1_sf - Ft2_sf; 12782292SN/A Fd2_sf = Fs2_sf - Ft2_sf; 12799440SAndreas.Sandberg@ARM.com }}); 12802292SN/A 0x2: mul_ps({{ 12812292SN/A Fd1_sf = Fs1_sf * Ft2_sf; 12822292SN/A Fd2_sf = Fs2_sf * Ft2_sf; 12832292SN/A }}); 12842292SN/A 0x5: abs_ps({{ 12852292SN/A Fd1_sf = fabs(Fs1_sf); 12862292SN/A Fd2_sf = fabs(Fs2_sf); 12879440SAndreas.Sandberg@ARM.com }}); 12882292SN/A 0x6: mov_ps({{ 12892292SN/A Fd1_sf = Fs1_sf; 12902292SN/A Fd2_sf = Fs2_sf; 12912292SN/A }}); 12922292SN/A 0x7: neg_ps({{ 12932292SN/A Fd1_sf = -(Fs1_sf); 12942292SN/A Fd2_sf = -(Fs2_sf); 12959440SAndreas.Sandberg@ARM.com }}); 12962292SN/A default: CP1Unimpl::unknown(); 12972292SN/A } 12982292SN/A } 12992292SN/A 0x1: CP1Unimpl::unknown(); 13002329SN/A 0x2: decode FUNCTION_LO { 13012329SN/A 0x1: decode MOVCF { 13022329SN/A format Float64Op { 13039440SAndreas.Sandberg@ARM.com 0x0: movf_ps({{ 13042329SN/A Fd1 = (getCondCode(FCSR, CC) == 0) ? 13052329SN/A Fs1 : Fd1; 13062329SN/A Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 13072329SN/A Fs2 : Fd2; 13082329SN/A }}); 13092329SN/A 0x1: movt_ps({{ 13102329SN/A Fd2 = (getCondCode(FCSR, CC) == 1) ? 13112329SN/A Fs1 : Fd1; 13129440SAndreas.Sandberg@ARM.com Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 13139440SAndreas.Sandberg@ARM.com Fs2 : Fd2; 13142329SN/A }}); 13152329SN/A } 13162329SN/A } 13179440SAndreas.Sandberg@ARM.com 13182329SN/A format Float64Op { 13192329SN/A 0x2: movz_ps({{ 13202329SN/A Fd1 = (getCondCode(FCSR, CC) == 0) ? 13212329SN/A Fs1 : Fd1; 13222329SN/A Fd2 = (getCondCode(FCSR, CC) == 0) ? 13232329SN/A Fs2 : Fd2; 13242329SN/A }}); 13259440SAndreas.Sandberg@ARM.com 0x3: movn_ps({{ 13269440SAndreas.Sandberg@ARM.com Fd1 = (getCondCode(FCSR, CC) == 1) ? 13272329SN/A Fs1 : Fd1; 13282329SN/A Fd2 = (getCondCode(FCSR, CC) == 1) ? 13292329SN/A Fs2 : Fd2; 13302329SN/A }}); 13312329SN/A } 13322329SN/A default: CP1Unimpl::unknown(); 13339944Smatt.horsnell@ARM.com } 13349944Smatt.horsnell@ARM.com 0x3: CP1Unimpl::unknown(); 1335 0x4: decode FUNCTION_LO { 1336 0x0: FloatOp::cvt_s_pu({{ Fd_sf = Fs2_sf; }}); 1337 default: CP1Unimpl::unknown(); 1338 } 1339 1340 0x5: decode FUNCTION_LO { 1341 0x0: FloatOp::cvt_s_pl({{ Fd_sf = Fs1_sf; }}); 1342 format Float64Op { 1343 0x4: pll({{ 1344 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft1_uw; 1345 }}); 1346 0x5: plu({{ 1347 Fd_ud = (uint64_t)Fs1_uw << 32 | Ft2_uw; 1348 }}); 1349 0x6: pul({{ 1350 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft1_uw; 1351 }}); 1352 0x7: puu({{ 1353 Fd_ud = (uint64_t)Fs2_uw << 32 | Ft2_uw; 1354 }}); 1355 } 1356 default: CP1Unimpl::unknown(); 1357 } 1358 1359 0x6: decode FUNCTION_LO { 1360 format FloatPSCompareOp { 1361 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1362 UnorderedFalse); 1363 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1364 UnorderedTrue); 1365 0x2: c_eq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1366 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1367 UnorderedFalse); 1368 0x3: c_ueq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1369 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1370 UnorderedTrue); 1371 0x4: c_olt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1372 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1373 UnorderedFalse); 1374 0x5: c_ult_ps({{ cond1 = (Fs_sf < Ft_sf); }}, 1375 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1376 UnorderedTrue); 1377 0x6: c_ole_ps({{ cond1 = (Fs_sf <= Ft_sf); }}, 1378 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1379 UnorderedFalse); 1380 0x7: c_ule_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1381 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1382 UnorderedTrue); 1383 } 1384 } 1385 1386 0x7: decode FUNCTION_LO { 1387 format FloatPSCompareOp { 1388 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 1389 UnorderedFalse, QnanException); 1390 0x1: c_ngle_ps({{ cond1 = 0; }}, 1391 {{ cond2 = 0; }}, 1392 UnorderedTrue, QnanException); 1393 0x2: c_seq_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1394 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1395 UnorderedFalse, QnanException); 1396 0x3: c_ngl_ps({{ cond1 = (Fs1_sf == Ft1_sf); }}, 1397 {{ cond2 = (Fs2_sf == Ft2_sf); }}, 1398 UnorderedTrue, QnanException); 1399 0x4: c_lt_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1400 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1401 UnorderedFalse, QnanException); 1402 0x5: c_nge_ps({{ cond1 = (Fs1_sf < Ft1_sf); }}, 1403 {{ cond2 = (Fs2_sf < Ft2_sf); }}, 1404 UnorderedTrue, QnanException); 1405 0x6: c_le_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1406 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1407 UnorderedFalse, QnanException); 1408 0x7: c_ngt_ps({{ cond1 = (Fs1_sf <= Ft1_sf); }}, 1409 {{ cond2 = (Fs2_sf <= Ft2_sf); }}, 1410 UnorderedTrue, QnanException); 1411 } 1412 } 1413 } 1414 } 1415 default: CP1Unimpl::unknown(); 1416 } 1417 } 1418 1419 //Table A-19 MIPS32 COP2 Encoding of rs Field 1420 0x2: decode RS_MSB { 1421 format CP2Unimpl { 1422 0x0: decode RS_HI { 1423 0x0: decode RS_LO { 1424 0x0: mfc2(); 1425 0x2: cfc2(); 1426 0x3: mfhc2(); 1427 0x4: mtc2(); 1428 0x6: ctc2(); 1429 0x7: mftc2(); 1430 default: unknown(); 1431 } 1432 1433 0x1: decode ND { 1434 0x0: decode TF { 1435 0x0: bc2f(); 1436 0x1: bc2t(); 1437 default: unknown(); 1438 } 1439 1440 0x1: decode TF { 1441 0x0: bc2fl(); 1442 0x1: bc2tl(); 1443 default: unknown(); 1444 } 1445 default: unknown(); 1446 1447 } 1448 default: unknown(); 1449 } 1450 default: unknown(); 1451 } 1452 } 1453 1454 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1455 //Note: "COP1X instructions are legal only if 64-bit floating point 1456 //operations are enabled." 1457 0x3: decode FUNCTION_HI { 1458 0x0: decode FUNCTION_LO { 1459 format LoadIndexedMemory { 1460 0x0: lwxc1({{ Fd_uw = Mem_uw; }}); 1461 0x1: ldxc1({{ Fd_ud = Mem_ud; }}); 1462 0x5: luxc1({{ Fd_ud = Mem_ud; }}, 1463 {{ EA = (Rs + Rt) & ~7; }}); 1464 } 1465 } 1466 1467 0x1: decode FUNCTION_LO { 1468 format StoreIndexedMemory { 1469 0x0: swxc1({{ Mem_uw = Fs_uw; }}); 1470 0x1: sdxc1({{ Mem_ud = Fs_ud; }}); 1471 0x5: suxc1({{ Mem_ud = Fs_ud; }}, 1472 {{ EA = (Rs + Rt) & ~7; }}); 1473 } 1474 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 1475 } 1476 1477 0x3: decode FUNCTION_LO { 1478 0x6: Float64Op::alnv_ps({{ 1479 if (Rs<2:0> == 0) { 1480 Fd_ud = Fs_ud; 1481 } else if (Rs<2:0> == 4) { 1482 if (GuestByteOrder == BigEndianByteOrder) 1483 Fd_ud = Fs_ud<31:0> << 32 | Ft_ud<63:32>; 1484 else 1485 Fd_ud = Ft_ud<31:0> << 32 | Fs_ud<63:32>; 1486 } else { 1487 Fd_ud = Fd_ud; 1488 } 1489 }}); 1490 } 1491 1492 format FloatAccOp { 1493 0x4: decode FUNCTION_LO { 1494 0x0: madd_s({{ Fd_sf = (Fs_sf * Ft_sf) + Fr_sf; }}); 1495 0x1: madd_d({{ Fd_df = (Fs_df * Ft_df) + Fr_df; }}); 1496 0x6: madd_ps({{ 1497 Fd1_sf = (Fs1_df * Ft1_df) + Fr1_df; 1498 Fd2_sf = (Fs2_df * Ft2_df) + Fr2_df; 1499 }}); 1500 } 1501 1502 0x5: decode FUNCTION_LO { 1503 0x0: msub_s({{ Fd_sf = (Fs_sf * Ft_sf) - Fr_sf; }}); 1504 0x1: msub_d({{ Fd_df = (Fs_df * Ft_df) - Fr_df; }}); 1505 0x6: msub_ps({{ 1506 Fd1_sf = (Fs1_df * Ft1_df) - Fr1_df; 1507 Fd2_sf = (Fs2_df * Ft2_df) - Fr2_df; 1508 }}); 1509 } 1510 1511 0x6: decode FUNCTION_LO { 1512 0x0: nmadd_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) - Fr_sf; }}); 1513 0x1: nmadd_d({{ Fd_df = (-1 * Fs_df * Ft_df) - Fr_df; }}); 1514 0x6: nmadd_ps({{ 1515 Fd1_sf = -((Fs1_df * Ft1_df) + Fr1_df); 1516 Fd2_sf = -((Fs2_df * Ft2_df) + Fr2_df); 1517 }}); 1518 } 1519 1520 0x7: decode FUNCTION_LO { 1521 0x0: nmsub_s({{ Fd_sf = (-1 * Fs_sf * Ft_sf) + Fr_sf; }}); 1522 0x1: nmsub_d({{ Fd_df = (-1 * Fs_df * Ft_df) + Fr_df; }}); 1523 0x6: nmsub_ps({{ 1524 Fd1_sf = -((Fs1_df * Ft1_df) - Fr1_df); 1525 Fd2_sf = -((Fs2_df * Ft2_df) - Fr2_df); 1526 }}); 1527 } 1528 } 1529 } 1530 1531 format Branch { 1532 0x4: beql({{ cond = (Rs_sw == Rt_sw); }}, Likely); 1533 0x5: bnel({{ cond = (Rs_sw != Rt_sw); }}, Likely); 1534 0x6: blezl({{ cond = (Rs_sw <= 0); }}, Likely); 1535 0x7: bgtzl({{ cond = (Rs_sw > 0); }}, Likely); 1536 } 1537 } 1538 1539 0x3: decode OPCODE_LO { 1540 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1541 0x4: decode FUNCTION_HI { 1542 0x0: decode FUNCTION_LO { 1543 0x2: IntOp::mul({{ 1544 int64_t temp1 = Rs_sd * Rt_sd; 1545 Rd_sw = temp1<31:0>; 1546 }}, IntMultOp); 1547 1548 format HiLoRdSelValOp { 1549 0x0: madd({{ 1550 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1551 (Rs_sd * Rt_sd); 1552 }}, IntMultOp); 1553 0x1: maddu({{ 1554 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + 1555 (Rs_ud * Rt_ud); 1556 }}, IntMultOp); 1557 0x4: msub({{ 1558 val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1559 (Rs_sd * Rt_sd); 1560 }}, IntMultOp); 1561 0x5: msubu({{ 1562 val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - 1563 (Rs_ud * Rt_ud); 1564 }}, IntMultOp); 1565 } 1566 } 1567 1568 0x4: decode FUNCTION_LO { 1569 format BasicOp { 1570 0x0: clz({{ 1571 int cnt = 32; 1572 for (int idx = 31; idx >= 0; idx--) { 1573 if (Rs<idx:idx> == 1) { 1574 cnt = 31 - idx; 1575 break; 1576 } 1577 } 1578 Rd_uw = cnt; 1579 }}); 1580 0x1: clo({{ 1581 int cnt = 32; 1582 for (int idx = 31; idx >= 0; idx--) { 1583 if (Rs<idx:idx> == 0) { 1584 cnt = 31 - idx; 1585 break; 1586 } 1587 } 1588 Rd_uw = cnt; 1589 }}); 1590 } 1591 } 1592 1593 0x7: decode FUNCTION_LO { 1594 0x7: FailUnimpl::sdbbp(); 1595 } 1596 } 1597 1598 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 1599 //of the Architecture 1600 0x7: decode FUNCTION_HI { 1601 0x0: decode FUNCTION_LO { 1602 format BasicOp { 1603 0x0: ext({{ Rt_uw = bits(Rs_uw, MSB+LSB, LSB); }}); 1604 0x4: ins({{ 1605 Rt_uw = bits(Rt_uw, 31, MSB+1) << (MSB+1) | 1606 bits(Rs_uw, MSB-LSB, 0) << LSB | 1607 bits(Rt_uw, LSB-1, 0); 1608 }}); 1609 } 1610 } 1611 1612 0x1: decode FUNCTION_LO { 1613 format MT_Control { 1614 0x0: fork({{ 1615 forkThread(xc->tcBase(), fault, RD, Rs, Rt); 1616 }}, UserMode); 1617 0x1: yield({{ 1618 Rd_sw = yieldThread(xc->tcBase(), fault, Rs_sw, 1619 YQMask); 1620 }}, UserMode); 1621 } 1622 1623 //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL) 1624 0x2: decode OP_HI { 1625 0x0: decode OP_LO { 1626 format LoadIndexedMemory { 1627 0x0: lwx({{ Rd_sw = Mem_sw; }}); 1628 0x4: lhx({{ Rd_sw = Mem_sh; }}); 1629 0x6: lbux({{ Rd_uw = Mem_ub; }}); 1630 } 1631 } 1632 } 1633 0x4: DspIntOp::insv({{ 1634 int pos = dspctl<5:0>; 1635 int size = dspctl<12:7> - 1; 1636 Rt_uw = insertBits(Rt_uw, pos+size, 1637 pos, Rs_uw<size:0>); 1638 }}); 1639 } 1640 1641 0x2: decode FUNCTION_LO { 1642 1643 //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field 1644 //(DSP ASE MANUAL) 1645 0x0: decode OP_HI { 1646 0x0: decode OP_LO { 1647 format DspIntOp { 1648 0x0: addu_qb({{ 1649 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1650 NOSATURATE, UNSIGNED, &dspctl); 1651 }}); 1652 0x1: subu_qb({{ 1653 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1654 NOSATURATE, UNSIGNED, &dspctl); 1655 }}); 1656 0x4: addu_s_qb({{ 1657 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1658 SATURATE, UNSIGNED, &dspctl); 1659 }}); 1660 0x5: subu_s_qb({{ 1661 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_QB, 1662 SATURATE, UNSIGNED, &dspctl); 1663 }}); 1664 0x6: muleu_s_ph_qbl({{ 1665 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1666 MODE_L, &dspctl); 1667 }}, IntMultOp); 1668 0x7: muleu_s_ph_qbr({{ 1669 Rd_uw = dspMuleu(Rs_uw, Rt_uw, 1670 MODE_R, &dspctl); 1671 }}, IntMultOp); 1672 } 1673 } 1674 0x1: decode OP_LO { 1675 format DspIntOp { 1676 0x0: addu_ph({{ 1677 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1678 NOSATURATE, UNSIGNED, &dspctl); 1679 }}); 1680 0x1: subu_ph({{ 1681 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1682 NOSATURATE, UNSIGNED, &dspctl); 1683 }}); 1684 0x2: addq_ph({{ 1685 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1686 NOSATURATE, SIGNED, &dspctl); 1687 }}); 1688 0x3: subq_ph({{ 1689 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1690 NOSATURATE, SIGNED, &dspctl); 1691 }}); 1692 0x4: addu_s_ph({{ 1693 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1694 SATURATE, UNSIGNED, &dspctl); 1695 }}); 1696 0x5: subu_s_ph({{ 1697 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1698 SATURATE, UNSIGNED, &dspctl); 1699 }}); 1700 0x6: addq_s_ph({{ 1701 Rd_uw = dspAdd(Rs_uw, Rt_uw, SIMD_FMT_PH, 1702 SATURATE, SIGNED, &dspctl); 1703 }}); 1704 0x7: subq_s_ph({{ 1705 Rd_uw = dspSub(Rs_uw, Rt_uw, SIMD_FMT_PH, 1706 SATURATE, SIGNED, &dspctl); 1707 }}); 1708 } 1709 } 1710 0x2: decode OP_LO { 1711 format DspIntOp { 1712 0x0: addsc({{ 1713 int64_t dresult; 1714 dresult = Rs_ud + Rt_ud; 1715 Rd_sw = dresult<31:0>; 1716 dspctl = insertBits(dspctl, 13, 13, 1717 dresult<32:32>); 1718 }}); 1719 0x1: addwc({{ 1720 int64_t dresult; 1721 dresult = Rs_sd + Rt_sd + dspctl<13:13>; 1722 Rd_sw = dresult<31:0>; 1723 if (dresult<32:32> != dresult<31:31>) 1724 dspctl = insertBits(dspctl, 20, 20, 1); 1725 }}); 1726 0x2: modsub({{ 1727 Rd_sw = (Rs_sw == 0) ? Rt_sw<23:8> : 1728 Rs_sw - Rt_sw<7:0>; 1729 }}); 1730 0x4: raddu_w_qb({{ 1731 Rd_uw = Rs_uw<31:24> + Rs_uw<23:16> + 1732 Rs_uw<15:8> + Rs_uw<7:0>; 1733 }}); 1734 0x6: addq_s_w({{ 1735 Rd_sw = dspAdd(Rs_sw, Rt_sw, SIMD_FMT_W, 1736 SATURATE, SIGNED, &dspctl); 1737 }}); 1738 0x7: subq_s_w({{ 1739 Rd_sw = dspSub(Rs_sw, Rt_sw, SIMD_FMT_W, 1740 SATURATE, SIGNED, &dspctl); 1741 }}); 1742 } 1743 } 1744 0x3: decode OP_LO { 1745 format DspIntOp { 1746 0x4: muleq_s_w_phl({{ 1747 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1748 MODE_L, &dspctl); 1749 }}, IntMultOp); 1750 0x5: muleq_s_w_phr({{ 1751 Rd_sw = dspMuleq(Rs_sw, Rt_sw, 1752 MODE_R, &dspctl); 1753 }}, IntMultOp); 1754 0x6: mulq_s_ph({{ 1755 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1756 SATURATE, NOROUND, &dspctl); 1757 }}, IntMultOp); 1758 0x7: mulq_rs_ph({{ 1759 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_PH, 1760 SATURATE, ROUND, &dspctl); 1761 }}, IntMultOp); 1762 } 1763 } 1764 } 1765 1766 //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field 1767 //(DSP ASE MANUAL) 1768 0x1: decode OP_HI { 1769 0x0: decode OP_LO { 1770 format DspIntOp { 1771 0x0: cmpu_eq_qb({{ 1772 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1773 UNSIGNED, CMP_EQ, &dspctl); 1774 }}); 1775 0x1: cmpu_lt_qb({{ 1776 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1777 UNSIGNED, CMP_LT, &dspctl); 1778 }}); 1779 0x2: cmpu_le_qb({{ 1780 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_QB, 1781 UNSIGNED, CMP_LE, &dspctl); 1782 }}); 1783 0x3: pick_qb({{ 1784 Rd_uw = dspPick(Rs_uw, Rt_uw, 1785 SIMD_FMT_QB, &dspctl); 1786 }}); 1787 0x4: cmpgu_eq_qb({{ 1788 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1789 UNSIGNED, CMP_EQ ); 1790 }}); 1791 0x5: cmpgu_lt_qb({{ 1792 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1793 UNSIGNED, CMP_LT); 1794 }}); 1795 0x6: cmpgu_le_qb({{ 1796 Rd_uw = dspCmpg(Rs_uw, Rt_uw, SIMD_FMT_QB, 1797 UNSIGNED, CMP_LE); 1798 }}); 1799 } 1800 } 1801 0x1: decode OP_LO { 1802 format DspIntOp { 1803 0x0: cmp_eq_ph({{ 1804 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1805 SIGNED, CMP_EQ, &dspctl); 1806 }}); 1807 0x1: cmp_lt_ph({{ 1808 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1809 SIGNED, CMP_LT, &dspctl); 1810 }}); 1811 0x2: cmp_le_ph({{ 1812 dspCmp(Rs_uw, Rt_uw, SIMD_FMT_PH, 1813 SIGNED, CMP_LE, &dspctl); 1814 }}); 1815 0x3: pick_ph({{ 1816 Rd_uw = dspPick(Rs_uw, Rt_uw, 1817 SIMD_FMT_PH, &dspctl); 1818 }}); 1819 0x4: precrq_qb_ph({{ 1820 Rd_uw = Rs_uw<31:24> << 24 | 1821 Rs_uw<15:8> << 16 | 1822 Rt_uw<31:24> << 8 | 1823 Rt_uw<15:8>; 1824 }}); 1825 0x5: precr_qb_ph({{ 1826 Rd_uw = Rs_uw<23:16> << 24 | 1827 Rs_uw<7:0> << 16 | 1828 Rt_uw<23:16> << 8 | 1829 Rt_uw<7:0>; 1830 }}); 1831 0x6: packrl_ph({{ 1832 Rd_uw = dspPack(Rs_uw, Rt_uw, SIMD_FMT_PH); 1833 }}); 1834 0x7: precrqu_s_qb_ph({{ 1835 Rd_uw = dspPrecrqu(Rs_uw, Rt_uw, &dspctl); 1836 }}); 1837 } 1838 } 1839 0x2: decode OP_LO { 1840 format DspIntOp { 1841 0x4: precrq_ph_w({{ 1842 Rd_uw = Rs_uw<31:16> << 16 | Rt_uw<31:16>; 1843 }}); 1844 0x5: precrq_rs_ph_w({{ 1845 Rd_uw = dspPrecrq(Rs_uw, Rt_uw, 1846 SIMD_FMT_W, &dspctl); 1847 }}); 1848 } 1849 } 1850 0x3: decode OP_LO { 1851 format DspIntOp { 1852 0x0: cmpgdu_eq_qb({{ 1853 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1854 UNSIGNED, CMP_EQ, &dspctl); 1855 }}); 1856 0x1: cmpgdu_lt_qb({{ 1857 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1858 UNSIGNED, CMP_LT, &dspctl); 1859 }}); 1860 0x2: cmpgdu_le_qb({{ 1861 Rd_uw = dspCmpgd(Rs_uw, Rt_uw, SIMD_FMT_QB, 1862 UNSIGNED, CMP_LE, &dspctl); 1863 }}); 1864 0x6: precr_sra_ph_w({{ 1865 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1866 SIMD_FMT_W, NOROUND); 1867 }}); 1868 0x7: precr_sra_r_ph_w({{ 1869 Rt_uw = dspPrecrSra(Rt_uw, Rs_uw, RD, 1870 SIMD_FMT_W, ROUND); 1871 }}); 1872 } 1873 } 1874 } 1875 1876 //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field 1877 //(DSP ASE MANUAL) 1878 0x2: decode OP_HI { 1879 0x0: decode OP_LO { 1880 format DspIntOp { 1881 0x1: absq_s_qb({{ 1882 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_QB, &dspctl); 1883 }}); 1884 0x2: repl_qb({{ 1885 Rd_uw = RS_RT<7:0> << 24 | 1886 RS_RT<7:0> << 16 | 1887 RS_RT<7:0> << 8 | 1888 RS_RT<7:0>; 1889 }}); 1890 0x3: replv_qb({{ 1891 Rd_sw = Rt_uw<7:0> << 24 | 1892 Rt_uw<7:0> << 16 | 1893 Rt_uw<7:0> << 8 | 1894 Rt_uw<7:0>; 1895 }}); 1896 0x4: precequ_ph_qbl({{ 1897 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1898 SIMD_FMT_PH, SIGNED, MODE_L); 1899 }}); 1900 0x5: precequ_ph_qbr({{ 1901 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1902 SIMD_FMT_PH, SIGNED, MODE_R); 1903 }}); 1904 0x6: precequ_ph_qbla({{ 1905 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1906 SIMD_FMT_PH, SIGNED, MODE_LA); 1907 }}); 1908 0x7: precequ_ph_qbra({{ 1909 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, UNSIGNED, 1910 SIMD_FMT_PH, SIGNED, MODE_RA); 1911 }}); 1912 } 1913 } 1914 0x1: decode OP_LO { 1915 format DspIntOp { 1916 0x1: absq_s_ph({{ 1917 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_PH, &dspctl); 1918 }}); 1919 0x2: repl_ph({{ 1920 Rd_uw = (sext<10>(RS_RT))<15:0> << 16 | 1921 (sext<10>(RS_RT))<15:0>; 1922 }}); 1923 0x3: replv_ph({{ 1924 Rd_uw = Rt_uw<15:0> << 16 | 1925 Rt_uw<15:0>; 1926 }}); 1927 0x4: preceq_w_phl({{ 1928 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1929 SIMD_FMT_W, SIGNED, MODE_L); 1930 }}); 1931 0x5: preceq_w_phr({{ 1932 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_PH, SIGNED, 1933 SIMD_FMT_W, SIGNED, MODE_R); 1934 }}); 1935 } 1936 } 1937 0x2: decode OP_LO { 1938 format DspIntOp { 1939 0x1: absq_s_w({{ 1940 Rd_sw = dspAbs(Rt_sw, SIMD_FMT_W, &dspctl); 1941 }}); 1942 } 1943 } 1944 0x3: decode OP_LO { 1945 0x3: IntOp::bitrev({{ 1946 Rd_uw = bitrev( Rt_uw<15:0> ); 1947 }}); 1948 format DspIntOp { 1949 0x4: preceu_ph_qbl({{ 1950 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1951 UNSIGNED, SIMD_FMT_PH, 1952 UNSIGNED, MODE_L); 1953 }}); 1954 0x5: preceu_ph_qbr({{ 1955 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1956 UNSIGNED, SIMD_FMT_PH, 1957 UNSIGNED, MODE_R ); 1958 }}); 1959 0x6: preceu_ph_qbla({{ 1960 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1961 UNSIGNED, SIMD_FMT_PH, 1962 UNSIGNED, MODE_LA ); 1963 }}); 1964 0x7: preceu_ph_qbra({{ 1965 Rd_uw = dspPrece(Rt_uw, SIMD_FMT_QB, 1966 UNSIGNED, SIMD_FMT_PH, 1967 UNSIGNED, MODE_RA); 1968 }}); 1969 } 1970 } 1971 } 1972 1973 //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field 1974 //(DSP ASE MANUAL) 1975 0x3: decode OP_HI { 1976 0x0: decode OP_LO { 1977 format DspIntOp { 1978 0x0: shll_qb({{ 1979 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_QB, 1980 NOSATURATE, UNSIGNED, &dspctl); 1981 }}); 1982 0x1: shrl_qb({{ 1983 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_QB, 1984 UNSIGNED); 1985 }}); 1986 0x2: shllv_qb({{ 1987 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_QB, 1988 NOSATURATE, UNSIGNED, &dspctl); 1989 }}); 1990 0x3: shrlv_qb({{ 1991 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_QB, 1992 UNSIGNED); 1993 }}); 1994 0x4: shra_qb({{ 1995 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 1996 NOROUND, SIGNED, &dspctl); 1997 }}); 1998 0x5: shra_r_qb({{ 1999 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_QB, 2000 ROUND, SIGNED, &dspctl); 2001 }}); 2002 0x6: shrav_qb({{ 2003 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2004 NOROUND, SIGNED, &dspctl); 2005 }}); 2006 0x7: shrav_r_qb({{ 2007 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_QB, 2008 ROUND, SIGNED, &dspctl); 2009 }}); 2010 } 2011 } 2012 0x1: decode OP_LO { 2013 format DspIntOp { 2014 0x0: shll_ph({{ 2015 Rd_uw = dspShll(Rt_uw, RS, SIMD_FMT_PH, 2016 NOSATURATE, SIGNED, &dspctl); 2017 }}); 2018 0x1: shra_ph({{ 2019 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2020 NOROUND, SIGNED, &dspctl); 2021 }}); 2022 0x2: shllv_ph({{ 2023 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2024 NOSATURATE, SIGNED, &dspctl); 2025 }}); 2026 0x3: shrav_ph({{ 2027 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2028 NOROUND, SIGNED, &dspctl); 2029 }}); 2030 0x4: shll_s_ph({{ 2031 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_PH, 2032 SATURATE, SIGNED, &dspctl); 2033 }}); 2034 0x5: shra_r_ph({{ 2035 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_PH, 2036 ROUND, SIGNED, &dspctl); 2037 }}); 2038 0x6: shllv_s_ph({{ 2039 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_PH, 2040 SATURATE, SIGNED, &dspctl); 2041 }}); 2042 0x7: shrav_r_ph({{ 2043 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_PH, 2044 ROUND, SIGNED, &dspctl); 2045 }}); 2046 } 2047 } 2048 0x2: decode OP_LO { 2049 format DspIntOp { 2050 0x4: shll_s_w({{ 2051 Rd_sw = dspShll(Rt_sw, RS, SIMD_FMT_W, 2052 SATURATE, SIGNED, &dspctl); 2053 }}); 2054 0x5: shra_r_w({{ 2055 Rd_sw = dspShra(Rt_sw, RS, SIMD_FMT_W, 2056 ROUND, SIGNED, &dspctl); 2057 }}); 2058 0x6: shllv_s_w({{ 2059 Rd_sw = dspShll(Rt_sw, Rs_sw, SIMD_FMT_W, 2060 SATURATE, SIGNED, &dspctl); 2061 }}); 2062 0x7: shrav_r_w({{ 2063 Rd_sw = dspShra(Rt_sw, Rs_sw, SIMD_FMT_W, 2064 ROUND, SIGNED, &dspctl); 2065 }}); 2066 } 2067 } 2068 0x3: decode OP_LO { 2069 format DspIntOp { 2070 0x1: shrl_ph({{ 2071 Rd_sw = dspShrl(Rt_sw, RS, SIMD_FMT_PH, 2072 UNSIGNED); 2073 }}); 2074 0x3: shrlv_ph({{ 2075 Rd_sw = dspShrl(Rt_sw, Rs_sw, SIMD_FMT_PH, 2076 UNSIGNED); 2077 }}); 2078 } 2079 } 2080 } 2081 } 2082 2083 0x3: decode FUNCTION_LO { 2084 2085 //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field 2086 //(DSP ASE Rev2 Manual) 2087 0x0: decode OP_HI { 2088 0x0: decode OP_LO { 2089 format DspIntOp { 2090 0x0: adduh_qb({{ 2091 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2092 NOROUND, UNSIGNED); 2093 }}); 2094 0x1: subuh_qb({{ 2095 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2096 NOROUND, UNSIGNED); 2097 }}); 2098 0x2: adduh_r_qb({{ 2099 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2100 ROUND, UNSIGNED); 2101 }}); 2102 0x3: subuh_r_qb({{ 2103 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_QB, 2104 ROUND, UNSIGNED); 2105 }}); 2106 } 2107 } 2108 0x1: decode OP_LO { 2109 format DspIntOp { 2110 0x0: addqh_ph({{ 2111 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2112 NOROUND, SIGNED); 2113 }}); 2114 0x1: subqh_ph({{ 2115 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2116 NOROUND, SIGNED); 2117 }}); 2118 0x2: addqh_r_ph({{ 2119 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2120 ROUND, SIGNED); 2121 }}); 2122 0x3: subqh_r_ph({{ 2123 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_PH, 2124 ROUND, SIGNED); 2125 }}); 2126 0x4: mul_ph({{ 2127 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2128 NOSATURATE, &dspctl); 2129 }}, IntMultOp); 2130 0x6: mul_s_ph({{ 2131 Rd_sw = dspMul(Rs_sw, Rt_sw, SIMD_FMT_PH, 2132 SATURATE, &dspctl); 2133 }}, IntMultOp); 2134 } 2135 } 2136 0x2: decode OP_LO { 2137 format DspIntOp { 2138 0x0: addqh_w({{ 2139 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2140 NOROUND, SIGNED); 2141 }}); 2142 0x1: subqh_w({{ 2143 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2144 NOROUND, SIGNED); 2145 }}); 2146 0x2: addqh_r_w({{ 2147 Rd_uw = dspAddh(Rs_sw, Rt_sw, SIMD_FMT_W, 2148 ROUND, SIGNED); 2149 }}); 2150 0x3: subqh_r_w({{ 2151 Rd_uw = dspSubh(Rs_sw, Rt_sw, SIMD_FMT_W, 2152 ROUND, SIGNED); 2153 }}); 2154 0x6: mulq_s_w({{ 2155 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2156 SATURATE, NOROUND, &dspctl); 2157 }}, IntMultOp); 2158 0x7: mulq_rs_w({{ 2159 Rd_sw = dspMulq(Rs_sw, Rt_sw, SIMD_FMT_W, 2160 SATURATE, ROUND, &dspctl); 2161 }}, IntMultOp); 2162 } 2163 } 2164 } 2165 } 2166 2167 //Table A-10 MIPS32 BSHFL Encoding of sa Field 2168 0x4: decode SA { 2169 format BasicOp { 2170 0x02: wsbh({{ 2171 Rd_uw = Rt_uw<23:16> << 24 | 2172 Rt_uw<31:24> << 16 | 2173 Rt_uw<7:0> << 8 | 2174 Rt_uw<15:8>; 2175 }}); 2176 0x10: seb({{ Rd_sw = Rt_sb; }}); 2177 0x18: seh({{ Rd_sw = Rt_sh; }}); 2178 } 2179 } 2180 2181 0x6: decode FUNCTION_LO { 2182 2183 //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field 2184 //(DSP ASE MANUAL) 2185 0x0: decode OP_HI { 2186 0x0: decode OP_LO { 2187 format DspHiLoOp { 2188 0x0: dpa_w_ph({{ 2189 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2190 SIMD_FMT_PH, SIGNED, MODE_L); 2191 }}, IntMultOp); 2192 0x1: dps_w_ph({{ 2193 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2194 SIMD_FMT_PH, SIGNED, MODE_L); 2195 }}, IntMultOp); 2196 0x2: mulsa_w_ph({{ 2197 dspac = dspMulsa(dspac, Rs_sw, Rt_sw, 2198 ACDST, SIMD_FMT_PH ); 2199 }}, IntMultOp); 2200 0x3: dpau_h_qbl({{ 2201 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2202 SIMD_FMT_QB, UNSIGNED, MODE_L); 2203 }}, IntMultOp); 2204 0x4: dpaq_s_w_ph({{ 2205 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2206 ACDST, SIMD_FMT_PH, 2207 SIMD_FMT_W, NOSATURATE, 2208 MODE_L, &dspctl); 2209 }}, IntMultOp); 2210 0x5: dpsq_s_w_ph({{ 2211 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2212 ACDST, SIMD_FMT_PH, 2213 SIMD_FMT_W, NOSATURATE, 2214 MODE_L, &dspctl); 2215 }}, IntMultOp); 2216 0x6: mulsaq_s_w_ph({{ 2217 dspac = dspMulsaq(dspac, Rs_sw, Rt_sw, 2218 ACDST, SIMD_FMT_PH, 2219 &dspctl); 2220 }}, IntMultOp); 2221 0x7: dpau_h_qbr({{ 2222 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2223 SIMD_FMT_QB, UNSIGNED, MODE_R); 2224 }}, IntMultOp); 2225 } 2226 } 2227 0x1: decode OP_LO { 2228 format DspHiLoOp { 2229 0x0: dpax_w_ph({{ 2230 dspac = dspDpa(dspac, Rs_sw, Rt_sw, ACDST, 2231 SIMD_FMT_PH, SIGNED, MODE_X); 2232 }}, IntMultOp); 2233 0x1: dpsx_w_ph({{ 2234 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2235 SIMD_FMT_PH, SIGNED, MODE_X); 2236 }}, IntMultOp); 2237 0x3: dpsu_h_qbl({{ 2238 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2239 SIMD_FMT_QB, UNSIGNED, MODE_L); 2240 }}, IntMultOp); 2241 0x4: dpaq_sa_l_w({{ 2242 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2243 ACDST, SIMD_FMT_W, 2244 SIMD_FMT_L, SATURATE, 2245 MODE_L, &dspctl); 2246 }}, IntMultOp); 2247 0x5: dpsq_sa_l_w({{ 2248 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2249 ACDST, SIMD_FMT_W, 2250 SIMD_FMT_L, SATURATE, 2251 MODE_L, &dspctl); 2252 }}, IntMultOp); 2253 0x7: dpsu_h_qbr({{ 2254 dspac = dspDps(dspac, Rs_sw, Rt_sw, ACDST, 2255 SIMD_FMT_QB, UNSIGNED, MODE_R); 2256 }}, IntMultOp); 2257 } 2258 } 2259 0x2: decode OP_LO { 2260 format DspHiLoOp { 2261 0x0: maq_sa_w_phl({{ 2262 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2263 ACDST, SIMD_FMT_PH, 2264 MODE_L, SATURATE, &dspctl); 2265 }}, IntMultOp); 2266 0x2: maq_sa_w_phr({{ 2267 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2268 ACDST, SIMD_FMT_PH, 2269 MODE_R, SATURATE, &dspctl); 2270 }}, IntMultOp); 2271 0x4: maq_s_w_phl({{ 2272 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2273 ACDST, SIMD_FMT_PH, 2274 MODE_L, NOSATURATE, &dspctl); 2275 }}, IntMultOp); 2276 0x6: maq_s_w_phr({{ 2277 dspac = dspMaq(dspac, Rs_uw, Rt_uw, 2278 ACDST, SIMD_FMT_PH, 2279 MODE_R, NOSATURATE, &dspctl); 2280 }}, IntMultOp); 2281 } 2282 } 2283 0x3: decode OP_LO { 2284 format DspHiLoOp { 2285 0x0: dpaqx_s_w_ph({{ 2286 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2287 ACDST, SIMD_FMT_PH, 2288 SIMD_FMT_W, NOSATURATE, 2289 MODE_X, &dspctl); 2290 }}, IntMultOp); 2291 0x1: dpsqx_s_w_ph({{ 2292 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2293 ACDST, SIMD_FMT_PH, 2294 SIMD_FMT_W, NOSATURATE, 2295 MODE_X, &dspctl); 2296 }}, IntMultOp); 2297 0x2: dpaqx_sa_w_ph({{ 2298 dspac = dspDpaq(dspac, Rs_sw, Rt_sw, 2299 ACDST, SIMD_FMT_PH, 2300 SIMD_FMT_W, SATURATE, 2301 MODE_X, &dspctl); 2302 }}, IntMultOp); 2303 0x3: dpsqx_sa_w_ph({{ 2304 dspac = dspDpsq(dspac, Rs_sw, Rt_sw, 2305 ACDST, SIMD_FMT_PH, 2306 SIMD_FMT_W, SATURATE, 2307 MODE_X, &dspctl); 2308 }}, IntMultOp); 2309 } 2310 } 2311 } 2312 2313 //Table 3.3 MIPS32 APPEND Encoding of the op Field 2314 0x1: decode OP_HI { 2315 0x0: decode OP_LO { 2316 format IntOp { 2317 0x0: append({{ 2318 Rt_uw = (Rt_uw << RD) | bits(Rs_uw, RD - 1, 0); 2319 }}); 2320 0x1: prepend({{ 2321 Rt_uw = (Rt_uw >> RD) | 2322 (bits(Rs_uw, RD - 1, 0) << (32 - RD)); 2323 }}); 2324 } 2325 } 2326 0x2: decode OP_LO { 2327 format IntOp { 2328 0x0: balign({{ 2329 Rt_uw = (Rt_uw << (8 * BP)) | 2330 (Rs_uw >> (8 * (4 - BP))); 2331 }}); 2332 } 2333 } 2334 } 2335 2336 } 2337 0x7: decode FUNCTION_LO { 2338 2339 //Table 5-11 MIPS32 EXTR.W Encoding of the op Field 2340 //(DSP ASE MANUAL) 2341 0x0: decode OP_HI { 2342 0x0: decode OP_LO { 2343 format DspHiLoOp { 2344 0x0: extr_w({{ 2345 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2346 NOROUND, NOSATURATE, &dspctl); 2347 }}); 2348 0x1: extrv_w({{ 2349 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2350 NOROUND, NOSATURATE, &dspctl); 2351 }}); 2352 0x2: extp({{ 2353 Rt_uw = dspExtp(dspac, RS, &dspctl); 2354 }}); 2355 0x3: extpv({{ 2356 Rt_uw = dspExtp(dspac, Rs_uw, &dspctl); 2357 }}); 2358 0x4: extr_r_w({{ 2359 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2360 ROUND, NOSATURATE, &dspctl); 2361 }}); 2362 0x5: extrv_r_w({{ 2363 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2364 ROUND, NOSATURATE, &dspctl); 2365 }}); 2366 0x6: extr_rs_w({{ 2367 Rt_uw = dspExtr(dspac, SIMD_FMT_W, RS, 2368 ROUND, SATURATE, &dspctl); 2369 }}); 2370 0x7: extrv_rs_w({{ 2371 Rt_uw = dspExtr(dspac, SIMD_FMT_W, Rs_uw, 2372 ROUND, SATURATE, &dspctl); 2373 }}); 2374 } 2375 } 2376 0x1: decode OP_LO { 2377 format DspHiLoOp { 2378 0x2: extpdp({{ 2379 Rt_uw = dspExtpd(dspac, RS, &dspctl); 2380 }}); 2381 0x3: extpdpv({{ 2382 Rt_uw = dspExtpd(dspac, Rs_uw, &dspctl); 2383 }}); 2384 0x6: extr_s_h({{ 2385 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, RS, 2386 NOROUND, SATURATE, &dspctl); 2387 }}); 2388 0x7: extrv_s_h({{ 2389 Rt_uw = dspExtr(dspac, SIMD_FMT_PH, Rs_uw, 2390 NOROUND, SATURATE, &dspctl); 2391 }}); 2392 } 2393 } 2394 0x2: decode OP_LO { 2395 format DspIntOp { 2396 0x2: rddsp({{ 2397 Rd_uw = readDSPControl(&dspctl, RDDSPMASK); 2398 }}); 2399 0x3: wrdsp({{ 2400 writeDSPControl(&dspctl, Rs_uw, WRDSPMASK); 2401 }}); 2402 } 2403 } 2404 0x3: decode OP_LO { 2405 format DspHiLoOp { 2406 0x2: shilo({{ 2407 if (sext<6>(HILOSA) < 0) { 2408 dspac = (uint64_t)dspac << 2409 -sext<6>(HILOSA); 2410 } else { 2411 dspac = (uint64_t)dspac >> 2412 sext<6>(HILOSA); 2413 } 2414 }}); 2415 0x3: shilov({{ 2416 if (sext<6>(Rs_sw<5:0>) < 0) { 2417 dspac = (uint64_t)dspac << 2418 -sext<6>(Rs_sw<5:0>); 2419 } else { 2420 dspac = (uint64_t)dspac >> 2421 sext<6>(Rs_sw<5:0>); 2422 } 2423 }}); 2424 0x7: mthlip({{ 2425 dspac = dspac << 32; 2426 dspac |= Rs_uw; 2427 dspctl = insertBits(dspctl, 5, 0, 2428 dspctl<5:0> + 32); 2429 }}); 2430 } 2431 } 2432 } 2433 0x3: decode OP default FailUnimpl::rdhwr() { 2434 0x0: decode FULL_SYSTEM { 2435 0: decode RD { 2436 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 2437 } 2438 } 2439 } 2440 } 2441 } 2442 } 2443 2444 0x4: decode OPCODE_LO { 2445 format LoadMemory { 2446 0x0: lb({{ Rt_sw = Mem_sb; }}); 2447 0x1: lh({{ Rt_sw = Mem_sh; }}); 2448 0x3: lw({{ Rt_sw = Mem_sw; }}); 2449 0x4: lbu({{ Rt_uw = Mem_ub;}}); 2450 0x5: lhu({{ Rt_uw = Mem_uh; }}); 2451 } 2452 2453 format LoadUnalignedMemory { 2454 0x2: lwl({{ 2455 uint32_t mem_shift = 24 - (8 * byte_offset); 2456 Rt_uw = mem_word << mem_shift | (Rt_uw & mask(mem_shift)); 2457 }}); 2458 0x6: lwr({{ 2459 uint32_t mem_shift = 8 * byte_offset; 2460 Rt_uw = (Rt_uw & (mask(mem_shift) << (32 - mem_shift))) | 2461 (mem_word >> mem_shift); 2462 }}); 2463 } 2464 } 2465 2466 0x5: decode OPCODE_LO { 2467 format StoreMemory { 2468 0x0: sb({{ Mem_ub = Rt<7:0>; }}); 2469 0x1: sh({{ Mem_uh = Rt<15:0>; }}); 2470 0x3: sw({{ Mem_uw = Rt<31:0>; }}); 2471 } 2472 2473 format StoreUnalignedMemory { 2474 0x2: swl({{ 2475 uint32_t reg_shift = 24 - (8 * byte_offset); 2476 uint32_t mem_shift = 32 - reg_shift; 2477 mem_word = (mem_word & (mask(reg_shift) << mem_shift)) | 2478 (Rt_uw >> reg_shift); 2479 }}); 2480 0x6: swr({{ 2481 uint32_t reg_shift = 8 * byte_offset; 2482 mem_word = Rt_uw << reg_shift | 2483 (mem_word & (mask(reg_shift))); 2484 }}); 2485 } 2486 format CP0Control { 2487 0x7: cache({{ 2488 //Addr CacheEA = Rs_uw + OFFSET; 2489 //fault = xc->CacheOp((uint8_t)CACHE_OP,(Addr) CacheEA); 2490 }}); 2491 } 2492 } 2493 2494 0x6: decode OPCODE_LO { 2495 format LoadMemory { 2496 0x0: ll({{ Rt_uw = Mem_uw; }}, mem_flags=LLSC); 2497 0x1: lwc1({{ Ft_uw = Mem_uw; }}); 2498 0x5: ldc1({{ Ft_ud = Mem_ud; }}); 2499 } 2500 0x2: CP2Unimpl::lwc2(); 2501 0x6: CP2Unimpl::ldc2(); 2502 0x3: Prefetch::pref(); 2503 } 2504 2505 2506 0x7: decode OPCODE_LO { 2507 0x0: StoreCond::sc({{ Mem_uw = Rt_uw; }}, 2508 {{ uint64_t tmp = write_result; 2509 Rt_uw = (tmp == 0 || tmp == 1) ? tmp : Rt_uw; 2510 }}, mem_flags=LLSC, 2511 inst_flags = IsStoreConditional); 2512 format StoreMemory { 2513 0x1: swc1({{ Mem_uw = Ft_uw; }}); 2514 0x5: sdc1({{ Mem_ud = Ft_ud; }}); 2515 } 2516 0x2: CP2Unimpl::swc2(); 2517 0x6: CP2Unimpl::sdc2(); 2518 } 2519} 2520 2521 2522