decoder.isa revision 4828:768d4cf6b0dc 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2006 The Regents of The University of Michigan
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28//
29// Authors: Korey Sewell
30//          Brett Miller
31
32////////////////////////////////////////////////////////////////////
33//
34// The actual MIPS32 ISA decoder
35// -----------------------------
36// The following instructions are specified in the MIPS32 ISA
37// Specification. Decoding closely follows the style specified
38// in the MIPS32 ISA specification document starting with Table
39// A-2 (document available @ http://www.mips.com)
40//
41decode OPCODE_HI default Unknown::unknown() {
42    //Table A-2
43    0x0: decode OPCODE_LO {
44        0x0: decode FUNCTION_HI {
45            0x0: decode FUNCTION_LO {
46                0x1: decode MOVCI {
47                    format BasicOp {
48                        0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }});
49                        1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }});
50                    }
51                }
52
53                format BasicOp {
54                    //Table A-3 Note: "Specific encodings of the rd, rs, and
55                    //rt fields are used to distinguish SLL, SSNOP, and EHB
56                    //functions
57                    0x0: decode RS  {
58                        0x0: decode RT_RD {
59                            0x0: decode SA default Nop::nop() {
60                                0x1: WarnUnimpl::ssnop();
61                                0x3: WarnUnimpl::ehb();
62                            }
63                            default: sll({{ Rd = Rt.uw << SA; }});
64                        }
65                    }
66
67                    0x2: decode RS_SRL {
68                        0x0:decode SRL {
69                            0: srl({{ Rd = Rt.uw >> SA; }});
70
71                            //Hardcoded assuming 32-bit ISA, probably need parameter here
72                            1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}});
73                        }
74                    }
75
76                    0x3: decode RS {
77                        0x0: sra({{
78                            uint32_t temp = Rt >> SA;
79                            if ( (Rt & 0x80000000) > 0 ) {
80                                uint32_t mask = 0x80000000;
81                                for(int i=0; i < SA; i++) {
82                                    temp |= mask;
83                                    mask = mask >> 1;
84                                }
85                            }
86                            Rd = temp;
87                        }});
88                    }
89
90                    0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }});
91
92                    0x6: decode SRLV {
93                        0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }});
94
95                        //Hardcoded assuming 32-bit ISA, probably need parameter here
96                        1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}});
97                    }
98
99                    0x7: srav({{
100                        int shift_amt = Rs<4:0>;
101
102                        uint32_t temp = Rt >> shift_amt;
103
104                        if ( (Rt & 0x80000000) > 0 ) {
105                                uint32_t mask = 0x80000000;
106                                for(int i=0; i < shift_amt; i++) {
107                                    temp |= mask;
108                                    mask = mask >> 1;
109                                }
110                            }
111
112                        Rd = temp;
113                    }});
114                }
115            }
116
117            0x1: decode FUNCTION_LO {
118                //Table A-3 Note: "Specific encodings of the hint field are
119                //used to distinguish JR from JR.HB and JALR from JALR.HB"
120                format Jump {
121                    0x0: decode HINT {
122                        0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards);
123                        default: jr({{ NNPC = Rs & ~1; }}, IsReturn);
124                    }
125
126                    0x1: decode HINT {
127                        0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall
128                                     , ClearHazards);
129                        default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall);
130                    }
131                }
132
133                format BasicOp {
134                    0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
135                    0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
136                    0x4: syscall({{ xc->syscall(R2); }},
137                                 IsSerializeAfter, IsNonSpeculative,
138                                 IsSyscall);
139                    0x7: sync({{ ; }}, IsMemBarrier);
140                }
141
142                format FailUnimpl {
143                    0x5: break();
144                }
145            }
146
147            0x2: decode FUNCTION_LO {
148                0x0: HiLoRsSelOp::mfhi({{ Rd = HI_RS_SEL; }});
149                0x1: HiLoRdSelOp::mthi({{ HI_RD_SEL = Rs; }});
150                0x2: HiLoRsSelOp::mflo({{ Rd = LO_RS_SEL; }});
151                0x3: HiLoRdSelOp::mtlo({{ LO_RD_SEL = Rs; }});
152            }
153
154            0x3: decode FUNCTION_LO {
155                format HiLoRdSelValOp {
156                    0x0: mult({{ val = Rs.sd * Rt.sd; }});
157                    0x1: multu({{ val = Rs.ud * Rt.ud; }});
158                }
159
160                format HiLoOp {
161                    0x2: div({{ if (Rt.sd != 0) {
162                        HI0 = Rs.sd % Rt.sd;
163                        LO0 = Rs.sd / Rt.sd;
164                    }
165                    }});
166                    0x3: divu({{ if (Rt.ud != 0) {
167                        HI0 = Rs.ud % Rt.ud;
168                        LO0 = Rs.ud / Rt.ud;
169                    }
170                    }});
171                }
172            }
173
174            0x4: decode HINT {
175                0x0: decode FUNCTION_LO {
176                    format IntOp {
177                        0x0: add({{  Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}});
178                        0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}});
179                        0x2: sub({{ Rd.sw = Rs.sw - Rt.sw;  /*Trap on Overflow*/}});
180                        0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}});
181                        0x4: and({{ Rd = Rs & Rt;}});
182                        0x5: or({{ Rd = Rs | Rt;}});
183                        0x6: xor({{ Rd = Rs ^ Rt;}});
184                        0x7: nor({{ Rd = ~(Rs | Rt);}});
185                    }
186                }
187            }
188
189            0x5: decode HINT {
190                0x0: decode FUNCTION_LO {
191                    format IntOp{
192                        0x2: slt({{  Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}});
193                        0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}});
194                    }
195                }
196            }
197
198            0x6: decode FUNCTION_LO {
199                format Trap {
200                    0x0: tge({{  cond = (Rs.sw >= Rt.sw); }});
201                    0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }});
202                    0x2: tlt({{ cond = (Rs.sw < Rt.sw); }});
203                    0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }});
204                    0x4: teq({{ cond = (Rs.sw == Rt.sw); }});
205                    0x6: tne({{ cond = (Rs.sw != Rt.sw); }});
206                }
207            }
208        }
209
210        0x1: decode REGIMM_HI {
211            0x0: decode REGIMM_LO {
212                format Branch {
213                    0x0: bltz({{ cond = (Rs.sw < 0); }});
214                    0x1: bgez({{ cond = (Rs.sw >= 0); }});
215                    0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely);
216                    0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely);
217                }
218            }
219
220            0x1: decode REGIMM_LO {
221                format Trap {
222                    0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }});
223                    0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }});
224                    0x2: tlti( {{ cond = (Rs.sw < INTIMM); }});
225                    0x3: tltiu({{ cond = (Rs.uw < INTIMM); }});
226                    0x4: teqi( {{ cond = (Rs.sw == INTIMM);}});
227                    0x6: tnei( {{ cond = (Rs.sw != INTIMM);}});
228                }
229            }
230
231            0x2: decode REGIMM_LO {
232                format Branch {
233                    0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link);
234                    0x1: decode RS {
235                        0x0: bal ({{ cond = 1; }}, IsCall, Link);
236                        default: bgezal({{ cond = (Rs.sw >= 0); }}, Link);
237                    }
238                    0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely);
239                    0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely);
240                }
241            }
242
243            0x3: decode REGIMM_LO {
244                // from Table 5-4 MIPS32 REGIMM Encoding of rt Field (DSP ASE MANUAL)
245                0x4: DspBranch::bposge32({{ cond = (dspctl<5:0> >= 32); }});
246                format WarnUnimpl {
247                    0x7: synci();
248                }
249            }
250        }
251
252        format Jump {
253            0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}});
254            0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall,
255                     Link);
256        }
257
258        format Branch {
259            0x4: decode RS_RT  {
260                0x0: b({{ cond = 1; }});
261                default: beq({{ cond = (Rs.sw == Rt.sw); }});
262            }
263            0x5: bne({{ cond = (Rs.sw != Rt.sw); }});
264            0x6: blez({{ cond = (Rs.sw <= 0); }});
265            0x7: bgtz({{ cond = (Rs.sw > 0); }});
266        }
267    }
268
269    0x1: decode OPCODE_LO {
270        format IntImmOp {
271            0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}});
272            0x1: addiu({{ Rt.sw = Rs.sw + imm;}});
273            0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }});
274
275            //Edited to include MIPS AVP Pass/Fail instructions and
276            //default to the sltiu instruction
277            0x3: decode RS_RT_INTIMM {
278                0xabc1: BasicOp::fail({{ exitSimLoop("AVP/SRVP Test Failed"); }});
279                0xabc2: BasicOp::pass({{ exitSimLoop("AVP/SRVP Test Passed"); }});
280              default: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }});
281            }
282
283            0x4: andi({{ Rt.sw = Rs.sw & zextImm;}});
284            0x5: ori({{ Rt.sw = Rs.sw | zextImm;}});
285            0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}});
286
287            0x7: decode RS {
288                0x0: lui({{ Rt = imm << 16}});
289            }
290        }
291    }
292
293    0x2: decode OPCODE_LO {
294        //Table A-11 MIPS32 COP0 Encoding of rs Field
295        0x0: decode RS_MSB {
296            0x0: decode RS {
297                format CP0Control {
298                    0x0: mfc0({{  Rt = CP0_RD_SEL; }});
299                    0x4: mtc0({{  CP0_RD_SEL = Rt; }});
300                }
301
302
303                format MT_MFTR { // Decode MIPS MT MFTR instruction into sub-instructions
304                    0x8: decode MT_U {
305                        0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) +
306                                                                    Ctrl_Base_DepTag);
307                                   }});
308                        0x1: decode SEL {
309                            0x0: mftgpr({{ data = xc->readRegOtherThread(RT); }});
310                            0x1: decode RT {
311                                0x0: mftlo_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPLo0); }});
312                                0x1: mfthi_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPHi0); }});
313                                0x2: mftacx_dsp0({{ data = xc->readRegOtherThread(MipsISA::DSPACX0); }});
314                                0x4: mftlo_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPLo1); }});
315                                0x5: mfthi_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPHi1); }});
316                                0x6: mftacx_dsp1({{ data = xc->readRegOtherThread(MipsISA::DSPACX1); }});
317                                0x8: mftlo_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPLo2); }});
318                                0x9: mfthi_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPHi2); }});
319                                0x10: mftacx_dsp2({{ data = xc->readRegOtherThread(MipsISA::DSPACX2); }});
320                                0x12: mftlo_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPLo3); }});
321                                0x13: mfthi_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPHi3); }});
322                                0x14: mftacx_dsp3({{ data = xc->readRegOtherThread(MipsISA::DSPACX3); }});
323                                0x16: mftdsp({{ data = xc->readRegOtherThread(MipsISA::DSPControl); }});
324                            }
325                            0x2: decode MT_H {
326                                0x0: mftc1({{ data = xc->readRegOtherThread(RT +
327                                                                            FP_Base_DepTag);
328                                           }});
329                                0x1: mfthc1({{ data = xc->readRegOtherThread(RT +
330                                                                             FP_Base_DepTag);
331                                           }});
332                            }
333                            0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(MipsISA::FCSR +
334                                                                            FP_Base_DepTag);
335                                          switch (RT)
336                                          {
337                                               case 0:
338                                                 data = xc->readRegOtherThread(MipsISA::FIR +
339                                                                               Ctrl_Base_DepTag);
340                                                 break;
341                                               case 25:
342                                                 data = 0 | fcsr_val & 0xFE000000 >> 24
343                                                          | fcsr_val & 0x00800000 >> 23;
344                                                 break;
345                                               case 26:
346                                                 data = 0 | fcsr_val & 0x0003F07C;
347                                                 break;
348                                               case 28:
349                                                 data = 0 | fcsr_val & 0x00000F80
350                                                          | fcsr_val & 0x01000000 >> 21
351                                                          | fcsr_val & 0x00000003;
352                                                 break;
353                                               case 31:
354                                                 data = fcsr_val;
355                                                 break;
356                                               default:
357                                                 fatal("FP Control Value (%d) Not Valid");
358                                          }
359                                        }});
360                        }
361                    }
362                }
363
364                format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions
365                    0xC: decode MT_U {
366                        0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag,
367                                                            Rt);
368                                   }});
369                        0x1: decode SEL {
370                            0x0: mttgpr({{ xc->setRegOtherThread(RD, Rt); }});
371                            0x1: decode RT {
372                                0x0: mttlo_dsp0({{ xc->setRegOtherThread(MipsISA::DSPLo0, Rt);
373                                                }});
374                                0x1: mtthi_dsp0({{ xc->setRegOtherThread(MipsISA::DSPHi0,
375                                                                         Rt);
376                                                }});
377                                0x2: mttacx_dsp0({{ xc->setRegOtherThread(MipsISA::DSPACX0,
378                                                                          Rt);
379                                                 }});
380                                0x4: mttlo_dsp1({{ xc->setRegOtherThread(MipsISA::DSPLo1,
381                                                                         Rt);
382                                                }});
383                                0x5: mtthi_dsp1({{ xc->setRegOtherThread(MipsISA::DSPHi1,
384                                                                         Rt);
385                                                }});
386                                0x6: mttacx_dsp1({{ xc->setRegOtherThread(MipsISA::DSPACX1,
387                                                                          Rt);
388                                                 }});
389                                0x8: mttlo_dsp2({{ xc->setRegOtherThread(MipsISA::DSPLo2,
390                                                                         Rt);
391                                                }});
392                                0x9: mtthi_dsp2({{ xc->setRegOtherThread(MipsISA::DSPHi2,
393                                                                         Rt);
394                                                }});
395                                0x10: mttacx_dsp2({{ xc->setRegOtherThread(MipsISA::DSPACX2,
396                                                                           Rt);
397                                                  }});
398                                0x12: mttlo_dsp3({{ xc->setRegOtherThread(MipsISA::DSPLo3,
399                                                                          Rt);
400                                                 }});
401                                0x13: mtthi_dsp3({{ xc->setRegOtherThread(MipsISA::DSPHi3,
402                                                                          Rt);
403                                                 }});
404                                0x14: mttacx_dsp3({{ xc->setRegOtherThread(MipsISA::DSPACX3, Rt);
405                                                  }});
406                                0x16: mttdsp({{ xc->setRegOtherThread(MipsISA::DSPControl, Rt); }});
407                            }
408                            0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD +
409                                                                                FP_Base_DepTag);
410                                          data = insertBits(data, top_bit, bottom_bit, Rt);
411                                          xc->setRegOtherThread(RD + FP_Base_DepTag, data);
412                                       }});
413                            0x3: cttc1({{ uint32_t data;
414                                          switch (RD)
415                                          {
416                                            case 25:
417                                              data = 0 | (Rt.uw<7:1> << 25) // move 31...25
418                                                  | (FCSR & 0x01000000) // bit 24
419                                                  | (FCSR & 0x004FFFFF);// bit 22...0
420                                              break;
421
422                                            case 26:
423                                              data = 0 | (FCSR & 0xFFFC0000) // move 31...18
424                                                  | Rt.uw<17:12> << 12           // bit 17...12
425                                                  | (FCSR & 0x00000F80) << 7// bit 11...7
426                                                  | Rt.uw<6:2> << 2              // bit 6...2
427                                                  | (FCSR & 0x00000002);     // bit 1...0
428                                              break;
429
430                                            case 28:
431                                              data = 0 | (FCSR & 0xFE000000) // move 31...25
432                                                  | Rt.uw<2:2> << 24       // bit 24
433                                                  | (FCSR & 0x00FFF000) << 23// bit 23...12
434                                                  | Rt.uw<11:7> << 7       // bit 24
435                                                  | (FCSR & 0x000007E)
436                                                  | Rt.uw<1:0>;// bit 22...0
437                                              break;
438
439                                            case 31:
440                                              data  = Rt.uw;
441                                              break;
442
443                                            default:
444                                              panic("FP Control Value (%d) Not Available. Ignoring Access to"
445                                                    "Floating Control Status Register", FS);
446                                          }
447                                          xc->setRegOtherThread(FCSR, data);
448                                       }});
449                        }
450                    }
451                }
452
453
454                0xB: decode RD {
455                    format MT_Control {
456                        0x0: decode POS {
457                            0x0: decode SEL {
458                                0x1: decode SC {
459                                    0x0: dvpe({{ Rt = MVPControl;
460                                                 if (VPEConf0<VPEC0_MVP:> == 1) {
461                                                     MVPControl = insertBits(MVPControl, MVPC_EVP, 0);
462                                                 }
463                                              }});
464                                    0x1: evpe({{ Rt = MVPControl;
465                                                 if (VPEConf0<VPEC0_MVP:> == 1) {
466                                                     MVPControl = insertBits(MVPControl, MVPC_EVP, 1);
467                                                 }
468                                              }});
469                                }
470                            }
471                        }
472
473                        0x1: decode POS {
474                            0xF: decode SEL {
475                                0x1: decode SC {
476                                    0x0: dmt({{ Rt = VPEControl;
477                                                VPEControl = insertBits(VPEControl, VPEC_TE, 0);
478                                         }});
479                                    0x1: emt({{ Rt = VPEControl;
480                                                VPEControl = insertBits(VPEControl, VPEC_TE, 1);
481                                         }});
482
483                                }
484                            }
485                        }
486                    }
487                    0xC: decode POS {
488                      0x0: decode SC {
489                        0x0: CP0Control::di({{
490                            if(Config_AR >= 1) // Rev 2.0 or beyond?
491                                {
492                                  Rt = Status;
493                                  Status_IE = 0;
494                                }
495                            else // Enable this else branch once we actually set values for Config on init
496                              {
497                                fault = new ReservedInstructionFault();
498                              }
499                          }});
500                        0x1: CP0Control::ei({{
501                            if(Config_AR >= 1)
502                              {
503                                Rt = Status;
504                                Status_IE = 1;
505                              }
506                            else
507                              {
508                                fault = new ReservedInstructionFault();
509                              }
510                          }});
511                      }
512                    }
513                }
514
515                format CP0Control {
516                    0xA: rdpgpr({{
517                      if(Config_AR >= 1)
518                        { // Rev 2 of the architecture
519                          Rd = xc->tcBase()->readIntReg(Rt + NumIntRegs * SRSCtl_PSS);
520                        }
521                      else
522                        {
523                          fault = new ReservedInstructionFault();
524                        }
525                         }});
526                    0xE: wrpgpr({{
527                      if(Config_AR >= 1)
528                        { // Rev 2 of the architecture
529                          xc->tcBase()->setIntReg(Rd + NumIntRegs * SRSCtl_PSS,Rt);
530                        }
531                      else
532                        {
533                          fault = new ReservedInstructionFault();
534                        }
535
536                         }});
537
538                }
539
540            }
541
542            //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO
543            0x1: decode FUNCTION {
544              format CP0Control {
545                0x18: eret({{
546                  if(Status_ERL == 1){
547                    Status_ERL = 0;
548                    NPC = ErrorEPC;
549                  }
550                  else{
551                    NPC = EPC;
552                    Status_EXL = 0;
553                    if(Config_AR >= 1 && SRSCtl_HSS > 0 && Status_BEV == 0){
554                      SRSCtl_CSS = SRSCtl_PSS;
555                    }
556                  }
557                  //		  LLFlag = 0;
558                  // ClearHazards(); ?
559                }});
560
561                0x1F: deret({{
562                    //if(Debug_DM == 1){
563                    //Debug_DM = 1;
564                    //Debug_IEXI = 0;
565                    //NPC = DEPC;
566                    //}
567                    panic("deret not implemented");
568                }});
569              }
570
571              format FailUnimpl {
572                  0x01: tlbr(); // Need to hook up to TLB
573                  0x02: tlbwi(); // Need to hook up to TLB
574                    0x06: tlbwr();// Need to hook up to TLB
575                    0x08: tlbp();// Need to hook up to TLB
576
577                    0x20: wait();
578                }
579
580            }
581        }
582
583        //Table A-13 MIPS32 COP1 Encoding of rs Field
584        0x1: decode RS_MSB {
585
586            0x0: decode RS_HI {
587                0x0: decode RS_LO {
588                    format CP1Control {
589                        0x0: mfc1 ({{ Rt.uw = Fs.uw; }});
590
591                        0x2: cfc1({{
592                            switch (FS)
593                            {
594                              case 0:
595                                Rt = FIR;
596                                break;
597                              case 25:
598                                Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23;
599                                break;
600                              case 26:
601                                Rt = 0 | (FCSR & 0x0003F07C);
602                                break;
603                              case 28:
604                                Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003);
605                                break;
606                              case 31:
607                                Rt = FCSR;
608                                break;
609                              default:
610                                panic("FP Control Value (%d) Not Valid");
611                            }
612                        }});
613
614                        0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}});
615
616                        0x4: mtc1 ({{ Fs.uw = Rt.uw;       }});
617
618                        0x6: ctc1({{
619                            switch (FS)
620                            {
621                              case 25:
622                                FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25
623                                    | (FCSR & 0x01000000) // bit 24
624                                    | (FCSR & 0x004FFFFF);// bit 22...0
625                                break;
626
627                              case 26:
628                                FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18
629                                    | Rt.uw<17:12> << 12           // bit 17...12
630                                    | (FCSR & 0x00000F80) << 7// bit 11...7
631                                    | Rt.uw<6:2> << 2              // bit 6...2
632                                    | (FCSR & 0x00000002);     // bit 1...0
633                                break;
634
635                              case 28:
636                                FCSR = 0 | (FCSR & 0xFE000000) // move 31...25
637                                    | Rt.uw<2:2> << 24       // bit 24
638                                    | (FCSR & 0x00FFF000) << 23// bit 23...12
639                                    | Rt.uw<11:7> << 7       // bit 24
640                                    | (FCSR & 0x000007E)
641                                    | Rt.uw<1:0>;// bit 22...0
642                                break;
643
644                              case 31:
645                                FCSR  = Rt.uw;
646                                break;
647
648                              default:
649                                panic("FP Control Value (%d) Not Available. Ignoring Access to"
650                                      "Floating Control Status Register", FS);
651                            }
652                        }});
653
654                        0x7: mthc1({{
655                             uint64_t fs_hi = Rt.uw;
656                             uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF;
657                             Fs.ud = (fs_hi << 32) | fs_lo;
658                        }});
659
660                    }
661                }
662
663                0x1: decode ND {
664                    format Branch {
665                        0x0: decode TF {
666                            0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
667                                      }});
668                            0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
669                                      }});
670                        }
671                        0x1: decode TF {
672                            0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0;
673                                       }}, Likely);
674                            0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1;
675                                       }}, Likely);
676                        }
677                    }
678                }
679            }
680
681            0x1: decode RS_HI {
682                0x2: decode RS_LO {
683                    //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S
684                    //(( single-precision floating point))
685                    0x0: decode FUNCTION_HI {
686                        0x0: decode FUNCTION_LO {
687                            format FloatOp {
688                                0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}});
689                                0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}});
690                                0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}});
691                                0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}});
692                                0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}});
693                                0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}});
694                                0x7: neg_s({{ Fd.sf = -Fs.sf;}});
695                            }
696
697                            0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}});
698                        }
699
700                        0x1: decode FUNCTION_LO {
701                            format FloatConvertOp {
702                                0x0: round_l_s({{ val = Fs.sf; }}, ToLong,
703                                               Round);
704                                0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong,
705                                               Trunc);
706                                0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong,
707                                               Ceil);
708                                0x3: floor_l_s({{ val = Fs.sf; }}, ToLong,
709                                               Floor);
710                                0x4: round_w_s({{ val = Fs.sf; }}, ToWord,
711                                               Round);
712                                0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord,
713                                               Trunc);
714                                0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord,
715                                               Ceil);
716                                0x7: floor_w_s({{ val = Fs.sf; }}, ToWord,
717                                               Floor);
718                            }
719                        }
720
721                        0x2: decode FUNCTION_LO {
722                            0x1: decode MOVCF {
723                                format BasicOp {
724                                    0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }});
725                                    0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }});
726                                }
727                            }
728
729                            format BasicOp {
730                                0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }});
731                                0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }});
732                            }
733
734                            format FloatOp {
735                                0x5: recip_s({{ Fd = 1 / Fs; }});
736                                0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}});
737                            }
738                        }
739
740                        0x4: decode FUNCTION_LO {
741                            format FloatConvertOp {
742                                0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble);
743                                0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord);
744                                0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong);
745                            }
746
747                            0x6: FloatOp::cvt_ps_s({{
748                                    Fd.ud = (uint64_t) Fs.uw << 32 |
749                                            (uint64_t) Ft.uw;
750                                }});
751                        }
752
753                        0x6: decode FUNCTION_LO {
754                            format FloatCompareOp {
755                                0x0: c_f_s({{ cond = 0; }}, SinglePrecision,
756                                           UnorderedFalse);
757                                0x1: c_un_s({{ cond = 0; }}, SinglePrecision,
758                                            UnorderedTrue);
759                                0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }},
760                                            UnorderedFalse);
761                                0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }},
762                                             UnorderedTrue);
763                                0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf);	}},
764                                             UnorderedFalse);
765                                0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }},
766                                             UnorderedTrue);
767                                0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }},
768                                             UnorderedFalse);
769                                0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }},
770                                             UnorderedTrue);
771                            }
772                        }
773
774                        0x7: decode FUNCTION_LO {
775                            format FloatCompareOp {
776                                0x0: c_sf_s({{ cond = 0; }}, SinglePrecision,
777                                            UnorderedFalse, QnanException);
778                                0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision,
779                                              UnorderedTrue, QnanException);
780                                0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}},
781                                             UnorderedFalse, QnanException);
782                                0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }},
783                                             UnorderedTrue, QnanException);
784                                0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }},
785                                            UnorderedFalse, QnanException);
786                                0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }},
787                                             UnorderedTrue, QnanException);
788                                0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }},
789                                            UnorderedFalse, QnanException);
790                                0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }},
791                                             UnorderedTrue, QnanException);
792                            }
793                        }
794                    }
795
796                    //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D
797                    0x1: decode FUNCTION_HI {
798                        0x0: decode FUNCTION_LO {
799                            format FloatOp {
800                                0x0: add_d({{ Fd.df = Fs.df + Ft.df; }});
801                                0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }});
802                                0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }});
803                                0x3: div_d({{ Fd.df = Fs.df / Ft.df; }});
804                                0x4: sqrt_d({{ Fd.df = sqrt(Fs.df);  }});
805                                0x5: abs_d({{ Fd.df = fabs(Fs.df);   }});
806                                0x7: neg_d({{ Fd.df = -1 * Fs.df;    }});
807                            }
808
809                            0x6: BasicOp::mov_d({{ Fd.df = Fs.df;    }});
810                        }
811
812                        0x1: decode FUNCTION_LO {
813                            format FloatConvertOp {
814                                0x0: round_l_d({{ val = Fs.df; }}, ToLong,
815                                               Round);
816                                0x1: trunc_l_d({{ val = Fs.df; }}, ToLong,
817                                               Trunc);
818                                0x2: ceil_l_d({{ val = Fs.df; }}, ToLong,
819                                               Ceil);
820                                0x3: floor_l_d({{ val = Fs.df; }}, ToLong,
821                                               Floor);
822                                0x4: round_w_d({{ val = Fs.df; }}, ToWord,
823                                               Round);
824                                0x5: trunc_w_d({{ val = Fs.df; }}, ToWord,
825                                               Trunc);
826                                0x6: ceil_w_d({{ val = Fs.df; }}, ToWord,
827                                               Ceil);
828                                0x7: floor_w_d({{ val = Fs.df; }}, ToWord,
829                                               Floor);
830                            }
831                        }
832
833                        0x2: decode FUNCTION_LO {
834                            0x1: decode MOVCF {
835                                format BasicOp {
836                                    0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ?
837                                                       Fs.df : Fd.df;
838                                                }});
839                                    0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ?
840                                                       Fs.df : Fd.df;
841                                                }});
842                                }
843                            }
844
845                            format BasicOp {
846                                0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }});
847                                0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }});
848                            }
849
850                            format FloatOp {
851                                0x5: recip_d({{ Fd.df = 1 / Fs.df }});
852                                0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }});
853                            }
854                        }
855
856                        0x4: decode FUNCTION_LO {
857                            format FloatConvertOp {
858                                0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle);
859                                0x4: cvt_w_d({{ val = Fs.df; }}, ToWord);
860                                0x5: cvt_l_d({{ val = Fs.df; }}, ToLong);
861                            }
862                        }
863
864                        0x6: decode FUNCTION_LO {
865                            format FloatCompareOp {
866                                0x0: c_f_d({{ cond = 0; }}, DoublePrecision,
867                                           UnorderedFalse);
868                                0x1: c_un_d({{ cond = 0; }}, DoublePrecision,
869                                            UnorderedTrue);
870                                0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }},
871                                            UnorderedFalse);
872                                0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }},
873                                             UnorderedTrue);
874                                0x4: c_olt_d({{ cond = (Fs.df < Ft.df);	}},
875                                             UnorderedFalse);
876                                0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }},
877                                             UnorderedTrue);
878                                0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }},
879                                             UnorderedFalse);
880                                0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }},
881                                             UnorderedTrue);
882                            }
883                        }
884
885                        0x7: decode FUNCTION_LO {
886                            format FloatCompareOp {
887                                0x0: c_sf_d({{ cond = 0; }}, DoublePrecision,
888                                            UnorderedFalse, QnanException);
889                                0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision,
890                                              UnorderedTrue, QnanException);
891                                0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }},
892                                             UnorderedFalse, QnanException);
893                                0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }},
894                                             UnorderedTrue, QnanException);
895                                0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }},
896                                            UnorderedFalse, QnanException);
897                                0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }},
898                                             UnorderedTrue, QnanException);
899                                0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }},
900                                            UnorderedFalse, QnanException);
901                                0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }},
902                                             UnorderedTrue, QnanException);
903                            }
904                        }
905                    }
906
907                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W
908                    0x4: decode FUNCTION {
909                        format FloatConvertOp {
910                            0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle);
911                            0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble);
912                            0x26: FailUnimpl::cvt_ps_w();
913                        }
914                    }
915
916                    //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1
917                    //Note: "1. Format type L is legal only if 64-bit floating point operations
918                    //are enabled."
919                    0x5: decode FUNCTION_HI {
920                        format FloatConvertOp {
921                            0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle);
922                            0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble);
923                            0x26: FailUnimpl::cvt_ps_l();
924                        }
925                    }
926
927                    //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1
928                    //Note: "1. Format type PS is legal only if 64-bit floating point operations
929                    //are enabled. "
930                    0x6: decode FUNCTION_HI {
931                        0x0: decode FUNCTION_LO {
932                            format Float64Op {
933                                0x0: add_ps({{
934                                    Fd1.sf = Fs1.sf + Ft2.sf;
935                                    Fd2.sf = Fs2.sf + Ft2.sf;
936                                }});
937                                0x1: sub_ps({{
938                                    Fd1.sf = Fs1.sf - Ft2.sf;
939                                    Fd2.sf = Fs2.sf - Ft2.sf;
940                                }});
941                                0x2: mul_ps({{
942                                    Fd1.sf = Fs1.sf * Ft2.sf;
943                                    Fd2.sf = Fs2.sf * Ft2.sf;
944                                }});
945                                0x5: abs_ps({{
946                                    Fd1.sf = fabs(Fs1.sf);
947                                    Fd2.sf = fabs(Fs2.sf);
948                                }});
949                                0x6: mov_ps({{
950                                    Fd1.sf = Fs1.sf;
951                                    Fd2.sf = Fs2.sf;
952                                }});
953                                0x7: neg_ps({{
954                                    Fd1.sf = -(Fs1.sf);
955                                    Fd2.sf = -(Fs2.sf);
956                                }});
957                            }
958                        }
959
960                        0x2: decode FUNCTION_LO {
961                            0x1: decode MOVCF {
962                                format Float64Op {
963                                    0x0: movf_ps({{
964                                        Fd1 = (getCondCode(FCSR, CC) == 0) ?
965                                            Fs1 : Fd1;
966                                        Fd2 = (getCondCode(FCSR, CC+1) == 0) ?
967                                            Fs2 : Fd2;
968                                    }});
969                                    0x1: movt_ps({{
970                                        Fd2 = (getCondCode(FCSR, CC) == 1) ?
971                                            Fs1 : Fd1;
972                                        Fd2 = (getCondCode(FCSR, CC+1) == 1) ?
973                                            Fs2 : Fd2;
974                                    }});
975                                }
976                            }
977
978                            format Float64Op {
979                                0x2: movz_ps({{
980                                    Fd1 = (getCondCode(FCSR, CC) == 0) ?
981                                        Fs1 : Fd1;
982                                    Fd2 = (getCondCode(FCSR, CC) == 0) ?
983                                        Fs2 : Fd2;
984                                }});
985                                0x3: movn_ps({{
986                                    Fd1 = (getCondCode(FCSR, CC) == 1) ?
987                                        Fs1 : Fd1;
988                                    Fd2 = (getCondCode(FCSR, CC) == 1) ?
989                                        Fs2 : Fd2;
990                                }});
991                            }
992
993                        }
994
995                        0x4: decode FUNCTION_LO {
996                            0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }});
997                        }
998
999                        0x5: decode FUNCTION_LO {
1000                            0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }});
1001
1002                            format Float64Op {
1003                                0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1004                                                    Ft1.uw;
1005                                         }});
1006                                0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 |
1007                                                    Ft2.uw;
1008                                         }});
1009                                0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1010                                                    Ft1.uw;
1011                                         }});
1012                                0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 |
1013                                                    Ft2.uw;
1014                                         }});
1015                            }
1016                        }
1017
1018                        0x6: decode FUNCTION_LO {
1019                            format FloatPSCompareOp {
1020                                0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1021                                            UnorderedFalse);
1022                                0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1023                                             UnorderedTrue);
1024                                0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1025                                             {{ cond2 = (Fs2.sf == Ft2.sf); }},
1026                                             UnorderedFalse);
1027                                0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1028                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
1029                                              UnorderedTrue);
1030                                0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
1031                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
1032                                              UnorderedFalse);
1033                                0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }},
1034                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
1035                                              UnorderedTrue);
1036                                0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }},
1037                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1038                                              UnorderedFalse);
1039                                0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1040                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1041                                              UnorderedTrue);
1042                            }
1043                        }
1044
1045                        0x7: decode FUNCTION_LO {
1046                            format FloatPSCompareOp {
1047                                0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }},
1048                                             UnorderedFalse, QnanException);
1049                                0x1: c_ngle_ps({{ cond1 = 0; }},
1050                                               {{ cond2 = 0; }},
1051                                               UnorderedTrue, QnanException);
1052                                0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1053                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
1054                                              UnorderedFalse, QnanException);
1055                                0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }},
1056                                              {{ cond2 = (Fs2.sf == Ft2.sf); }},
1057                                              UnorderedTrue, QnanException);
1058                                0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
1059                                             {{ cond2 = (Fs2.sf < Ft2.sf); }},
1060                                             UnorderedFalse, QnanException);
1061                                0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }},
1062                                              {{ cond2 = (Fs2.sf < Ft2.sf); }},
1063                                              UnorderedTrue, QnanException);
1064                                0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1065                                             {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1066                                             UnorderedFalse, QnanException);
1067                                0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }},
1068                                              {{ cond2 = (Fs2.sf <= Ft2.sf); }},
1069                                              UnorderedTrue, QnanException);
1070                            }
1071                        }
1072                    }
1073                }
1074            }
1075        }
1076
1077        //Table A-19 MIPS32 COP2 Encoding of rs Field
1078        0x2: decode RS_MSB {
1079            format FailUnimpl {
1080                0x0: decode RS_HI {
1081                    0x0: decode RS_LO {
1082                        0x0: mfc2();
1083                        0x2: cfc2();
1084                        0x3: mfhc2();
1085                        0x4: mtc2();
1086                        0x6: ctc2();
1087                        0x7: mftc2();
1088                    }
1089
1090                    0x1: decode ND {
1091                        0x0: decode TF {
1092                            0x0: bc2f();
1093                            0x1: bc2t();
1094                        }
1095
1096                        0x1: decode TF {
1097                            0x0: bc2fl();
1098                            0x1: bc2tl();
1099                        }
1100                    }
1101                }
1102            }
1103        }
1104
1105        //Table A-20 MIPS64 COP1X Encoding of Function Field 1
1106        //Note: "COP1X instructions are legal only if 64-bit floating point
1107        //operations are enabled."
1108        0x3: decode FUNCTION_HI {
1109            0x0: decode FUNCTION_LO {
1110                format LoadIndexedMemory {
1111                    0x0: lwxc1({{ Fd.uw = Mem.uw;}});
1112                    0x1: ldxc1({{ Fd.ud = Mem.ud;}});
1113                    0x5: luxc1({{ Fd.ud = Mem.ud;}},
1114                               {{ EA = (Rs + Rt) & ~7; }});
1115                }
1116            }
1117
1118            0x1: decode FUNCTION_LO {
1119                format StoreIndexedMemory {
1120                    0x0: swxc1({{ Mem.uw = Fs.uw;}});
1121                    0x1: sdxc1({{ Mem.ud = Fs.ud;}});
1122                    0x5: suxc1({{ Mem.ud = Fs.ud;}},
1123                               {{ EA = (Rs + Rt) & ~7; }});
1124                }
1125
1126                0x7: Prefetch::prefx({{ EA = Rs + Rt; }});
1127            }
1128
1129            0x3: decode FUNCTION_LO {
1130                0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) {
1131                                               Fd.ud = Fs.ud;
1132                                           } else if (Rs<2:0> == 4) {
1133                                             #if BYTE_ORDER == BIG_ENDIAN
1134                                               Fd.ud = Fs.ud<31:0> << 32 |
1135                                                       Ft.ud<63:32>;
1136                                             #elif BYTE_ORDER == LITTLE_ENDIAN
1137                                               Fd.ud = Ft.ud<31:0> << 32 |
1138                                                       Fs.ud<63:32>;
1139                                             #endif
1140                                           } else {
1141                                               Fd.ud = Fd.ud;
1142                                           }
1143                                        }});
1144            }
1145
1146            format FloatAccOp {
1147                0x4: decode FUNCTION_LO {
1148                    0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }});
1149                    0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }});
1150                    0x6: madd_ps({{
1151                        Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df;
1152                        Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df;
1153                    }});
1154                }
1155
1156                0x5: decode FUNCTION_LO {
1157                    0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }});
1158                    0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }});
1159                    0x6: msub_ps({{
1160                        Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df;
1161                        Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df;
1162                    }});
1163                }
1164
1165                0x6: decode FUNCTION_LO {
1166                    0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
1167                    0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }});
1168                    0x6: nmadd_ps({{
1169                        Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df);
1170                        Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df);
1171                    }});
1172                }
1173
1174                0x7: decode FUNCTION_LO {
1175                    0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }});
1176                    0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }});
1177                    0x6: nmsub_ps({{
1178                        Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df);
1179                        Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df);
1180                    }});
1181                }
1182
1183            }
1184        }
1185
1186        format Branch {
1187            0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely);
1188            0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely);
1189            0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely);
1190            0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely);
1191        }
1192    }
1193
1194    0x3: decode OPCODE_LO {
1195        //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field
1196        0x4: decode FUNCTION_HI {
1197            0x0: decode FUNCTION_LO {
1198                0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd;
1199                                   Rd.sw = temp1<31:0>;
1200                                }});
1201
1202                format HiLoRdSelValOp {
1203                    0x0: madd({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.sd * Rt.sd); }});
1204                    0x1: maddu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) + (Rs.ud * Rt.ud); }});
1205                    0x4: msub({{ val = ((int64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.sd * Rt.sd); }});
1206                    0x5: msubu({{ val = ((uint64_t)HI_RD_SEL << 32 | LO_RD_SEL) - (Rs.ud * Rt.ud); }});
1207                }
1208            }
1209
1210            0x4: decode FUNCTION_LO {
1211                format BasicOp {
1212                    0x0: clz({{ int cnt = 32;
1213                          for (int idx = 31; idx >= 0; idx--) {
1214                              if( Rs<idx:idx> == 1) {
1215                                  cnt = 31 - idx;
1216                                  break;
1217                              }
1218                          }
1219                          Rd.uw = cnt;
1220                       }});
1221                    0x1: clo({{ int cnt = 32;
1222                          for (int idx = 31; idx >= 0; idx--) {
1223                              if( Rs<idx:idx> == 0) {
1224                                  cnt = 31 - idx;
1225                                  break;
1226                              }
1227                          }
1228                          Rd.uw = cnt;
1229                        }});
1230                }
1231            }
1232
1233            0x7: decode FUNCTION_LO {
1234                0x7: FailUnimpl::sdbbp();
1235            }
1236        }
1237
1238        //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2
1239        //of the Architecture
1240        0x7: decode FUNCTION_HI {
1241            0x0: decode FUNCTION_LO {
1242                format BasicOp {
1243                    0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }});
1244                    0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) |
1245                                        bits(Rs.uw, MSB-LSB, 0) << LSB |
1246                                        bits(Rt.uw, LSB-1, 0);
1247                             }});
1248                }
1249            }
1250
1251            0x1: decode FUNCTION_LO {
1252                format MT_Control {
1253                    0x0: fork({{ forkThread(xc->tcBase(), fault, RD, Rs, Rt); }},
1254                              UserMode);
1255                    0x1: yield({{ Rd.sw = yieldThread(xc->tcBase(), fault, Rs.sw, YQMask); }},
1256                               UserMode);
1257                }
1258
1259                //Table 5-9 MIPS32 LX Encoding of the op Field (DSP ASE MANUAL)
1260                0x2: decode OP_HI {
1261                    0x0: decode OP_LO {
1262                        format LoadIndexedMemory {
1263                            0x0: lwx({{ Rd.sw = Mem.sw; }});
1264                            0x4: lhx({{ Rd.sw = Mem.sh; }});
1265                            0x6: lbux({{ Rd.uw = Mem.ub; }});
1266                        }
1267                    }
1268                }
1269                0x4: DspIntOp::insv({{ int pos = dspctl<5:0>;
1270                                       int size = dspctl<12:7>-1;
1271                                       Rt.uw = insertBits( Rt.uw, pos+size, pos, Rs.uw<size:0> ); }});
1272            }
1273
1274            0x2: decode FUNCTION_LO {
1275
1276                //Table 5-5 MIPS32 ADDU.QB Encoding of the op Field (DSP ASE MANUAL)
1277                0x0: decode OP_HI {
1278                    0x0: decode OP_LO {
1279                        format DspIntOp {
1280                            0x0: addu_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1281                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1282                            0x1: subu_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1283                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1284                            0x4: addu_s_qb({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1285                                                              SATURATE, UNSIGNED, &dspctl ); }});
1286                            0x5: subu_s_qb({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_QB,
1287                                                              SATURATE, UNSIGNED, &dspctl ); }});
1288                            0x6: muleu_s_ph_qbl({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1289                                                                     MODE_L, &dspctl ); }});
1290                            0x7: muleu_s_ph_qbr({{ Rd.uw = dspMuleu( Rs.uw, Rt.uw,
1291                                                                     MODE_R, &dspctl ); }});
1292                        }
1293                    }
1294                    0x1: decode OP_LO {
1295                        format DspIntOp {
1296                            0x0: addu_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1297                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1298                            0x1: subu_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1299                                                            NOSATURATE, UNSIGNED, &dspctl ); }});
1300                            0x2: addq_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1301                                                            NOSATURATE, SIGNED, &dspctl ); }});
1302                            0x3: subq_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1303                                                            NOSATURATE, SIGNED, &dspctl ); }});
1304                            0x4: addu_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1305                                                              SATURATE, UNSIGNED, &dspctl ); }});
1306                            0x5: subu_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1307                                                              SATURATE, UNSIGNED, &dspctl ); }});
1308                            0x6: addq_s_ph({{ Rd.uw = dspAdd( Rs.uw, Rt.uw, SIMD_FMT_PH,
1309                                                              SATURATE, SIGNED, &dspctl ); }});
1310                            0x7: subq_s_ph({{ Rd.uw = dspSub( Rs.uw, Rt.uw, SIMD_FMT_PH,
1311                                                              SATURATE, SIGNED, &dspctl ); }});
1312                        }
1313                    }
1314                    0x2: decode OP_LO {
1315                        format DspIntOp {
1316                            0x0: addsc({{ int64_t dresult;
1317                                          dresult = Rs.ud + Rt.ud;
1318                                          Rd.sw = dresult<31:0>;
1319                                          dspctl = insertBits( dspctl, 13, 13,
1320                                                               dresult<32:32> ); }});
1321                            0x1: addwc({{ int64_t dresult;
1322                                          dresult = Rs.sd + Rt.sd + dspctl<13:13>;
1323                                          Rd.sw = dresult<31:0>;
1324                                          if( dresult<32:32> != dresult<31:31> )
1325                                              dspctl = insertBits( dspctl, 20, 20, 1 ); }});
1326                            0x2: modsub({{ Rd.sw = (Rs.sw == 0) ? Rt.sw<23:8> : Rs.sw - Rt.sw<7:0>; }});
1327                            0x4: raddu_w_qb({{ Rd.uw = Rs.uw<31:24> + Rs.uw<23:16> +
1328                                                   Rs.uw<15:8> + Rs.uw<7:0>; }});
1329                            0x6: addq_s_w({{ Rd.sw = dspAdd( Rs.sw, Rt.sw, SIMD_FMT_W,
1330                                                             SATURATE, SIGNED, &dspctl ); }});
1331                            0x7: subq_s_w({{ Rd.sw = dspSub( Rs.sw, Rt.sw, SIMD_FMT_W,
1332                                                             SATURATE, SIGNED, &dspctl ); }});
1333                        }
1334                    }
1335                    0x3: decode OP_LO {
1336                        format DspIntOp {
1337                            0x4: muleq_s_w_phl({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1338                                                                    MODE_L, &dspctl ); }});
1339                            0x5: muleq_s_w_phr({{ Rd.sw = dspMuleq( Rs.sw, Rt.sw,
1340                                                                    MODE_R, &dspctl ); }});
1341                            0x6: mulq_s_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1342                                                               SATURATE, NOROUND, &dspctl ); }});
1343                            0x7: mulq_rs_ph({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_PH,
1344                                                                SATURATE, ROUND, &dspctl ); }});
1345                        }
1346                    }
1347                }
1348
1349                //Table 5-6 MIPS32 CMPU_EQ_QB Encoding of the op Field (DSP ASE MANUAL)
1350                0x1: decode OP_HI {
1351                    0x0: decode OP_LO {
1352                        format DspIntOp {
1353                            0x0: cmpu_eq_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1354                                                       UNSIGNED, CMP_EQ, &dspctl ); }});
1355                            0x1: cmpu_lt_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1356                                                       UNSIGNED, CMP_LT, &dspctl ); }});
1357                            0x2: cmpu_le_qb({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_QB,
1358                                                       UNSIGNED, CMP_LE, &dspctl ); }});
1359                            0x3: pick_qb({{ Rd.uw = dspPick( Rs.uw, Rt.uw,
1360                                                             SIMD_FMT_QB, &dspctl ); }});
1361                            0x4: cmpgu_eq_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1362                                                                 UNSIGNED, CMP_EQ ); }});
1363                            0x5: cmpgu_lt_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1364                                                                 UNSIGNED, CMP_LT ); }});
1365                            0x6: cmpgu_le_qb({{ Rd.uw = dspCmpg( Rs.uw, Rt.uw, SIMD_FMT_QB,
1366                                                                 UNSIGNED, CMP_LE ); }});
1367                        }
1368                    }
1369                    0x1: decode OP_LO {
1370                        format DspIntOp {
1371                            0x0: cmp_eq_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1372                                                      SIGNED, CMP_EQ, &dspctl ); }});
1373                            0x1: cmp_lt_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1374                                                      SIGNED, CMP_LT, &dspctl ); }});
1375                            0x2: cmp_le_ph({{ dspCmp( Rs.uw, Rt.uw, SIMD_FMT_PH,
1376                                                      SIGNED, CMP_LE, &dspctl ); }});
1377                            0x3: pick_ph({{ Rd.uw = dspPick( Rs.uw, Rt.uw,
1378                                                             SIMD_FMT_PH, &dspctl ); }});
1379                            0x4: precrq_qb_ph({{ Rd.uw = Rs.uw<31:24> << 24 |
1380                                                         Rs.uw<15:8> << 16 |
1381                                                         Rt.uw<31:24> << 8 |
1382                                                         Rt.uw<15:8>; }});
1383                            0x5: precr_qb_ph({{ Rd.uw = Rs.uw<23:16> << 24 |
1384                                                         Rs.uw<7:0> << 16 |
1385                                                         Rt.uw<23:16> << 8 |
1386                                                         Rt.uw<7:0>; }});
1387                            0x6: packrl_ph({{ Rd.uw = dspPack( Rs.uw, Rt.uw,
1388                                                               SIMD_FMT_PH ); }});
1389                            0x7: precrqu_s_qb_ph({{ Rd.uw = dspPrecrqu( Rs.uw, Rt.uw, &dspctl ); }});
1390                        }
1391                    }
1392                    0x2: decode OP_LO {
1393                        format DspIntOp {
1394                            0x4: precrq_ph_w({{ Rd.uw = Rs.uw<31:16> << 16 | Rt.uw<31:16>; }});
1395                            0x5: precrq_rs_ph_w({{ Rd.uw = dspPrecrq( Rs.uw, Rt.uw, SIMD_FMT_W, &dspctl ); }});
1396                        }
1397                    }
1398                    0x3: decode OP_LO {
1399                        format DspIntOp {
1400                            0x0: cmpgdu_eq_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1401                                                                   UNSIGNED, CMP_EQ, &dspctl ); }});
1402                            0x1: cmpgdu_lt_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1403                                                                   UNSIGNED, CMP_LT, &dspctl  ); }});
1404                            0x2: cmpgdu_le_qb({{ Rd.uw = dspCmpgd( Rs.uw, Rt.uw, SIMD_FMT_QB,
1405                                                                   UNSIGNED, CMP_LE, &dspctl ); }});
1406                            0x6: precr_sra_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD,
1407                                                                        SIMD_FMT_W, NOROUND ); }});
1408                            0x7: precr_sra_r_ph_w({{ Rt.uw = dspPrecrSra( Rt.uw, Rs.uw, RD,
1409                                                                        SIMD_FMT_W, ROUND ); }});
1410                        }
1411                    }
1412                }
1413
1414                //Table 5-7 MIPS32 ABSQ_S.PH Encoding of the op Field (DSP ASE MANUAL)
1415                0x2: decode OP_HI {
1416                    0x0: decode OP_LO {
1417                        format DspIntOp {
1418                            0x1: absq_s_qb({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_QB, &dspctl );}});
1419                            0x2: repl_qb({{ Rd.uw = RS_RT<7:0> << 24 |
1420                                                    RS_RT<7:0> << 16 |
1421                                                    RS_RT<7:0> << 8 |
1422                                                    RS_RT<7:0>; }});
1423                            0x3: replv_qb({{ Rd.sw = Rt.uw<7:0> << 24 |
1424                                                     Rt.uw<7:0> << 16 |
1425                                                     Rt.uw<7:0> << 8 |
1426                                                     Rt.uw<7:0>; }});
1427                            0x4: precequ_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1428                                                                     SIMD_FMT_PH, SIGNED, MODE_L ); }});
1429                            0x5: precequ_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1430                                                                     SIMD_FMT_PH, SIGNED, MODE_R ); }});
1431                            0x6: precequ_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1432                                                                      SIMD_FMT_PH, SIGNED, MODE_LA ); }});
1433                            0x7: precequ_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1434                                                                      SIMD_FMT_PH, SIGNED, MODE_RA ); }});
1435                        }
1436                    }
1437                    0x1: decode OP_LO {
1438                        format DspIntOp {
1439                            0x1: absq_s_ph({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_PH, &dspctl ); }});
1440                            0x2: repl_ph({{ Rd.uw = (sext<10>(RS_RT))<15:0> << 16 |
1441                                                    (sext<10>(RS_RT))<15:0>; }});
1442                            0x3: replv_ph({{ Rd.uw = Rt.uw<15:0> << 16 |
1443                                                     Rt.uw<15:0>; }});
1444                            0x4: preceq_w_phl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED,
1445                                                                   SIMD_FMT_W, SIGNED, MODE_L ); }});
1446                            0x5: preceq_w_phr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_PH, SIGNED,
1447                                                                   SIMD_FMT_W, SIGNED, MODE_R ); }});
1448                        }
1449                    }
1450                    0x2: decode OP_LO {
1451                        format DspIntOp {
1452                            0x1: absq_s_w({{ Rd.sw = dspAbs( Rt.sw, SIMD_FMT_W, &dspctl ); }});
1453                        }
1454                    }
1455                    0x3: decode OP_LO {
1456                        0x3: IntOp::bitrev({{ Rd.uw = bitrev( Rt.uw<15:0> ); }});
1457                        format DspIntOp {
1458                            0x4: preceu_ph_qbl({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1459                                                                    SIMD_FMT_PH, UNSIGNED, MODE_L ); }});
1460                            0x5: preceu_ph_qbr({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1461                                                                    SIMD_FMT_PH, UNSIGNED, MODE_R ); }});
1462                            0x6: preceu_ph_qbla({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1463                                                                     SIMD_FMT_PH, UNSIGNED, MODE_LA ); }});
1464                            0x7: preceu_ph_qbra({{ Rd.uw = dspPrece( Rt.uw, SIMD_FMT_QB, UNSIGNED,
1465                                                                     SIMD_FMT_PH, UNSIGNED, MODE_RA ); }});
1466                        }
1467                    }
1468                }
1469
1470                //Table 5-8 MIPS32 SHLL.QB Encoding of the op Field (DSP ASE MANUAL)
1471                0x3: decode OP_HI {
1472                    0x0: decode OP_LO {
1473                        format DspIntOp {
1474                            0x0: shll_qb({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_QB,
1475                                                             NOSATURATE, UNSIGNED, &dspctl ); }});
1476                            0x1: shrl_qb({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_QB,
1477                                                             UNSIGNED ); }});
1478                            0x2: shllv_qb({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_QB,
1479                                                              NOSATURATE, UNSIGNED, &dspctl ); }});
1480                            0x3: shrlv_qb({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_QB,
1481                                                              UNSIGNED ); }});
1482                            0x4: shra_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB,
1483                                                             NOROUND, SIGNED, &dspctl ); }});
1484                            0x5: shra_r_qb({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_QB,
1485                                                               ROUND, SIGNED, &dspctl ); }});
1486                            0x6: shrav_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB,
1487                                                              NOROUND, SIGNED, &dspctl ); }});
1488                            0x7: shrav_r_qb({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_QB,
1489                                                                ROUND, SIGNED, &dspctl ); }});
1490                        }
1491                    }
1492                    0x1: decode OP_LO {
1493                        format DspIntOp {
1494                            0x0: shll_ph({{ Rd.uw = dspShll( Rt.uw, RS, SIMD_FMT_PH,
1495                                                             NOSATURATE, SIGNED, &dspctl ); }});
1496                            0x1: shra_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH,
1497                                                             NOROUND, SIGNED, &dspctl ); }});
1498                            0x2: shllv_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH,
1499                                                              NOSATURATE, SIGNED, &dspctl ); }});
1500                            0x3: shrav_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH,
1501                                                              NOROUND, SIGNED, &dspctl ); }});
1502                            0x4: shll_s_ph({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_PH,
1503                                                               SATURATE, SIGNED, &dspctl ); }});
1504                            0x5: shra_r_ph({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_PH,
1505                                                               ROUND, SIGNED, &dspctl ); }});
1506                            0x6: shllv_s_ph({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_PH,
1507                                                                SATURATE, SIGNED, &dspctl ); }});
1508                            0x7: shrav_r_ph({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_PH,
1509                                                                ROUND, SIGNED, &dspctl ); }});
1510                        }
1511                    }
1512                    0x2: decode OP_LO {
1513                        format DspIntOp {
1514                            0x4: shll_s_w({{ Rd.sw = dspShll( Rt.sw, RS, SIMD_FMT_W,
1515                                                              SATURATE, SIGNED, &dspctl ); }});
1516                            0x5: shra_r_w({{ Rd.sw = dspShra( Rt.sw, RS, SIMD_FMT_W,
1517                                                              ROUND, SIGNED, &dspctl ); }});
1518                            0x6: shllv_s_w({{ Rd.sw = dspShll( Rt.sw, Rs.sw, SIMD_FMT_W,
1519                                                               SATURATE, SIGNED, &dspctl ); }});
1520                            0x7: shrav_r_w({{ Rd.sw = dspShra( Rt.sw, Rs.sw, SIMD_FMT_W,
1521                                                               ROUND, SIGNED, &dspctl ); }});
1522                        }
1523                    }
1524                    0x3: decode OP_LO {
1525                        format DspIntOp {
1526                            0x1: shrl_ph({{ Rd.sw = dspShrl( Rt.sw, RS, SIMD_FMT_PH,
1527                                                             UNSIGNED ); }});
1528                            0x3: shrlv_ph({{ Rd.sw = dspShrl( Rt.sw, Rs.sw, SIMD_FMT_PH,
1529                                                              UNSIGNED ); }});
1530                        }
1531                    }
1532                }
1533            }
1534
1535            0x3: decode FUNCTION_LO {
1536
1537                //Table 3.12 MIPS32 ADDUH.QB Encoding of the op Field (DSP ASE Rev2 Manual)
1538                0x0: decode OP_HI {
1539                    0x0: decode OP_LO {
1540                        format DspIntOp {
1541                            0x0: adduh_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1542                                                              NOROUND, UNSIGNED ); }});
1543                            0x1: subuh_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1544                                                              NOROUND, UNSIGNED ); }});
1545                            0x2: adduh_r_qb({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1546                                                                ROUND, UNSIGNED ); }});
1547                            0x3: subuh_r_qb({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_QB,
1548                                                                ROUND, UNSIGNED ); }});
1549                        }
1550                    }
1551                    0x1: decode OP_LO {
1552                        format DspIntOp {
1553                            0x0: addqh_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1554                                                              NOROUND, SIGNED ); }});
1555                            0x1: subqh_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1556                                                              NOROUND, SIGNED ); }});
1557                            0x2: addqh_r_ph({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1558                                                                ROUND, SIGNED ); }});
1559                            0x3: subqh_r_ph({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_PH,
1560                                                                ROUND, SIGNED ); }});
1561                            0x4: mul_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1562                                                           NOSATURATE, &dspctl ); }});
1563                            0x6: mul_s_ph({{ Rd.sw = dspMul( Rs.sw, Rt.sw, SIMD_FMT_PH,
1564                                                             SATURATE, &dspctl ); }});
1565                        }
1566                    }
1567                    0x2: decode OP_LO {
1568                        format DspIntOp {
1569                            0x0: addqh_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1570                                                             NOROUND, SIGNED ); }});
1571                            0x1: subqh_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1572                                                             NOROUND, SIGNED ); }});
1573                            0x2: addqh_r_w({{ Rd.uw = dspAddh( Rs.sw, Rt.sw, SIMD_FMT_W,
1574                                                               ROUND, SIGNED ); }});
1575                            0x3: subqh_r_w({{ Rd.uw = dspSubh( Rs.sw, Rt.sw, SIMD_FMT_W,
1576                                                               ROUND, SIGNED ); }});
1577                            0x6: mulq_s_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1578                                                              SATURATE, NOROUND, &dspctl ); }});
1579                            0x7: mulq_rs_w({{ Rd.sw = dspMulq( Rs.sw, Rt.sw, SIMD_FMT_W,
1580                                                               SATURATE, ROUND, &dspctl ); }});
1581                        }
1582                    }
1583                }
1584            }
1585
1586            //Table A-10 MIPS32 BSHFL Encoding of sa Field
1587            0x4: decode SA {
1588                format BasicOp {
1589                    0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 |
1590                                      Rt.uw<31:24> << 16 |
1591                                      Rt.uw<7:0>   << 8  |
1592                                      Rt.uw<15:8>;
1593                    }});
1594                    0x10: seb({{ Rd.sw = Rt.sb; }});
1595                    0x18: seh({{ Rd.sw = Rt.sh; }});
1596                }
1597            }
1598
1599            0x6: decode FUNCTION_LO {
1600
1601                //Table 5-10 MIPS32 DPAQ.W.PH Encoding of the op Field (DSP ASE MANUAL)
1602                0x0: decode OP_HI {
1603                    0x0: decode OP_LO {
1604                        format DspHiLoOp {
1605                            0x0: dpa_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1606                                                             SIMD_FMT_PH, SIGNED, MODE_L ); }});
1607                            0x1: dps_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1608                                                             SIMD_FMT_PH, SIGNED, MODE_L ); }});
1609                            0x2: mulsa_w_ph({{ dspac = dspMulsa( dspac, Rs.sw, Rt.sw,
1610                                                                 ACDST, SIMD_FMT_PH ); }});
1611                            0x3: dpau_h_qbl({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1612                                                               SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1613                            0x4: dpaq_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1614                                                                 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1615                            0x5: dpsq_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1616                                                                 SIMD_FMT_W, NOSATURATE, MODE_L, &dspctl ); }});
1617                            0x6: mulsaq_s_w_ph({{ dspac = dspMulsaq( dspac, Rs.sw, Rt.sw,
1618                                                                     ACDST, SIMD_FMT_PH, &dspctl ); }});
1619                            0x7: dpau_h_qbr({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1620                                                               SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1621                        }
1622                    }
1623                    0x1: decode OP_LO {
1624                        format DspHiLoOp {
1625                            0x0: dpax_w_ph({{ dspac = dspDpa( dspac, Rs.sw, Rt.sw, ACDST,
1626                                                              SIMD_FMT_PH, SIGNED, MODE_X ); }});
1627                            0x1: dpsx_w_ph({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1628                                                              SIMD_FMT_PH, SIGNED, MODE_X ); }});
1629                            0x3: dpsu_h_qbl({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1630                                                               SIMD_FMT_QB, UNSIGNED, MODE_L ); }});
1631                            0x4: dpaq_sa_l_w({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1632                                                                 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1633                            0x5: dpsq_sa_l_w({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_W,
1634                                                                 SIMD_FMT_L, SATURATE, MODE_L, &dspctl ); }});
1635                            0x7: dpsu_h_qbr({{ dspac = dspDps( dspac, Rs.sw, Rt.sw, ACDST,
1636                                                               SIMD_FMT_QB, UNSIGNED, MODE_R ); }});
1637                        }
1638                    }
1639                    0x2: decode OP_LO {
1640                        format DspHiLoOp {
1641                            0x0: maq_sa_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1642                                                                 MODE_L, SATURATE, &dspctl ); }});
1643                            0x2: maq_sa_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1644                                                                 MODE_R, SATURATE, &dspctl ); }});
1645                            0x4: maq_s_w_phl({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1646                                                                 MODE_L, NOSATURATE, &dspctl ); }});
1647                            0x6: maq_s_w_phr({{ dspac = dspMaq( dspac, Rs.uw, Rt.uw, ACDST, SIMD_FMT_PH,
1648                                                                 MODE_R, NOSATURATE, &dspctl ); }});
1649                        }
1650                    }
1651                    0x3: decode OP_LO {
1652                        format DspHiLoOp {
1653                            0x0: dpaqx_s_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1654                                                                  SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1655                            0x1: dpsqx_s_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1656                                                                  SIMD_FMT_W, NOSATURATE, MODE_X, &dspctl ); }});
1657                            0x2: dpaqx_sa_w_ph({{ dspac = dspDpaq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1658                                                                   SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1659                            0x3: dpsqx_sa_w_ph({{ dspac = dspDpsq( dspac, Rs.sw, Rt.sw, ACDST, SIMD_FMT_PH,
1660                                                                   SIMD_FMT_W, SATURATE, MODE_X, &dspctl ); }});
1661                        }
1662                    }
1663                }
1664
1665                //Table 3.3 MIPS32 APPEND Encoding of the op Field
1666                0x1: decode OP_HI {
1667                    0x0: decode OP_LO {
1668                        format IntOp {
1669                            0x0: append({{ Rt.uw = (Rt.uw << RD) | bits(Rs.uw,RD-1,0); }});
1670                            0x1: prepend({{ Rt.uw = (Rt.uw >> RD) | (bits(Rs.uw,RD-1,0) << 32-RD); }});
1671                        }
1672                    }
1673                    0x2: decode OP_LO {
1674                        format IntOp {
1675                            0x0: balign({{ Rt.uw = (Rt.uw << (8*BP)) | (Rs.uw >> (8*(4-BP))); }});
1676                        }
1677                    }
1678                }
1679
1680                0x7: FailUnimpl::rdhwr();
1681            }
1682
1683            0x7: decode FUNCTION_LO {
1684
1685                //Table 5-11 MIPS32 EXTR.W Encoding of the op Field (DSP ASE MANUAL)
1686                0x0: decode OP_HI {
1687                    0x0: decode OP_LO {
1688                        format DspHiLoOp {
1689                            0x0: extr_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1690                                                            NOROUND, NOSATURATE, &dspctl ); }});
1691                            0x1: extrv_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1692                                                             NOROUND, NOSATURATE, &dspctl ); }});
1693                            0x2: extp({{ Rt.uw = dspExtp( dspac, RS, &dspctl ); }});
1694                            0x3: extpv({{ Rt.uw = dspExtp( dspac, Rs.uw, &dspctl ); }});
1695                            0x4: extr_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1696                                                              ROUND, NOSATURATE, &dspctl ); }});
1697                            0x5: extrv_r_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1698                                                               ROUND, NOSATURATE, &dspctl ); }});
1699                            0x6: extr_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, RS,
1700                                                               ROUND, SATURATE, &dspctl ); }});
1701                            0x7: extrv_rs_w({{ Rt.uw = dspExtr( dspac, SIMD_FMT_W, Rs.uw,
1702                                                                ROUND, SATURATE, &dspctl ); }});
1703                        }
1704                    }
1705                    0x1: decode OP_LO {
1706                        format DspHiLoOp {
1707                            0x2: extpdp({{ Rt.uw = dspExtpd( dspac, RS, &dspctl ); }});
1708                            0x3: extpdpv({{ Rt.uw = dspExtpd( dspac, Rs.uw, &dspctl ); }});
1709                            0x6: extr_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, RS,
1710                                                              NOROUND, SATURATE, &dspctl ); }});
1711                            0x7: extrv_s_h({{ Rt.uw = dspExtr( dspac, SIMD_FMT_PH, Rs.uw,
1712                                                               NOROUND, SATURATE, &dspctl ); }});
1713                        }
1714                    }
1715                    0x2: decode OP_LO {
1716                        format DspIntOp {
1717                            0x2: rddsp({{ Rd.uw = readDSPControl( &dspctl, RDDSPMASK ); }});
1718                            0x3: wrdsp({{ writeDSPControl( &dspctl, Rs.uw, WRDSPMASK ); }});
1719                        }
1720                    }
1721                    0x3: decode OP_LO {
1722                        format DspHiLoOp {
1723                            0x2: shilo({{ if( sext<6>(HILOSA) < 0 )
1724                                              dspac = (uint64_t)dspac << -sext<6>(HILOSA);
1725                                          else
1726                                              dspac = (uint64_t)dspac >> sext<6>(HILOSA); }});
1727                            0x3: shilov({{ if( sext<6>(Rs.sw<5:0>) < 0 )
1728                                              dspac = (uint64_t)dspac << -sext<6>(Rs.sw<5:0>);
1729                                           else
1730                                              dspac = (uint64_t)dspac >> sext<6>(Rs.sw<5:0>); }});
1731                            0x7: mthlip({{ dspac = dspac << 32;
1732                                           dspac |= Rs.uw;
1733                                           dspctl = insertBits( dspctl, 5, 0,
1734                                                                dspctl<5:0>+32 ); }});
1735                        }
1736                    }
1737                }
1738            }
1739        }
1740    }
1741
1742    0x4: decode OPCODE_LO {
1743        format LoadMemory {
1744            0x0: lb({{ Rt.sw = Mem.sb; }});
1745            0x1: lh({{ Rt.sw = Mem.sh; }});
1746            0x3: lw({{ Rt.sw = Mem.sw; }});
1747            0x4: lbu({{ Rt.uw = Mem.ub; }});
1748            0x5: lhu({{ Rt.uw = Mem.uh; }});
1749        }
1750
1751        format LoadUnalignedMemory {
1752            0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset);
1753                        Rt.uw = mem_word << mem_shift |
1754                            Rt.uw & mask(mem_shift);
1755                     }});
1756            0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset;
1757                        Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) |
1758                            mem_word >> mem_shift;
1759                     }});
1760      }
1761    }
1762
1763    0x5: decode OPCODE_LO {
1764        format StoreMemory {
1765            0x0: sb({{ Mem.ub = Rt<7:0>; }});
1766            0x1: sh({{ Mem.uh = Rt<15:0>; }});
1767            0x3: sw({{ Mem.uw = Rt<31:0>; }});
1768        }
1769
1770        format StoreUnalignedMemory {
1771            0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset);
1772                        uint32_t mem_shift = 32 - reg_shift;
1773                        mem_word = mem_word & (mask(reg_shift) << mem_shift) |
1774                                   Rt.uw >> reg_shift;
1775                     }});
1776            0x6: swr({{ uint32_t reg_shift = 8 * byte_offset;
1777                        mem_word = Rt.uw << reg_shift |
1778                                   mem_word & (mask(reg_shift));
1779                     }});
1780        }
1781
1782        0x7: FailUnimpl::cache();
1783    }
1784
1785    0x6: decode OPCODE_LO {
1786        format LoadMemory {
1787            0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
1788            0x1: lwc1({{ Ft.uw = Mem.uw; }});
1789            0x5: ldc1({{ Ft.ud = Mem.ud; }});
1790        }
1791
1792        0x3: Prefetch::pref();
1793    }
1794
1795
1796    0x7: decode OPCODE_LO {
1797        0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
1798                           {{ uint64_t tmp = write_result;
1799                              Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
1800                           }}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
1801
1802        format StoreMemory {
1803            0x1: swc1({{ Mem.uw = Ft.uw; }});
1804            0x5: sdc1({{ Mem.ud = Ft.ud; }});
1805        }
1806    }
1807}
1808
1809
1810