decoder.isa revision 2965:82703e01285a
1// -*- mode:c++ -*- 2 3// Copyright (c) 2006 The Regents of The University of Michigan 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright 11// notice, this list of conditions and the following disclaimer in the 12// documentation and/or other materials provided with the distribution; 13// neither the name of the copyright holders nor the names of its 14// contributors may be used to endorse or promote products derived from 15// this software without specific prior written permission. 16// 17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28// 29// Authors: Korey Sewell 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual MIPS32 ISA decoder 34// ----------------------------- 35// The following instructions are specified in the MIPS32 ISA 36// Specification. Decoding closely follows the style specified 37// in the MIPS32 ISA specification document starting with Table 38// A-2 (document available @ www.mips.com) 39// 40decode OPCODE_HI default Unknown::unknown() { 41 //Table A-2 42 0x0: decode OPCODE_LO { 43 0x0: decode FUNCTION_HI { 44 0x0: decode FUNCTION_LO { 45 0x1: decode MOVCI { 46 format BasicOp { 47 0: movf({{ Rd = (getCondCode(FCSR, CC) == 0) ? Rd : Rs; }}); 48 1: movt({{ Rd = (getCondCode(FCSR, CC) == 1) ? Rd : Rs; }}); 49 } 50 } 51 52 format BasicOp { 53 //Table A-3 Note: "Specific encodings of the rd, rs, and 54 //rt fields are used to distinguish SLL, SSNOP, and EHB 55 //functions 56 0x0: decode RS { 57 0x0: decode RT_RD { 58 0x0: decode SA default Nop::nop(){ 59 0x1: WarnUnimpl::ssnop(); 60 0x3: WarnUnimpl::ehb(); 61 } 62 default: sll({{ Rd = Rt.uw << SA; }}); 63 } 64 } 65 66 0x2: decode RS_SRL { 67 0x0:decode SRL { 68 0: srl({{ Rd = Rt.uw >> SA; }}); 69 70 //Hardcoded assuming 32-bit ISA, probably need parameter here 71 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 72 } 73 } 74 75 0x3: decode RS { 76 0x0: sra({{ 77 uint32_t temp = Rt >> SA; 78 if ( (Rt & 0x80000000) > 0 ) { 79 uint32_t mask = 0x80000000; 80 for(int i=0; i < SA; i++) { 81 temp |= mask; 82 mask = mask >> 1; 83 } 84 } 85 Rd = temp; 86 }}); 87 } 88 89 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 90 91 0x6: decode SRLV { 92 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 93 94 //Hardcoded assuming 32-bit ISA, probably need parameter here 95 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 96 } 97 98 0x7: srav({{ 99 int shift_amt = Rs<4:0>; 100 101 uint32_t temp = Rt >> shift_amt; 102 103 if ( (Rt & 0x80000000) > 0 ) { 104 uint32_t mask = 0x80000000; 105 for(int i=0; i < shift_amt; i++) { 106 temp |= mask; 107 mask = mask >> 1; 108 } 109 } 110 111 Rd = temp; 112 }}); 113 } 114 } 115 116 0x1: decode FUNCTION_LO { 117 //Table A-3 Note: "Specific encodings of the hint field are 118 //used to distinguish JR from JR.HB and JALR from JALR.HB" 119 format Jump { 120 0x0: decode HINT { 121 0x1: jr_hb({{ NNPC = Rs & ~1; }}, IsReturn, ClearHazards); 122 default: jr({{ NNPC = Rs & ~1; }}, IsReturn); 123 } 124 125 0x1: decode HINT { 126 0x1: jalr_hb({{ Rd = NNPC; NNPC = Rs; }}, IsCall, Link 127 , ClearHazards); 128 default: jalr({{ Rd = NNPC; NNPC = Rs; }}, IsCall, 129 Link); 130 } 131 } 132 133 format BasicOp { 134 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 135 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 136 0x4: syscall({{ xc->syscall(R2); }}, 137 IsSerializeAfter, IsNonSpeculative); 138 0x7: sync({{ ; }}, IsMemBarrier); 139 } 140 141 format FailUnimpl { 142 0x5: break(); 143 } 144 } 145 146 0x2: decode FUNCTION_LO { 147 format HiLoMiscOp { 148 0x0: mfhi({{ Rd = HI; }}); 149 0x1: mthi({{ HI = Rs; }}); 150 0x2: mflo({{ Rd = LO; }}); 151 0x3: mtlo({{ LO = Rs; }}); 152 } 153 } 154 155 0x3: decode FUNCTION_LO { 156 format HiLoOp { 157 0x0: mult({{ val = Rs.sd * Rt.sd; }}); 158 0x1: multu({{ val = Rs.ud * Rt.ud; }}); 159 } 160 161 format HiLoMiscOp { 162 0x2: div({{ if (Rt.sd != 0) { 163 HI = Rs.sd % Rt.sd; 164 LO = Rs.sd / Rt.sd; 165 } 166 }}); 167 0x3: divu({{ if (Rt.ud != 0) { 168 HI = Rs.ud % Rt.ud; 169 LO = Rs.ud / Rt.ud; 170 } 171 }}); 172 } 173 } 174 175 0x4: decode HINT { 176 0x0: decode FUNCTION_LO { 177 format IntOp { 178 0x0: add({{ Rd.sw = Rs.sw + Rt.sw; /*Trap on Overflow*/}}); 179 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 180 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 181 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 182 0x4: and({{ Rd = Rs & Rt;}}); 183 0x5: or({{ Rd = Rs | Rt;}}); 184 0x6: xor({{ Rd = Rs ^ Rt;}}); 185 0x7: nor({{ Rd = ~(Rs | Rt);}}); 186 } 187 } 188 } 189 190 0x5: decode HINT { 191 0x0: decode FUNCTION_LO { 192 format IntOp{ 193 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 194 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 195 } 196 } 197 } 198 199 0x6: decode FUNCTION_LO { 200 format Trap { 201 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 202 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 203 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 204 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 205 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 206 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 207 } 208 } 209 } 210 211 0x1: decode REGIMM_HI { 212 0x0: decode REGIMM_LO { 213 format Branch { 214 0x0: bltz({{ cond = (Rs.sw < 0); }}); 215 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 216 0x2: bltzl({{ cond = (Rs.sw < 0); }}, Likely); 217 0x3: bgezl({{ cond = (Rs.sw >= 0); }}, Likely); 218 } 219 } 220 221 0x1: decode REGIMM_LO { 222 format Trap { 223 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 224 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 225 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 226 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 227 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 228 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 229 } 230 } 231 232 0x2: decode REGIMM_LO { 233 format Branch { 234 0x0: bltzal({{ cond = (Rs.sw < 0); }}, Link); 235 0x1: decode RS { 236 0x0: bal ({{ cond = 1; }}, IsCall, Link); 237 default: bgezal({{ cond = (Rs.sw >= 0); }}, Link); 238 } 239 0x2: bltzall({{ cond = (Rs.sw < 0); }}, Link, Likely); 240 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, Link, Likely); 241 } 242 } 243 244 0x3: decode REGIMM_LO { 245 format WarnUnimpl { 246 0x7: synci(); 247 } 248 } 249 } 250 251 format Jump { 252 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 253 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }}, IsCall, 254 Link); 255 } 256 257 format Branch { 258 0x4: decode RS_RT { 259 0x0: b({{ cond = 1; }}); 260 default: beq({{ cond = (Rs.sw == Rt.sw); }}); 261 } 262 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 263 0x6: blez({{ cond = (Rs.sw <= 0); }}); 264 0x7: bgtz({{ cond = (Rs.sw > 0); }}); 265 } 266 } 267 268 0x1: decode OPCODE_LO { 269 format IntImmOp { 270 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 271 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 272 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 273 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 274 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 275 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 276 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 277 278 0x7: decode RS { 279 0x0: lui({{ Rt = imm << 16}}); 280 } 281 } 282 } 283 284 0x2: decode OPCODE_LO { 285 //Table A-11 MIPS32 COP0 Encoding of rs Field 286 0x0: decode RS_MSB { 287 0x0: decode RS { 288 format CP0Control { 289 0x0: mfc0({{ Rt = xc->readMiscReg(RD << 5 | SEL); }}); 290 0x4: mtc0({{ xc->setMiscReg(RD << 5 | SEL, Rt); }}); 291 } 292 293 format MipsMT { 294 0x8: mftr(); 295 0xC: mttr(); 296 0xB: decode RD { 297 0x0: decode SC { 298 0x0: dvpe(); 299 0x1: evpe(); 300 } 301 0x1: decode SC { 302 0x0: dmt(); 303 0x1: emt(); 304 0xC: decode SC { 305 0x0: di(); 306 0x1: ei(); 307 } 308 } 309 } 310 } 311 312 format FailUnimpl { 313 0xA: rdpgpr(); 314 0xE: wrpgpr(); 315 } 316 } 317 318 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 319 0x1: decode FUNCTION { 320 format FailUnimpl { 321 0x01: tlbr(); 322 0x02: tlbwi(); 323 0x06: tlbwr(); 324 0x08: tlbp(); 325 326 0x18: eret(); 327 0x1F: deret(); 328 0x20: wait(); 329 } 330 } 331 } 332 333 //Table A-13 MIPS32 COP1 Encoding of rs Field 334 0x1: decode RS_MSB { 335 336 0x0: decode RS_HI { 337 0x0: decode RS_LO { 338 format CP1Control { 339 0x0: mfc1 ({{ Rt.uw = Fs.uw; }}); 340 341 0x2: cfc1({{ 342 switch (FS) 343 { 344 case 0: 345 Rt = FIR; 346 break; 347 case 25: 348 Rt = 0 | (FCSR & 0xFE000000) >> 24 | (FCSR & 0x00800000) >> 23; 349 break; 350 case 26: 351 Rt = 0 | (FCSR & 0x0003F07C); 352 break; 353 case 28: 354 Rt = 0 | (FCSR & 0x00000F80) | (FCSR & 0x01000000) >> 21 | (FCSR & 0x00000003); 355 break; 356 case 31: 357 Rt = FCSR; 358 break; 359 default: 360 panic("FP Control Value (%d) Not Valid"); 361 } 362 }}); 363 364 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 365 366 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 367 368 0x6: ctc1({{ 369 switch (FS) 370 { 371 case 25: 372 FCSR = 0 | (Rt.uw<7:1> << 25) // move 31...25 373 | (FCSR & 0x01000000) // bit 24 374 | (FCSR & 0x004FFFFF);// bit 22...0 375 break; 376 377 case 26: 378 FCSR = 0 | (FCSR & 0xFFFC0000) // move 31...18 379 | Rt.uw<17:12> << 12 // bit 17...12 380 | (FCSR & 0x00000F80) << 7// bit 11...7 381 | Rt.uw<6:2> << 2 // bit 6...2 382 | (FCSR & 0x00000002); // bit 1...0 383 break; 384 385 case 28: 386 FCSR = 0 | (FCSR & 0xFE000000) // move 31...25 387 | Rt.uw<2:2> << 24 // bit 24 388 | (FCSR & 0x00FFF000) << 23// bit 23...12 389 | Rt.uw<11:7> << 7 // bit 24 390 | (FCSR & 0x000007E) 391 | Rt.uw<1:0>;// bit 22...0 392 break; 393 394 case 31: 395 FCSR = Rt.uw; 396 break; 397 398 default: 399 panic("FP Control Value (%d) Not Available. Ignoring Access to" 400 "Floating Control Status Register", FS); 401 } 402 }}); 403 404 0x7: mthc1({{ 405 uint64_t fs_hi = Rt.uw; 406 uint64_t fs_lo = Fs.ud & 0x0FFFFFFFF; 407 Fs.ud = (fs_hi << 32) | fs_lo; 408 }}); 409 410 } 411 } 412 413 0x1: decode ND { 414 format Branch { 415 0x0: decode TF { 416 0x0: bc1f({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 417 }}); 418 0x1: bc1t({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 419 }}); 420 } 421 0x1: decode TF { 422 0x0: bc1fl({{ cond = getCondCode(FCSR, BRANCH_CC) == 0; 423 }}, Likely); 424 0x1: bc1tl({{ cond = getCondCode(FCSR, BRANCH_CC) == 1; 425 }}, Likely); 426 } 427 } 428 } 429 } 430 431 0x1: decode RS_HI { 432 0x2: decode RS_LO { 433 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 434 //(( single-precision floating point)) 435 0x0: decode FUNCTION_HI { 436 0x0: decode FUNCTION_LO { 437 format FloatOp { 438 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 439 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 440 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 441 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 442 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 443 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 444 0x7: neg_s({{ Fd.sf = -Fs.sf;}}); 445 } 446 447 0x6: BasicOp::mov_s({{ Fd.sf = Fs.sf;}}); 448 } 449 450 0x1: decode FUNCTION_LO { 451 format FloatConvertOp { 452 0x0: round_l_s({{ val = Fs.sf; }}, ToLong, 453 Round); 454 0x1: trunc_l_s({{ val = Fs.sf; }}, ToLong, 455 Trunc); 456 0x2: ceil_l_s({{ val = Fs.sf; }}, ToLong, 457 Ceil); 458 0x3: floor_l_s({{ val = Fs.sf; }}, ToLong, 459 Floor); 460 0x4: round_w_s({{ val = Fs.sf; }}, ToWord, 461 Round); 462 0x5: trunc_w_s({{ val = Fs.sf; }}, ToWord, 463 Trunc); 464 0x6: ceil_w_s({{ val = Fs.sf; }}, ToWord, 465 Ceil); 466 0x7: floor_w_s({{ val = Fs.sf; }}, ToWord, 467 Floor); 468 } 469 } 470 471 0x2: decode FUNCTION_LO { 472 0x1: decode MOVCF { 473 format BasicOp { 474 0x0: movf_s({{ Fd = (getCondCode(FCSR,CC) == 0) ? Fs : Fd; }}); 475 0x1: movt_s({{ Fd = (getCondCode(FCSR,CC) == 1) ? Fs : Fd; }}); 476 } 477 } 478 479 format BasicOp { 480 0x2: movz_s({{ Fd = (Rt == 0) ? Fs : Fd; }}); 481 0x3: movn_s({{ Fd = (Rt != 0) ? Fs : Fd; }}); 482 } 483 484 format FloatOp { 485 0x5: recip_s({{ Fd = 1 / Fs; }}); 486 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); 487 } 488 } 489 490 0x4: decode FUNCTION_LO { 491 format FloatConvertOp { 492 0x1: cvt_d_s({{ val = Fs.sf; }}, ToDouble); 493 0x4: cvt_w_s({{ val = Fs.sf; }}, ToWord); 494 0x5: cvt_l_s({{ val = Fs.sf; }}, ToLong); 495 } 496 497 0x6: FloatOp::cvt_ps_s({{ 498 Fd.ud = (uint64_t) Fs.uw << 32 | 499 (uint64_t) Ft.uw; 500 }}); 501 } 502 503 0x6: decode FUNCTION_LO { 504 format FloatCompareOp { 505 0x0: c_f_s({{ cond = 0; }}, SinglePrecision, 506 UnorderedFalse); 507 0x1: c_un_s({{ cond = 0; }}, SinglePrecision, 508 UnorderedTrue); 509 0x2: c_eq_s({{ cond = (Fs.sf == Ft.sf); }}, 510 UnorderedFalse); 511 0x3: c_ueq_s({{ cond = (Fs.sf == Ft.sf); }}, 512 UnorderedTrue); 513 0x4: c_olt_s({{ cond = (Fs.sf < Ft.sf); }}, 514 UnorderedFalse); 515 0x5: c_ult_s({{ cond = (Fs.sf < Ft.sf); }}, 516 UnorderedTrue); 517 0x6: c_ole_s({{ cond = (Fs.sf <= Ft.sf); }}, 518 UnorderedFalse); 519 0x7: c_ule_s({{ cond = (Fs.sf <= Ft.sf); }}, 520 UnorderedTrue); 521 } 522 } 523 524 0x7: decode FUNCTION_LO { 525 format FloatCompareOp { 526 0x0: c_sf_s({{ cond = 0; }}, SinglePrecision, 527 UnorderedFalse, QnanException); 528 0x1: c_ngle_s({{ cond = 0; }}, SinglePrecision, 529 UnorderedTrue, QnanException); 530 0x2: c_seq_s({{ cond = (Fs.sf == Ft.sf);}}, 531 UnorderedFalse, QnanException); 532 0x3: c_ngl_s({{ cond = (Fs.sf == Ft.sf); }}, 533 UnorderedTrue, QnanException); 534 0x4: c_lt_s({{ cond = (Fs.sf < Ft.sf); }}, 535 UnorderedFalse, QnanException); 536 0x5: c_nge_s({{ cond = (Fs.sf < Ft.sf); }}, 537 UnorderedTrue, QnanException); 538 0x6: c_le_s({{ cond = (Fs.sf <= Ft.sf); }}, 539 UnorderedFalse, QnanException); 540 0x7: c_ngt_s({{ cond = (Fs.sf <= Ft.sf); }}, 541 UnorderedTrue, QnanException); 542 } 543 } 544 } 545 546 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 547 0x1: decode FUNCTION_HI { 548 0x0: decode FUNCTION_LO { 549 format FloatOp { 550 0x0: add_d({{ Fd.df = Fs.df + Ft.df; }}); 551 0x1: sub_d({{ Fd.df = Fs.df - Ft.df; }}); 552 0x2: mul_d({{ Fd.df = Fs.df * Ft.df; }}); 553 0x3: div_d({{ Fd.df = Fs.df / Ft.df; }}); 554 0x4: sqrt_d({{ Fd.df = sqrt(Fs.df); }}); 555 0x5: abs_d({{ Fd.df = fabs(Fs.df); }}); 556 0x7: neg_d({{ Fd.df = -1 * Fs.df; }}); 557 } 558 559 0x6: BasicOp::mov_d({{ Fd.df = Fs.df; }}); 560 } 561 562 0x1: decode FUNCTION_LO { 563 format FloatConvertOp { 564 0x0: round_l_d({{ val = Fs.df; }}, ToLong, 565 Round); 566 0x1: trunc_l_d({{ val = Fs.df; }}, ToLong, 567 Trunc); 568 0x2: ceil_l_d({{ val = Fs.df; }}, ToLong, 569 Ceil); 570 0x3: floor_l_d({{ val = Fs.df; }}, ToLong, 571 Floor); 572 0x4: round_w_d({{ val = Fs.df; }}, ToWord, 573 Round); 574 0x5: trunc_w_d({{ val = Fs.df; }}, ToWord, 575 Trunc); 576 0x6: ceil_w_d({{ val = Fs.df; }}, ToWord, 577 Ceil); 578 0x7: floor_w_d({{ val = Fs.df; }}, ToWord, 579 Floor); 580 } 581 } 582 583 0x2: decode FUNCTION_LO { 584 0x1: decode MOVCF { 585 format BasicOp { 586 0x0: movf_d({{ Fd.df = (getCondCode(FCSR,CC) == 0) ? 587 Fs.df : Fd.df; 588 }}); 589 0x1: movt_d({{ Fd.df = (getCondCode(FCSR,CC) == 1) ? 590 Fs.df : Fd.df; 591 }}); 592 } 593 } 594 595 format BasicOp { 596 0x2: movz_d({{ Fd.df = (Rt == 0) ? Fs.df : Fd.df; }}); 597 0x3: movn_d({{ Fd.df = (Rt != 0) ? Fs.df : Fd.df; }}); 598 } 599 600 format FloatOp { 601 0x5: recip_d({{ Fd.df = 1 / Fs.df }}); 602 0x6: rsqrt_d({{ Fd.df = 1 / sqrt(Fs.df) }}); 603 } 604 } 605 606 0x4: decode FUNCTION_LO { 607 format FloatConvertOp { 608 0x0: cvt_s_d({{ val = Fs.df; }}, ToSingle); 609 0x4: cvt_w_d({{ val = Fs.df; }}, ToWord); 610 0x5: cvt_l_d({{ val = Fs.df; }}, ToLong); 611 } 612 } 613 614 0x6: decode FUNCTION_LO { 615 format FloatCompareOp { 616 0x0: c_f_d({{ cond = 0; }}, DoublePrecision, 617 UnorderedFalse); 618 0x1: c_un_d({{ cond = 0; }}, DoublePrecision, 619 UnorderedTrue); 620 0x2: c_eq_d({{ cond = (Fs.df == Ft.df); }}, 621 UnorderedFalse); 622 0x3: c_ueq_d({{ cond = (Fs.df == Ft.df); }}, 623 UnorderedTrue); 624 0x4: c_olt_d({{ cond = (Fs.df < Ft.df); }}, 625 UnorderedFalse); 626 0x5: c_ult_d({{ cond = (Fs.df < Ft.df); }}, 627 UnorderedTrue); 628 0x6: c_ole_d({{ cond = (Fs.df <= Ft.df); }}, 629 UnorderedFalse); 630 0x7: c_ule_d({{ cond = (Fs.df <= Ft.df); }}, 631 UnorderedTrue); 632 } 633 } 634 635 0x7: decode FUNCTION_LO { 636 format FloatCompareOp { 637 0x0: c_sf_d({{ cond = 0; }}, DoublePrecision, 638 UnorderedFalse, QnanException); 639 0x1: c_ngle_d({{ cond = 0; }}, DoublePrecision, 640 UnorderedTrue, QnanException); 641 0x2: c_seq_d({{ cond = (Fs.df == Ft.df); }}, 642 UnorderedFalse, QnanException); 643 0x3: c_ngl_d({{ cond = (Fs.df == Ft.df); }}, 644 UnorderedTrue, QnanException); 645 0x4: c_lt_d({{ cond = (Fs.df < Ft.df); }}, 646 UnorderedFalse, QnanException); 647 0x5: c_nge_d({{ cond = (Fs.df < Ft.df); }}, 648 UnorderedTrue, QnanException); 649 0x6: c_le_d({{ cond = (Fs.df <= Ft.df); }}, 650 UnorderedFalse, QnanException); 651 0x7: c_ngt_d({{ cond = (Fs.df <= Ft.df); }}, 652 UnorderedTrue, QnanException); 653 } 654 } 655 } 656 657 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 658 0x4: decode FUNCTION { 659 format FloatConvertOp { 660 0x20: cvt_s_w({{ val = Fs.uw; }}, ToSingle); 661 0x21: cvt_d_w({{ val = Fs.uw; }}, ToDouble); 662 0x26: FailUnimpl::cvt_ps_w(); 663 } 664 } 665 666 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 667 //Note: "1. Format type L is legal only if 64-bit floating point operations 668 //are enabled." 669 0x5: decode FUNCTION_HI { 670 format FloatConvertOp { 671 0x20: cvt_s_l({{ val = Fs.ud; }}, ToSingle); 672 0x21: cvt_d_l({{ val = Fs.ud; }}, ToDouble); 673 0x26: FailUnimpl::cvt_ps_l(); 674 } 675 } 676 677 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 678 //Note: "1. Format type PS is legal only if 64-bit floating point operations 679 //are enabled. " 680 0x6: decode FUNCTION_HI { 681 0x0: decode FUNCTION_LO { 682 format Float64Op { 683 0x0: add_ps({{ 684 Fd1.sf = Fs1.sf + Ft2.sf; 685 Fd2.sf = Fs2.sf + Ft2.sf; 686 }}); 687 0x1: sub_ps({{ 688 Fd1.sf = Fs1.sf - Ft2.sf; 689 Fd2.sf = Fs2.sf - Ft2.sf; 690 }}); 691 0x2: mul_ps({{ 692 Fd1.sf = Fs1.sf * Ft2.sf; 693 Fd2.sf = Fs2.sf * Ft2.sf; 694 }}); 695 0x5: abs_ps({{ 696 Fd1.sf = fabs(Fs1.sf); 697 Fd2.sf = fabs(Fs2.sf); 698 }}); 699 0x6: mov_ps({{ 700 Fd1.sf = Fs1.sf; 701 Fd2.sf = Fs2.sf; 702 }}); 703 0x7: neg_ps({{ 704 Fd1.sf = -(Fs1.sf); 705 Fd2.sf = -(Fs2.sf); 706 }}); 707 } 708 } 709 710 0x2: decode FUNCTION_LO { 711 0x1: decode MOVCF { 712 format Float64Op { 713 0x0: movf_ps({{ 714 Fd1 = (getCondCode(FCSR, CC) == 0) ? 715 Fs1 : Fd1; 716 Fd2 = (getCondCode(FCSR, CC+1) == 0) ? 717 Fs2 : Fd2; 718 }}); 719 0x1: movt_ps({{ 720 Fd2 = (getCondCode(FCSR, CC) == 1) ? 721 Fs1 : Fd1; 722 Fd2 = (getCondCode(FCSR, CC+1) == 1) ? 723 Fs2 : Fd2; 724 }}); 725 } 726 } 727 728 format Float64Op { 729 0x2: movz_ps({{ 730 Fd1 = (getCondCode(FCSR, CC) == 0) ? 731 Fs1 : Fd1; 732 Fd2 = (getCondCode(FCSR, CC) == 0) ? 733 Fs2 : Fd2; 734 }}); 735 0x3: movn_ps({{ 736 Fd1 = (getCondCode(FCSR, CC) == 1) ? 737 Fs1 : Fd1; 738 Fd2 = (getCondCode(FCSR, CC) == 1) ? 739 Fs2 : Fd2; 740 }}); 741 } 742 743 } 744 745 0x4: decode FUNCTION_LO { 746 0x0: FloatOp::cvt_s_pu({{ Fd.sf = Fs2.sf; }}); 747 } 748 749 0x5: decode FUNCTION_LO { 750 0x0: FloatOp::cvt_s_pl({{ Fd.sf = Fs1.sf; }}); 751 752 format Float64Op { 753 0x4: pll({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 754 Ft1.uw; 755 }}); 756 0x5: plu({{ Fd.ud = (uint64_t) Fs1.uw << 32 | 757 Ft2.uw; 758 }}); 759 0x6: pul({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 760 Ft1.uw; 761 }}); 762 0x7: puu({{ Fd.ud = (uint64_t) Fs2.uw << 32 | 763 Ft2.uw; 764 }}); 765 } 766 } 767 768 0x6: decode FUNCTION_LO { 769 format FloatPSCompareOp { 770 0x0: c_f_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 771 UnorderedFalse); 772 0x1: c_un_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 773 UnorderedTrue); 774 0x2: c_eq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 775 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 776 UnorderedFalse); 777 0x3: c_ueq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 778 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 779 UnorderedTrue); 780 0x4: c_olt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 781 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 782 UnorderedFalse); 783 0x5: c_ult_ps({{ cond1 = (Fs.sf < Ft.sf); }}, 784 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 785 UnorderedTrue); 786 0x6: c_ole_ps({{ cond1 = (Fs.sf <= Ft.sf); }}, 787 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 788 UnorderedFalse); 789 0x7: c_ule_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 790 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 791 UnorderedTrue); 792 } 793 } 794 795 0x7: decode FUNCTION_LO { 796 format FloatPSCompareOp { 797 0x0: c_sf_ps({{ cond1 = 0; }}, {{ cond2 = 0; }}, 798 UnorderedFalse, QnanException); 799 0x1: c_ngle_ps({{ cond1 = 0; }}, 800 {{ cond2 = 0; }}, 801 UnorderedTrue, QnanException); 802 0x2: c_seq_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 803 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 804 UnorderedFalse, QnanException); 805 0x3: c_ngl_ps({{ cond1 = (Fs1.sf == Ft1.sf); }}, 806 {{ cond2 = (Fs2.sf == Ft2.sf); }}, 807 UnorderedTrue, QnanException); 808 0x4: c_lt_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 809 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 810 UnorderedFalse, QnanException); 811 0x5: c_nge_ps({{ cond1 = (Fs1.sf < Ft1.sf); }}, 812 {{ cond2 = (Fs2.sf < Ft2.sf); }}, 813 UnorderedTrue, QnanException); 814 0x6: c_le_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 815 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 816 UnorderedFalse, QnanException); 817 0x7: c_ngt_ps({{ cond1 = (Fs1.sf <= Ft1.sf); }}, 818 {{ cond2 = (Fs2.sf <= Ft2.sf); }}, 819 UnorderedTrue, QnanException); 820 } 821 } 822 } 823 } 824 } 825 } 826 827 //Table A-19 MIPS32 COP2 Encoding of rs Field 828 0x2: decode RS_MSB { 829 format FailUnimpl { 830 0x0: decode RS_HI { 831 0x0: decode RS_LO { 832 0x0: mfc2(); 833 0x2: cfc2(); 834 0x3: mfhc2(); 835 0x4: mtc2(); 836 0x6: ctc2(); 837 0x7: mftc2(); 838 } 839 840 0x1: decode ND { 841 0x0: decode TF { 842 0x0: bc2f(); 843 0x1: bc2t(); 844 } 845 846 0x1: decode TF { 847 0x0: bc2fl(); 848 0x1: bc2tl(); 849 } 850 } 851 } 852 } 853 } 854 855 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 856 //Note: "COP1X instructions are legal only if 64-bit floating point 857 //operations are enabled." 858 0x3: decode FUNCTION_HI { 859 0x0: decode FUNCTION_LO { 860 format LoadIndexedMemory { 861 0x0: lwxc1({{ Fd.uw = Mem.uw;}}); 862 0x1: ldxc1({{ Fd.ud = Mem.ud;}}); 863 0x5: luxc1({{ Fd.ud = Mem.ud;}}, 864 {{ EA = (Rs + Rt) & ~7; }}); 865 } 866 } 867 868 0x1: decode FUNCTION_LO { 869 format StoreIndexedMemory { 870 0x0: swxc1({{ Mem.uw = Fs.uw;}}); 871 0x1: sdxc1({{ Mem.ud = Fs.ud;}}); 872 0x5: suxc1({{ Mem.ud = Fs.ud;}}, 873 {{ EA = (Rs + Rt) & ~7; }}); 874 } 875 876 0x7: Prefetch::prefx({{ EA = Rs + Rt; }}); 877 } 878 879 0x3: decode FUNCTION_LO { 880 0x6: Float64Op::alnv_ps({{ if (Rs<2:0> == 0) { 881 Fd.ud = Fs.ud; 882 } else if (Rs<2:0> == 4) { 883 #if BYTE_ORDER == BIG_ENDIAN 884 Fd.ud = Fs.ud<31:0> << 32 | 885 Ft.ud<63:32>; 886 #elif BYTE_ORDER == LITTLE_ENDIAN 887 Fd.ud = Ft.ud<31:0> << 32 | 888 Fs.ud<63:32>; 889 #endif 890 } else { 891 Fd.ud = Fd.ud; 892 } 893 }}); 894 } 895 896 format FloatAccOp { 897 0x4: decode FUNCTION_LO { 898 0x0: madd_s({{ Fd.sf = (Fs.sf * Ft.sf) + Fr.sf; }}); 899 0x1: madd_d({{ Fd.df = (Fs.df * Ft.df) + Fr.df; }}); 900 0x6: madd_ps({{ 901 Fd1.sf = (Fs1.df * Ft1.df) + Fr1.df; 902 Fd2.sf = (Fs2.df * Ft2.df) + Fr2.df; 903 }}); 904 } 905 906 0x5: decode FUNCTION_LO { 907 0x0: msub_s({{ Fd.sf = (Fs.sf * Ft.sf) - Fr.sf; }}); 908 0x1: msub_d({{ Fd.df = (Fs.df * Ft.df) - Fr.df; }}); 909 0x6: msub_ps({{ 910 Fd1.sf = (Fs1.df * Ft1.df) - Fr1.df; 911 Fd2.sf = (Fs2.df * Ft2.df) - Fr2.df; 912 }}); 913 } 914 915 0x6: decode FUNCTION_LO { 916 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 917 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Ft.df) + Fr.df; }}); 918 0x6: nmadd_ps({{ 919 Fd1.sf = -((Fs1.df * Ft1.df) + Fr1.df); 920 Fd2.sf = -((Fs2.df * Ft2.df) + Fr2.df); 921 }}); 922 } 923 924 0x7: decode FUNCTION_LO { 925 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Ft.sf) - Fr.sf; }}); 926 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Ft.df) - Fr.df; }}); 927 0x6: nmsub_ps({{ 928 Fd1.sf = -((Fs1.df * Ft1.df) - Fr1.df); 929 Fd2.sf = -((Fs2.df * Ft2.df) - Fr2.df); 930 }}); 931 } 932 933 } 934 } 935 936 format Branch { 937 0x4: beql({{ cond = (Rs.sw == Rt.sw); }}, Likely); 938 0x5: bnel({{ cond = (Rs.sw != Rt.sw); }}, Likely); 939 0x6: blezl({{ cond = (Rs.sw <= 0); }}, Likely); 940 0x7: bgtzl({{ cond = (Rs.sw > 0); }}, Likely); 941 } 942 } 943 944 0x3: decode OPCODE_LO { 945 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 946 0x4: decode FUNCTION_HI { 947 0x0: decode FUNCTION_LO { 948 0x2: IntOp::mul({{ int64_t temp1 = Rs.sd * Rt.sd; 949 Rd.sw = temp1<31:0> 950 }}); 951 952 format HiLoOp { 953 0x0: madd({{ val = ((int64_t) HI << 32 | LO) + 954 (Rs.sd * Rt.sd); 955 }}); 956 0x1: maddu({{ val = ((uint64_t) HI << 32 | LO) + 957 (Rs.ud * Rt.ud); 958 }}); 959 0x4: msub({{ val = ((int64_t) HI << 32 | LO) - 960 (Rs.sd * Rt.sd); 961 }}); 962 0x5: msubu({{ val = ((uint64_t) HI << 32 | LO) - 963 (Rs.ud * Rt.ud); 964 }}); 965 } 966 } 967 968 0x4: decode FUNCTION_LO { 969 format BasicOp { 970 0x0: clz({{ int cnt = 32; 971 for (int idx = 31; idx >= 0; idx--) { 972 if( Rs<idx:idx> == 1) { 973 cnt = 31 - idx; 974 break; 975 } 976 } 977 Rd.uw = cnt; 978 }}); 979 0x1: clo({{ int cnt = 32; 980 for (int idx = 31; idx >= 0; idx--) { 981 if( Rs<idx:idx> == 0) { 982 cnt = 31 - idx; 983 break; 984 } 985 } 986 Rd.uw = cnt; 987 }}); 988 } 989 } 990 991 0x7: decode FUNCTION_LO { 992 0x7: FailUnimpl::sdbbp(); 993 } 994 } 995 996 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 997 //of the Architecture 998 0x7: decode FUNCTION_HI { 999 0x0: decode FUNCTION_LO { 1000 format BasicOp { 1001 0x0: ext({{ Rt.uw = bits(Rs.uw, MSB+LSB, LSB); }}); 1002 0x4: ins({{ Rt.uw = bits(Rt.uw, 31, MSB+1) << (MSB+1) | 1003 bits(Rs.uw, MSB-LSB, 0) << LSB | 1004 bits(Rt.uw, LSB-1, 0); 1005 }}); 1006 } 1007 } 1008 1009 0x1: decode FUNCTION_LO { 1010 format MipsMT { 1011 0x0: fork(); 1012 0x1: yield(); 1013 } 1014 } 1015 1016 //Table A-10 MIPS32 BSHFL Encoding of sa Field 1017 0x4: decode SA { 1018 format BasicOp { 1019 0x02: wsbh({{ Rd.uw = Rt.uw<23:16> << 24 | 1020 Rt.uw<31:24> << 16 | 1021 Rt.uw<7:0> << 8 | 1022 Rt.uw<15:8>; 1023 }}); 1024 0x10: seb({{ Rd.sw = Rt.sb; }}); 1025 0x18: seh({{ Rd.sw = Rt.sh; }}); 1026 } 1027 } 1028 1029 0x6: decode FUNCTION_LO { 1030 0x7: FailUnimpl::rdhwr(); 1031 } 1032 } 1033 } 1034 1035 0x4: decode OPCODE_LO { 1036 format LoadMemory { 1037 0x0: lb({{ Rt.sw = Mem.sb; }}); 1038 0x1: lh({{ Rt.sw = Mem.sh; }}); 1039 0x3: lw({{ Rt.sw = Mem.sw; }}); 1040 0x4: lbu({{ Rt.uw = Mem.ub; }}); 1041 0x5: lhu({{ Rt.uw = Mem.uh; }}); 1042 } 1043 1044 format LoadUnalignedMemory { 1045 0x2: lwl({{ uint32_t mem_shift = 24 - (8 * byte_offset); 1046 Rt.uw = mem_word << mem_shift | 1047 Rt.uw & mask(mem_shift); 1048 }}); 1049 0x6: lwr({{ uint32_t mem_shift = 8 * byte_offset; 1050 Rt.uw = Rt.uw & (mask(mem_shift) << (32 - mem_shift)) | 1051 mem_word >> mem_shift; 1052 }}); 1053 } 1054 } 1055 1056 0x5: decode OPCODE_LO { 1057 format StoreMemory { 1058 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 1059 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 1060 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 1061 } 1062 1063 format StoreUnalignedMemory { 1064 0x2: swl({{ uint32_t reg_shift = 24 - (8 * byte_offset); 1065 uint32_t mem_shift = 32 - reg_shift; 1066 mem_word = mem_word & (mask(reg_shift) << mem_shift) | 1067 Rt.uw >> reg_shift; 1068 }}); 1069 0x6: swr({{ uint32_t reg_shift = 8 * byte_offset; 1070 mem_word = Rt.uw << reg_shift | 1071 mem_word & (mask(reg_shift)); 1072 }}); 1073 } 1074 1075 0x7: FailUnimpl::cache(); 1076 } 1077 1078 0x6: decode OPCODE_LO { 1079 format LoadMemory { 1080 0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED); 1081 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 1082 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 1083 } 1084 1085 0x3: Prefetch::pref(); 1086 } 1087 1088 1089 0x7: decode OPCODE_LO { 1090 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, 1091 {{ uint64_t tmp = write_result; 1092 Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; 1093 }}, mem_flags=LOCKED, inst_flags = IsStoreConditional); 1094 1095 format StoreMemory { 1096 0x1: swc1({{ Mem.uw = Ft.uw; }}); 1097 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 1098 } 1099 } 1100} 1101 1102 1103