decoder.isa revision 2604
1// -*- mode:c++ -*- 2 3//////////////////////////////////////////////////////////////////// 4// 5// The actual MIPS32 ISA decoder 6// ----------------------------- 7// The following instructions are specified in the MIPS32 ISA 8// Specification. Decoding closely follows the style specified 9// in the MIPS32 ISAthe specification document starting with Table 10// A-2 (document available @ www.mips.com) 11// 12//@todo: Distinguish "unknown/future" use insts from "reserved" 13// ones 14decode OPCODE_HI default Unknown::unknown() { 15 16 // Derived From ... Table A-2 MIPS32 ISA Manual 17 0x0: decode OPCODE_LO { 18 19 0x0: decode FUNCTION_HI { 20 0x0: decode FUNCTION_LO { 21 0x1: decode MOVCI { 22 format BasicOp { 23 0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}}); 24 1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}}); 25 } 26 } 27 28 format BasicOp { 29 30 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 31 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions. 32 0x0: decode RS { 33 0x0: decode RT { //fix Nop traditional vs. Nop converted disassembly later 34 0x0: decode RD default Nop::nop(){ 35 0x0: decode SA { 36 0x1: ssnop({{ ; }}); //really sll r0,r0,1 37 0x3: ehb({{ ; }}); //really sll r0,r0,3 38 } 39 } 40 41 default: sll({{ Rd = Rt.uw << SA; }}); 42 } 43 44 } 45 46 0x2: decode RS_SRL { 47 0x0:decode SRL { 48 0: srl({{ Rd = Rt.uw >> SA; }}); 49 50 //Hardcoded assuming 32-bit ISA, probably need parameter here 51 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 52 } 53 } 54 55 0x3: decode RS { 56 0x0: sra({{ 57 uint32_t temp = Rt >> SA; 58 59 if ( (Rt & 0x80000000) > 0 ) { 60 uint32_t mask = 0x80000000; 61 for(int i=0; i < SA; i++) { 62 temp |= mask; 63 mask = mask >> 1; 64 } 65 } 66 67 Rd = temp; 68 }}); 69 } 70 71 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 72 73 0x6: decode SRLV { 74 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 75 76 //Hardcoded assuming 32-bit ISA, probably need parameter here 77 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 78 } 79 80 0x7: srav({{ 81 int shift_amt = Rs<4:0>; 82 83 uint32_t temp = Rt >> shift_amt; 84 85 if ( (Rt & 0x80000000) > 0 ) { 86 uint32_t mask = 0x80000000; 87 for(int i=0; i < shift_amt; i++) { 88 temp |= mask; 89 mask = mask >> 1; 90 } 91 } 92 93 Rd = temp; 94 }}); 95 } 96 } 97 98 0x1: decode FUNCTION_LO { 99 100 //Table A-3 Note: "Specific encodings of the hint field are used 101 //to distinguish JR from JR.HB and JALR from JALR.HB" 102 format Jump { 103 0x0: decode HINT { 104 0:jr({{ NNPC = Rs & ~1; }},IsReturn); 105 106 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn); 107 } 108 109 0x1: decode HINT { 110 0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn); 111 112 1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); 113 } 114 } 115 116 format BasicOp { 117 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 118 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 119 } 120 121 format BasicOp { 122 0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative); 123 0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative); 124 0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative); 125 } 126 } 127 128 0x2: decode FUNCTION_LO { 129 format BasicOp { 130 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }}); 131 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }}); 132 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }}); 133 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }}); 134 } 135 } 136 137 0x3: decode FUNCTION_LO { 138 format IntOp { 139 0x0: mult({{ 140 int64_t temp1 = Rs.sd * Rt.sd; 141 xc->setMiscReg(Hi,temp1<63:32>); 142 xc->setMiscReg(Lo,temp1<31:0>); 143 }}); 144 145 0x1: multu({{ 146 uint64_t temp1 = Rs.ud * Rt.ud; 147 xc->setMiscReg(Hi,temp1<63:32>); 148 xc->setMiscReg(Lo,temp1<31:0>); 149 }}); 150 151 0x2: div({{ 152 xc->setMiscReg(Hi,Rs.sd % Rt.sd); 153 xc->setMiscReg(Lo,Rs.sd / Rt.sd); 154 }}); 155 156 0x3: divu({{ 157 xc->setMiscReg(Hi,Rs.ud % Rt.ud); 158 xc->setMiscReg(Lo,Rs.ud / Rt.ud); 159 }}); 160 } 161 } 162 163 0x4: decode HINT { 164 0x0: decode FUNCTION_LO { 165 format IntOp { 166 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}}); 167 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 168 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 169 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 170 0x4: and({{ Rd = Rs & Rt;}}); 171 0x5: or({{ Rd = Rs | Rt;}}); 172 0x6: xor({{ Rd = Rs ^ Rt;}}); 173 0x7: nor({{ Rd = ~(Rs | Rt);}}); 174 } 175 } 176 } 177 178 0x5: decode HINT { 179 0x0: decode FUNCTION_LO { 180 format IntOp{ 181 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 182 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 183 } 184 } 185 } 186 187 0x6: decode FUNCTION_LO { 188 format Trap { 189 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 190 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 191 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 192 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 193 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 194 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 195 } 196 } 197 } 198 199 0x1: decode REGIMM_HI { 200 0x0: decode REGIMM_LO { 201 format Branch { 202 0x0: bltz({{ cond = (Rs.sw < 0); }}); 203 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 204 } 205 206 format BranchLikely { 207 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 208 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 209 } 210 } 211 212 0x1: decode REGIMM_LO { 213 format Trap { 214 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 215 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 216 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 217 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 218 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 219 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 220 } 221 } 222 223 0x2: decode REGIMM_LO { 224 format Branch { 225 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn); 226 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn); 227 } 228 229 format BranchLikely { 230 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); 231 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); 232 } 233 } 234 235 0x3: decode REGIMM_LO { 236 format WarnUnimpl { 237 0x7: synci(); 238 } 239 } 240 } 241 242 format Jump { 243 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 244 245 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn); 246 } 247 248 format Branch { 249 0x4: beq({{ cond = (Rs.sw == Rt.sw); }}); 250 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 251 0x6: decode RT { 252 0x0: blez({{ cond = (Rs.sw <= 0); }}); 253 } 254 255 0x7: decode RT { 256 0x0: bgtz({{ cond = (Rs.sw > 0); }}); 257 } 258 } 259 } 260 261 0x1: decode OPCODE_LO { 262 format IntOp { 263 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 264 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 265 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 266 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 267 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 268 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 269 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 270 271 0x7: decode RS { 272 0x0: lui({{ Rt = imm << 16}}); 273 } 274 } 275 } 276 277 0x2: decode OPCODE_LO { 278 279 //Table A-11 MIPS32 COP0 Encoding of rs Field 280 0x0: decode RS_MSB { 281 0x0: decode RS { 282 format System { 283 0x0: mfc0({{ 284 //uint64_t reg_num = Rd.uw; 285 286 Rt = xc->readMiscReg(RD << 5 | SEL); 287 }}); 288 289 0x4: mtc0({{ 290 //uint64_t reg_num = Rd.uw; 291 292 xc->setMiscReg(RD << 5 | SEL,Rt); 293 }}); 294 295 0x8: mftr({{ 296 //The contents of the coprocessor 0 register specified by the 297 //combination of rd and sel are loaded into general register 298 //rt. Note that not all coprocessor 0 registers support the 299 //sel field. In those instances, the sel field must be zero. 300 301 //MT Code Needed Here 302 }}); 303 304 0xC: mttr({{ 305 //The contents of the coprocessor 0 register specified by the 306 //combination of rd and sel are loaded into general register 307 //rt. Note that not all coprocessor 0 registers support the 308 //sel field. In those instances, the sel field must be zero. 309 310 //MT Code Needed Here 311 }}); 312 313 314 0xA: rdpgpr({{ 315 //Accessing Previous Shadow Set Register Number 316 //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/; 317 //uint64_t reg_num = Rt.uw; 318 319 //Rd = xc->regs.IntRegFile[prev]; 320 //Rd = xc->shadowIntRegFile[prev][reg_num]; 321 }}); 322 323 0xB: decode RD { 324 325 0x0: decode SC { 326 0x0: dvpe({{ 327 Rt.sw = xc->readMiscReg(MVPControl); 328 xc->setMiscReg(MVPControl,0); 329 }}); 330 331 0x1: evpe({{ 332 Rt.sw = xc->readMiscReg(MVPControl); 333 xc->setMiscReg(MVPControl,1); 334 }}); 335 } 336 337 0x1: decode SC { 338 0x0: dmt({{ 339 Rt.sw = xc->readMiscReg(VPEControl); 340 xc->setMiscReg(VPEControl,0); 341 }}); 342 343 0x1: emt({{ 344 Rt.sw = xc->readMiscReg(VPEControl); 345 xc->setMiscReg(VPEControl,1); 346 }}); 347 } 348 349 0xC: decode SC { 350 0x0: di({{ 351 Rt.sw = xc->readMiscReg(Status); 352 xc->setMiscReg(Status,0); 353 }}); 354 355 0x1: ei({{ 356 Rt.sw = xc->readMiscReg(Status); 357 xc->setMiscReg(Status,1); 358 }}); 359 } 360 } 361 362 0xE: wrpgpr({{ 363 //Accessing Previous Shadow Set Register Number 364 //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/); 365 //uint64_t reg_num = Rd.uw; 366 367 //xc->regs.IntRegFile[prev]; 368 //xc->shadowIntRegFile[prev][reg_num] = Rt; 369 }}); 370 } 371 } 372 373 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 374 0x1: decode FUNCTION { 375 format System { 376 0x01: tlbr({{ }}); 377 0x02: tlbwi({{ }}); 378 0x06: tlbwr({{ }}); 379 0x08: tlbp({{ }}); 380 } 381 382 format WarnUnimpl { 383 0x18: eret(); 384 0x1F: deret(); 385 0x20: wait(); 386 } 387 } 388 } 389 390 //Table A-13 MIPS32 COP1 Encoding of rs Field 391 0x1: decode RS_MSB { 392 393 0x0: decode RS_HI { 394 0x0: decode RS_LO { 395 format FloatOp { 396 0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }}); 397 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 398 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 399 0x7: mthc1({{ 400 uint64_t fs_hi = Rt.ud << 32; 401 uint64_t fs_lo = Fs.ud & 0x0000FFFF; 402 Fs.ud = fs_hi & fs_lo; 403 }}); 404 } 405 406 format System { 407 0x2: cfc1({{ 408 uint32_t fcsr_reg = xc->readMiscReg(FCSR); 409 410 switch (FS) 411 { 412 case 0: 413 Rt = xc->readMiscReg(FIR); 414 break; 415 case 25: 416 Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23; 417 break; 418 case 26: 419 Rt = 0 | (fcsr_reg & 0x0003F07C); 420 break; 421 case 28: 422 Rt = 0 | (fcsr_reg); 423 break; 424 case 31: 425 Rt = fcsr_reg; 426 break; 427 default: 428 panic("FP Control Value (%d) Not Available. Ignoring Access to" 429 "Floating Control Status Register",fcsr_reg); 430 } 431 }}); 432 433 0x6: ctc1({{ 434 uint32_t fcsr_reg = xc->readMiscReg(FCSR); 435 uint32_t temp; 436 437 switch (FS) 438 { 439 case 25: 440 temp = 0 | (Rt.uw<7:1> << 25) // move 31...25 441 | (fcsr_reg & 0x01000000) // bit 24 442 | (fcsr_reg & 0x004FFFFF);// bit 22...0 443 break; 444 445 case 26: 446 temp = 0 | (fcsr_reg & 0xFFFC0000) // move 31...18 447 | Rt.uw<17:12> << 12 // bit 17...12 448 | (fcsr_reg & 0x00000F80) << 7// bit 11...7 449 | Rt.uw<6:2> << 2 // bit 6...2 450 | (fcsr_reg & 0x00000002); // bit 1...0 451 break; 452 453 case 28: 454 temp = 0 | (fcsr_reg & 0xFE000000) // move 31...25 455 | Rt.uw<2:2> << 24 // bit 24 456 | (fcsr_reg & 0x00FFF000) << 23// bit 23...12 457 | Rt.uw<11:7> << 7 // bit 24 458 | (fcsr_reg & 0x000007E) 459 | Rt.uw<1:0>;// bit 22...0 460 break; 461 462 case 31: 463 temp = Rt.uw; 464 break; 465 466 default: 467 panic("FP Control Value (%d) Not Available. Ignoring Access to" 468 "Floating Control Status Register",fcsr_reg); 469 } 470 471 xc->setMiscReg(FCSR,temp); 472 }}); 473 } 474 } 475 476 0x1: decode ND { 477 0x0: decode TF { 478 format Branch { 479 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 480 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 481 } 482 } 483 484 0x1: decode TF { 485 format BranchLikely { 486 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 487 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 488 } 489 } 490 } 491 } 492 493 0x1: decode RS_HI { 494 0x2: decode RS_LO { 495 496 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 497 //(( single-word )) 498 0x0: decode FUNCTION_HI { 499 0x0: decode FUNCTION_LO { 500 format FloatOp { 501 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 502 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 503 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 504 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 505 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 506 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 507 0x6: mov_s({{ Fd.sf = Fs.sf;}}); 508 0x7: neg_s({{ Fd.sf = -1 * Fs.sf;}}); 509 } 510 } 511 512 0x1: decode FUNCTION_LO { 513 format Float64Op { 514 0x0: round_l_s({{ 515 Fd.ud = fpConvert(roundFP(Fs.sf), SINGLE_TO_LONG); 516 }}); 517 518 0x1: trunc_l_s({{ 519 Fd.ud = fpConvert(truncFP(Fs.sf), SINGLE_TO_LONG); 520 }}); 521 522 0x2: ceil_l_s({{ 523 Fd.ud = fpConvert(ceil(Fs.sf), SINGLE_TO_LONG); 524 }}); 525 526 0x3: floor_l_s({{ 527 Fd.ud = fpConvert(floor(Fs.sf), SINGLE_TO_LONG); 528 }}); 529 } 530 531 format FloatOp { 532 0x4: round_w_s({{ 533 Fd.uw = fpConvert(roundFP(Fs.sf), SINGLE_TO_WORD); 534 }}); 535 536 0x5: trunc_w_s({{ 537 Fd.uw = fpConvert(truncFP(Fs.sf), SINGLE_TO_WORD); 538 }}); 539 540 0x6: ceil_w_s({{ 541 Fd.uw = fpConvert(ceil(Fs.sf), SINGLE_TO_WORD); 542 }}); 543 544 0x7: floor_w_s({{ 545 Fd.uw = fpConvert(floor(Fs.sf), SINGLE_TO_WORD); 546 }}); 547 } 548 } 549 550 0x2: decode FUNCTION_LO { 551 0x1: decode MOVCF { 552 format FloatOp { 553 0x0: movf_s({{if (getFPConditionCode(CC) == 0) Fd = Fs;}}); 554 0x1: movt_s({{if (getFPConditionCode(CC) == 1) Fd = Fs;}}); 555 } 556 } 557 558 format FloatOp { 559 0x2: movz_s({{ if (Rt == 0) Fd = Fs; }}); 560 0x3: movn_s({{ if (Rt != 0) Fd = Fs; }}); 561 0x5: recip_s({{ Fd = 1 / Fs; }}); 562 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); 563 } 564 } 565 566 0x4: decode FUNCTION_LO { 567 568 format FloatConvertOp { 569 0x1: cvt_d_s({{ 570 Fd.ud = fpConvert(Fs.sf, SINGLE_TO_DOUBLE); 571 }}); 572 573 0x4: cvt_w_s({{ 574 Fd.uw = fpConvert(Fs.sf, SINGLE_TO_WORD); 575 }}); 576 } 577 578 format FloatConvertOp { 579 0x5: cvt_l_s({{ 580 Fd.ud = fpConvert(Fs.sf, SINGLE_TO_LONG); 581 }}); 582 583 0x6: cvt_ps_st({{ 584 Fd.ud = (uint64_t)Fs.uw << 32 | (uint64_t)Ft.uw; 585 }}); 586 } 587 } 588 589 0x6: decode FUNCTION_LO { 590 format FloatCompareOp { 591 0x0: c_f_s({{ cond = 0; }}); 592 593 0x1: c_un_s({{ 594 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 595 cond = 1; 596 else 597 cond = 0; 598 }}); 599 600 0x2: c_eq_s({{ 601 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 602 cond = 0; 603 else 604 cond = (Fs.sf == Ft.sf); 605 }}); 606 607 0x3: c_ueq_s({{ 608 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 609 cond = 1; 610 else 611 cond = (Fs.sf == Ft.sf); 612 }}); 613 614 0x4: c_olt_s({{ 615 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 616 cond = 0; 617 else 618 cond = (Fs.sf < Ft.sf); 619 }}); 620 621 0x5: c_ult_s({{ 622 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 623 cond = 1; 624 else 625 cond = (Fs.sf < Ft.sf); 626 }}); 627 628 0x6: c_ole_s({{ 629 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 630 cond = 0; 631 else 632 cond = (Fs.sf <= Ft.sf); 633 }}); 634 635 0x7: c_ule_s({{ 636 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 637 cond = 1; 638 else 639 cond = (Fs.sf <= Ft.sf); 640 }}); 641 } 642 } 643 644 0x7: decode FUNCTION_LO { 645 format FloatCompareWithXcptOp { 646 0x0: c_sf_s({{ cond = 0; }}); 647 648 0x1: c_ngle_s({{ 649 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 650 cond = 1; 651 else 652 cond = 0; 653 }}); 654 655 0x2: c_seq_s({{ 656 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 657 cond = 0; 658 else 659 cond = (Fs.sf == Ft.sf); 660 }}); 661 662 0x3: c_ngl_s({{ 663 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 664 cond = 1; 665 else 666 cond = (Fs.sf == Ft.sf); 667 }}); 668 669 0x4: c_lt_s({{ 670 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 671 cond = 0; 672 else 673 cond = (Fs.sf < Ft.sf); 674 }}); 675 676 0x5: c_nge_s({{ 677 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 678 cond = 1; 679 else 680 cond = (Fs.sf < Ft.sf); 681 }}); 682 683 0x6: c_le_s({{ 684 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 685 cond = 0; 686 else 687 cond = (Fs.sf <= Ft.sf); 688 }}); 689 690 0x7: c_ngt_s({{ 691 if (unorderedFP(Fs.uw) || unorderedFP(Ft.uw)) 692 cond = 1; 693 else 694 cond = (Fs.sf <= Ft.sf); 695 }}); 696 } 697 } 698 } 699 700 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 701 0x1: decode FUNCTION_HI { 702 0x0: decode FUNCTION_LO { 703 format FloatOp { 704 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 705 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 706 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 707 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 708 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 709 0x5: absd({{ Fd.df = fabs(Fs.df);}}); 710 0x6: movd({{ Fd.ud = Fs.ud;}}); 711 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 712 } 713 } 714 715 0x1: decode FUNCTION_LO { 716 format Float64Op { 717 0x0: round_l_d({{ 718 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_NEAREST); 719 }}); 720 721 0x1: trunc_l_d({{ 722 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_ZERO); 723 }}); 724 725 0x2: ceil_l_d({{ 726 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_UP); 727 }}); 728 729 0x3: floor_l_d({{ 730 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_DOWN); 731 }}); 732 } 733 734 format FloatOp { 735 0x4: round_w_d({{ 736 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_NEAREST); 737 }}); 738 739 0x5: trunc_w_d({{ 740 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_ZERO); 741 }}); 742 743 0x6: ceil_w_d({{ 744 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_UP); 745 }}); 746 747 0x7: floor_w_d({{ 748 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_DOWN); 749 }}); 750 } 751 } 752 753 0x2: decode FUNCTION_LO { 754 0x1: decode MOVCF { 755 format FloatOp { 756 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }}); 757 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }}); 758 } 759 } 760 761 format BasicOp { 762 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); 763 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); 764 } 765 766 format Float64Op { 767 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 768 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 769 } 770 } 771 772 0x4: decode FUNCTION_LO { 773 format FloatOp { 774 0x0: cvt_s_d({{ 775 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 776 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_SINGLE, rnd_mode); 777 }}); 778 779 0x4: cvt_w_d({{ 780 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 781 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, rnd_mode); 782 }}); 783 } 784 785 //only legal for 64 bit 786 format Float64Op { 787 0x5: cvt_l_d({{ 788 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 789 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, rnd_mode); 790 }}); 791 } 792 } 793 794 0x6: decode FUNCTION_LO { 795 format FloatCompareOp { 796 0x0: c_f_d({{ cond = 0; }}); 797 798 0x1: c_un_d({{ 799 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 800 cond = 1; 801 else 802 cond = 0; 803 }}); 804 805 0x2: c_eq_d({{ 806 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 807 cond = 0; 808 else 809 cond = (Fs.df == Ft.df); 810 }}); 811 812 0x3: c_ueq_d({{ 813 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 814 cond = 1; 815 else 816 cond = (Fs.df == Ft.df); 817 }}); 818 819 0x4: c_olt_d({{ 820 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 821 cond = 0; 822 else 823 cond = (Fs.df < Ft.df); 824 }}); 825 826 0x5: c_ult_d({{ 827 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 828 cond = 1; 829 else 830 cond = (Fs.df < Ft.df); 831 }}); 832 833 0x6: c_ole_d({{ 834 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 835 cond = 0; 836 else 837 cond = (Fs.df <= Ft.df); 838 }}); 839 840 0x7: c_ule_d({{ 841 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 842 cond = 1; 843 else 844 cond = (Fs.df <= Ft.df); 845 }}); 846 } 847 } 848 849 0x7: decode FUNCTION_LO { 850 format FloatCompareWithXcptOp { 851 0x0: c_sf_d({{ cond = 0; }}); 852 853 0x1: c_ngle_d({{ 854 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 855 cond = 1; 856 else 857 cond = 0; 858 }}); 859 860 0x2: c_seq_d({{ 861 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 862 cond = 0; 863 else 864 cond = (Fs.df == Ft.df); 865 }}); 866 867 0x3: c_ngl_d({{ 868 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 869 cond = 1; 870 else 871 cond = (Fs.df == Ft.df); 872 }}); 873 874 0x4: c_lt_d({{ 875 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 876 cond = 0; 877 else 878 cond = (Fs.df < Ft.df); 879 }}); 880 881 0x5: c_nge_d({{ 882 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 883 cond = 1; 884 else 885 cond = (Fs.df < Ft.df); 886 }}); 887 888 0x6: c_le_d({{ 889 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 890 cond = 0; 891 else 892 cond = (Fs.df <= Ft.df); 893 }}); 894 895 0x7: c_ngt_d({{ 896 if (unorderedFP(Fs.ud) || unorderedFP(Ft.ud)) 897 cond = 1; 898 else 899 cond = (Fs.df <= Ft.df); 900 }}); 901 } 902 } 903 } 904 905 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 906 0x4: decode FUNCTION { 907 format FloatOp { 908 0x20: cvt_s_w({{ 909 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 910 Fd.uw = convert_and_round(Fs.sf, WORD_TO_SINGLE, rnd_mode); 911 }}); 912 913 0x21: cvt_d_w({{ 914 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 915 Fd.ud = convert_and_round(Fs.sf, WORD_TO_DOUBLE, rnd_mode); 916 }}); 917 } 918 } 919 920 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 921 //Note: "1. Format type L is legal only if 64-bit floating point operations 922 //are enabled." 923 0x5: decode FUNCTION_HI { 924 format Float64Op { 925 0x10: cvt_s_l({{ 926 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 927 Fd.uw = convert_and_round(Fs.ud, LONG_TO_SINGLE, rnd_mode); 928 }}); 929 930 0x11: cvt_d_l({{ 931 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 932 Fd.ud = convert_and_round(Fs.ud, LONG_TO_DOUBLE, rnd_mode); 933 }}); 934 } 935 } 936 937 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 938 //Note: "1. Format type PS is legal only if 64-bit floating point operations 939 //are enabled. " 940 0x6: decode FUNCTION_HI { 941 0x0: decode FUNCTION_LO { 942 format Float64Op { 943 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 944 //Lower Halves Independently but we take simulator shortcut 945 Fd.df = Fs.df + Ft.df; 946 }}); 947 948 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 949 //Lower Halves Independently but we take simulator shortcut 950 Fd.df = Fs.df - Ft.df; 951 }}); 952 953 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 954 //Lower Halves Independently but we take simulator shortcut 955 Fd.df = Fs.df * Ft.df; 956 }}); 957 958 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 959 //Lower Halves Independently but we take simulator shortcut 960 Fd.df = fabs(Fs.df); 961 }}); 962 963 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 964 //Lower Halves Independently but we take simulator shortcut 965 //Fd.df = Fs<31:0> | Ft<31:0>; 966 }}); 967 968 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 969 //Lower Halves Independently but we take simulator shortcut 970 Fd.df = -1 * Fs.df; 971 }}); 972 } 973 } 974 975 0x2: decode FUNCTION_LO { 976 0x1: decode MOVCF { 977 format Float64Op { 978 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}}); 979 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 980 } 981 } 982 983 format BasicOp { 984 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 985 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }}); 986 } 987 988 } 989 990 0x4: decode FUNCTION_LO { 991 0x0: Float64Op::cvt_s_pu({{ 992 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 993 Fd.uw = convert_and_round(Fs.ud, PUPPER_TO_SINGLE, rnd_mode); 994 }}); 995 } 996 997 0x5: decode FUNCTION_LO { 998 format Float64Op { 999 0x0: cvt_s_pl({{ 1000 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 1001 Fd.uw = convert_and_round(Fs.ud, PLOWER_TO_SINGLE, 1002 rnd_mode); 1003 }}); 1004 1005 0x4: pll({{ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<31:0>; }}); 1006 0x5: plu({{ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>;}}); 1007 0x6: pul({{ Fd.ud = Fs.ud<63:32> << 32 | Ft.ud<31:0>; }}); 1008 0x7: puu({{ Fd.ud = Fs.ud<63:32> << 32 | Ft.ud<63:32>;}}); 1009 } 1010 } 1011 1012 0x6: decode FUNCTION_LO { 1013 format FloatOp { 1014 0x0: c_f_ps({{ ; }}); 1015 0x1: c_un_ps({{ ; }}); 1016 0x2: c_eq_ps({{ ; }}); 1017 0x3: c_ueq_ps({{ ; }}); 1018 0x4: c_olt_ps({{ ; }}); 1019 0x5: c_ult_ps({{ ; }}); 1020 0x6: c_ole_ps({{ ; }}); 1021 0x7: c_ule_ps({{ ; }}); 1022 } 1023 } 1024 1025 0x7: decode FUNCTION_LO { 1026 format FloatOp { 1027 0x0: c_sf_ps({{ ; }}); 1028 0x1: c_ngle_ps({{ ; }}); 1029 0x2: c_seq_ps({{ ; }}); 1030 0x3: c_ngl_ps({{ ; }}); 1031 0x4: c_lt_ps({{ ; }}); 1032 0x5: c_nge_ps({{ ; }}); 1033 0x6: c_le_ps({{ ; }}); 1034 0x7: c_ngt_ps({{ ; }}); 1035 } 1036 } 1037 1038 } 1039 } 1040 } 1041 } 1042 1043 //Table A-19 MIPS32 COP2 Encoding of rs Field 1044 0x2: decode RS_MSB { 1045 0x0: decode RS_HI { 1046 0x0: decode RS_LO { 1047 format WarnUnimpl { 1048 0x0: mfc2(); 1049 0x2: cfc2(); 1050 0x3: mfhc2(); 1051 0x4: mtc2(); 1052 0x6: ctc2(); 1053 0x7: mftc2(); 1054 } 1055 } 1056 1057 0x1: decode ND { 1058 0x0: decode TF { 1059 format WarnUnimpl { 1060 0x0: bc2f(); 1061 0x1: bc2t(); 1062 } 1063 } 1064 1065 0x1: decode TF { 1066 format WarnUnimpl { 1067 0x0: bc2fl(); 1068 0x1: bc2tl(); 1069 } 1070 } 1071 } 1072 } 1073 } 1074 1075 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 1076 //Note: "COP1X instructions are legal only if 64-bit floating point 1077 //operations are enabled." 1078 0x3: decode FUNCTION_HI { 1079 0x0: decode FUNCTION_LO { 1080 format LoadFloatMemory { 1081 0x0: lwxc1({{ Ft.uw = Mem.uw;}}, {{ EA = Rs + Rt; }}); 1082 0x1: ldxc1({{ Ft.ud = Mem.ud;}}, {{ EA = Rs + Rt; }}); 1083 0x5: luxc1({{ Ft.uw = Mem.ud;}}, {{ EA = Rs + Rt; }}); 1084 } 1085 } 1086 1087 0x1: decode FUNCTION_LO { 1088 format StoreFloatMemory { 1089 0x0: swxc1({{ Mem.uw = Ft.uw;}}, {{ EA = Rs + Rt; }}); 1090 0x1: sdxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }}); 1091 0x5: suxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }}); 1092 } 1093 1094 0x7: WarnUnimpl::prefx(); 1095 } 1096 1097 format FloatOp { 1098 0x3: WarnUnimpl::alnv_ps(); 1099 1100 format BasicOp { 1101 0x4: decode FUNCTION_LO { 1102 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 1103 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 1104 0x6: madd_ps({{ 1105 //Must Check for Exception Here... Supposed to Operate on Upper and 1106 //Lower Halves Independently but we take simulator shortcut 1107 Fd.df = (Fs.df * Fs.df) + Fr.df; 1108 }}); 1109 } 1110 1111 0x5: decode FUNCTION_LO { 1112 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 1113 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 1114 0x6: msub_ps({{ 1115 //Must Check for Exception Here... Supposed to Operate on Upper and 1116 //Lower Halves Independently but we take simulator shortcut 1117 Fd.df = (Fs.df * Fs.df) - Fr.df; 1118 }}); 1119 } 1120 1121 0x6: decode FUNCTION_LO { 1122 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 1123 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 1124 0x6: nmadd_ps({{ 1125 //Must Check for Exception Here... Supposed to Operate on Upper and 1126 //Lower Halves Independently but we take simulator shortcut 1127 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 1128 }}); 1129 } 1130 1131 0x7: decode FUNCTION_LO { 1132 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 1133 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 1134 0x6: nmsub_ps({{ 1135 //Must Check for Exception Here... Supposed to Operate on Upper and 1136 //Lower Halves Independently but we take simulator shortcut 1137 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 1138 }}); 1139 } 1140 } 1141 } 1142 } 1143 1144 //MIPS obsolete instructions 1145 format BranchLikely { 1146 0x4: beql({{ cond = (Rs.sw == 0); }}); 1147 0x5: bnel({{ cond = (Rs.sw != 0); }}); 1148 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 1149 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 1150 } 1151 } 1152 1153 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 1154 1155 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1156 0x4: decode FUNCTION_HI { 1157 1158 0x0: decode FUNCTION_LO { 1159 format IntOp { 1160 0x0: madd({{ 1161 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1162 temp1 = temp1 + (Rs.sw * Rt.sw); 1163 xc->setMiscReg(Hi,temp1<63:32>); 1164 xc->setMiscReg(Lo,temp1<31:0>); 1165 }}); 1166 1167 0x1: maddu({{ 1168 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1169 temp1 = temp1 + (Rs.uw * Rt.uw); 1170 xc->setMiscReg(Hi,temp1<63:32>); 1171 xc->setMiscReg(Lo,temp1<31:0>); 1172 }}); 1173 1174 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 1175 1176 0x4: msub({{ 1177 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1178 temp1 = temp1 - (Rs.sw * Rt.sw); 1179 xc->setMiscReg(Hi,temp1<63:32>); 1180 xc->setMiscReg(Lo,temp1<31:0>); 1181 }}); 1182 1183 0x5: msubu({{ 1184 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1185 temp1 = temp1 - (Rs.uw * Rt.uw); 1186 xc->setMiscReg(Hi,temp1<63:32>); 1187 xc->setMiscReg(Lo,temp1<31:0>); 1188 }}); 1189 } 1190 } 1191 1192 0x4: decode FUNCTION_LO { 1193 format BasicOp { 1194 0x0: clz({{ 1195 int cnt = 0; 1196 uint32_t mask = 0x80000000; 1197 for (int i=0; i < 32; i++) 1198 if( (Rs & mask) == 0) { 1199 cnt++; 1200 } else { 1201 break; 1202 } 1203 } 1204 Rd.uw = cnt; 1205 }}); 1206 1207 0x1: clo({{ 1208 int cnt = 0; 1209 uint32_t mask = 0x80000000; 1210 for (int i=0; i < 32; i++) 1211 if( (Rs & mask) != 0) { 1212 cnt++; 1213 } else { 1214 break; 1215 } 1216 } 1217 Rd.uw = cnt; 1218 }}); 1219 } 1220 } 1221 1222 0x7: decode FUNCTION_LO { 1223 0x7: WarnUnimpl::sdbbp(); 1224 } 1225 } 1226 1227 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 1228 0x7: decode FUNCTION_HI { 1229 1230 0x0: decode FUNCTION_LO { 1231 format FailUnimpl { 1232 0x1: ext(); 1233 0x4: ins(); 1234 } 1235 } 1236 1237 0x1: decode FUNCTION_LO { 1238 format FailUnimpl { 1239 0x0: fork(); 1240 0x1: yield(); 1241 } 1242 } 1243 1244 1245 //Table A-10 MIPS32 BSHFL Encoding of sa Field 1246 0x4: decode SA { 1247 1248 0x02: FailUnimpl::wsbh(); 1249 1250 format BasicOp { 1251 0x10: seb({{ Rd.sw = Rt<7:0>}}); 1252 0x18: seh({{ Rd.sw = Rt<15:0>}}); 1253 } 1254 } 1255 1256 0x6: decode FUNCTION_LO { 1257 0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }} 1258 } 1259 } 1260 } 1261 1262 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 1263 format LoadMemory { 1264 0x0: lb({{ Rt.sw = Mem.sb; }}); 1265 0x1: lh({{ Rt.sw = Mem.sh; }}); 1266 1267 0x2: lwl({{ 1268 uint32_t mem_word = Mem.uw; 1269 uint32_t unalign_addr = Rs + disp; 1270 uint32_t offset = unalign_addr & 0x00000003; 1271#if BYTE_ORDER == BIG_ENDIAN 1272 switch(offset) 1273 { 1274 case 0: 1275 Rt = mem_word; 1276 break; 1277 1278 case 1: 1279 Rt &= 0x000F; 1280 Rt |= (mem_word << 4); 1281 break; 1282 1283 case 2: 1284 Rt &= 0x00FF; 1285 Rt |= (mem_word << 8); 1286 break; 1287 1288 case 3: 1289 Rt &= 0x0FFF; 1290 Rt |= (mem_word << 12); 1291 break; 1292 1293 default: 1294 panic("lwl: bad offset"); 1295 } 1296#elif BYTE_ORDER == LITTLE_ENDIAN 1297 switch(offset) 1298 { 1299 case 0: 1300 Rt &= 0x0FFF; 1301 Rt |= (mem_word << 12); 1302 break; 1303 1304 case 1: 1305 Rt &= 0x00FF; 1306 Rt |= (mem_word << 8); 1307 break; 1308 1309 case 2: 1310 Rt &= 0x000F; 1311 Rt |= (mem_word << 4); 1312 break; 1313 1314 case 3: 1315 Rt = mem_word; 1316 break; 1317 1318 default: 1319 panic("lwl: bad offset"); 1320 } 1321#endif 1322 }}, {{ EA = (Rs + disp) & ~3; }}); 1323 1324 0x3: lw({{ Rt.sw = Mem.sw; }}); 1325 0x4: lbu({{ Rt.uw = Mem.ub; }}); 1326 0x5: lhu({{ Rt.uw = Mem.uh; }}); 1327 0x6: lwr({{ 1328 uint32_t mem_word = Mem.uw; 1329 uint32_t unalign_addr = Rs + disp; 1330 uint32_t offset = unalign_addr & 0x00000003; 1331 1332#if BYTE_ORDER == BIG_ENDIAN 1333 switch(offset) 1334 { 1335 case 0: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; 1336 case 1: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; 1337 case 2: Rt &= 0xF000; Rt |= (mem_word >> 4); break; 1338 case 3: Rt = mem_word; break; 1339 default: panic("lwr: bad offset"); 1340 } 1341#elif BYTE_ORDER == LITTLE_ENDIAN 1342 switch(offset) 1343 { 1344 case 0: Rt = mem_word; break; 1345 case 1: Rt &= 0xF000; Rt |= (mem_word >> 4); break; 1346 case 2: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; 1347 case 3: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; 1348 default: panic("lwr: bad offset"); 1349 } 1350#endif 1351 }}, 1352 {{ EA = (Rs + disp) & ~3; }}); 1353 } 1354 1355 0x7: FailUnimpl::reserved(); 1356 } 1357 1358 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 1359 format StoreMemory { 1360 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 1361 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 1362 0x2: swl({{ 1363 uint32_t mem_word = 0; 1364 uint32_t aligned_addr = (Rs + disp) & ~3; 1365 uint32_t unalign_addr = Rs + disp; 1366 uint32_t offset = unalign_addr & 0x00000003; 1367 1368 DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x", 1369 aligned_addr,unalign_addr,offset); 1370 1371 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); 1372 1373#if BYTE_ORDER == BIG_ENDIAN 1374 switch(offset) 1375 { 1376 case 0: 1377 Mem = Rt; 1378 break; 1379 1380 case 1: 1381 mem_word &= 0xF000; 1382 mem_word |= (Rt >> 4); 1383 Mem = mem_word; 1384 break; 1385 1386 case 2: 1387 mem_word &= 0xFF00; 1388 mem_word |= (Rt >> 8); 1389 Mem = mem_word; 1390 break; 1391 1392 case 3: 1393 mem_word &= 0xFFF0; 1394 mem_word |= (Rt >> 12); 1395 Mem = mem_word; 1396 break; 1397 1398 default: 1399 panic("swl: bad offset"); 1400 } 1401#elif BYTE_ORDER == LITTLE_ENDIAN 1402 switch(offset) 1403 { 1404 case 0: 1405 mem_word &= 0xFFF0; 1406 mem_word |= (Rt >> 12); 1407 Mem = mem_word; 1408 break; 1409 1410 case 1: 1411 mem_word &= 0xFF00; 1412 mem_word |= (Rt >> 8); 1413 Mem = mem_word; 1414 break; 1415 1416 case 2: 1417 mem_word &= 0xF000; 1418 mem_word |= (Rt >> 4); 1419 Mem = mem_word; 1420 break; 1421 1422 case 3: 1423 Mem = Rt; 1424 break; 1425 1426 default: 1427 panic("swl: bad offset"); 1428 } 1429#endif 1430 }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT); 1431 1432 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 1433 1434 0x6: swr({{ 1435 uint32_t mem_word = 0; 1436 uint32_t aligned_addr = (Rs + disp) & ~3; 1437 uint32_t unalign_addr = Rs + disp; 1438 uint32_t offset = unalign_addr & 0x00000003; 1439 1440 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); 1441 1442#if BYTE_ORDER == BIG_ENDIAN 1443 switch(offset) 1444 { 1445 case 0: 1446 mem_word &= 0x0FFF; 1447 mem_word |= (Rt << 12); 1448 Mem = mem_word; 1449 break; 1450 1451 case 1: 1452 mem_word &= 0x00FF; 1453 mem_word |= (Rt << 8); 1454 Mem = mem_word; 1455 break; 1456 1457 case 2: 1458 mem_word &= 0x000F; 1459 mem_word |= (Rt << 4); 1460 Mem = mem_word; 1461 break; 1462 1463 case 3: 1464 Mem = Rt; 1465 break; 1466 1467 default: 1468 panic("swr: bad offset"); 1469 } 1470#elif BYTE_ORDER == LITTLE_ENDIAN 1471 switch(offset) 1472 { 1473 case 0: 1474 Mem = Rt; 1475 break; 1476 1477 case 1: 1478 mem_word &= 0x000F; 1479 mem_word |= (Rt << 4); 1480 Mem = mem_word; 1481 break; 1482 1483 case 2: 1484 mem_word &= 0x00FF; 1485 mem_word |= (Rt << 8); 1486 Mem = mem_word; 1487 break; 1488 1489 case 3: 1490 mem_word &= 0x0FFF; 1491 mem_word |= (Rt << 12); 1492 Mem = mem_word; 1493 break; 1494 1495 default: 1496 panic("swr: bad offset"); 1497 } 1498#endif 1499 }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT); 1500 } 1501 1502 format WarnUnimpl { 1503 0x7: cache(); 1504 } 1505 1506 } 1507 1508 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 1509 0x0: LoadMemory::ll({{Rt.uw = Mem.uw}},mem_flags=LOCKED); 1510 1511 format LoadFloatMemory { 1512 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 1513 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 1514 } 1515 } 1516 1517 1518 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 1519 0x0: StoreMemory::sc({{ Mem.uw = Rt.uw; Rt.uw = 1; }}); 1520 1521 format StoreFloatMemory { 1522 0x1: swc1({{ Mem.uw = Ft.uw; }}); 1523 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 1524 } 1525 } 1526} 1527 1528 1529