decoder.isa revision 2603
1// -*- mode:c++ -*- 2 3//////////////////////////////////////////////////////////////////// 4// 5// The actual MIPS32 ISA decoder 6// ----------------------------- 7// The following instructions are specified in the MIPS32 ISA 8// Specification. Decoding closely follows the style specified 9// in the MIPS32 ISAthe specification document starting with Table 10// A-2 (document available @ www.mips.com) 11// 12//@todo: Distinguish "unknown/future" use insts from "reserved" 13// ones 14decode OPCODE_HI default Unknown::unknown() { 15 16 // Derived From ... Table A-2 MIPS32 ISA Manual 17 0x0: decode OPCODE_LO { 18 19 0x0: decode FUNCTION_HI { 20 0x0: decode FUNCTION_LO { 21 0x1: decode MOVCI { 22 format BasicOp { 23 0: movf({{ if (xc->readMiscReg(FPCR) != CC) Rd = Rs}}); 24 1: movt({{ if (xc->readMiscReg(FPCR) == CC) Rd = Rs}}); 25 } 26 } 27 28 format BasicOp { 29 30 //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields 31 //are used to distinguish among the SLL, NOP, SSNOP and EHB functions. 32 0x0: decode RS { 33 0x0: decode RT { //fix Nop traditional vs. Nop converted disassembly later 34 0x0: decode RD default Nop::nop(){ 35 0x0: decode SA { 36 0x1: ssnop({{ ; }}); //really sll r0,r0,1 37 0x3: ehb({{ ; }}); //really sll r0,r0,3 38 } 39 } 40 41 default: sll({{ Rd = Rt.uw << SA; }}); 42 } 43 44 } 45 46 0x2: decode RS_SRL { 47 0x0:decode SRL { 48 0: srl({{ Rd = Rt.uw >> SA; }}); 49 50 //Hardcoded assuming 32-bit ISA, probably need parameter here 51 1: rotr({{ Rd = (Rt.uw << (32 - SA)) | (Rt.uw >> SA);}}); 52 } 53 } 54 55 0x3: decode RS { 56 0x0: sra({{ 57 uint32_t temp = Rt >> SA; 58 59 if ( (Rt & 0x80000000) > 0 ) { 60 uint32_t mask = 0x80000000; 61 for(int i=0; i < SA; i++) { 62 temp |= mask; 63 mask = mask >> 1; 64 } 65 } 66 67 Rd = temp; 68 }}); 69 } 70 71 0x4: sllv({{ Rd = Rt.uw << Rs<4:0>; }}); 72 73 0x6: decode SRLV { 74 0: srlv({{ Rd = Rt.uw >> Rs<4:0>; }}); 75 76 //Hardcoded assuming 32-bit ISA, probably need parameter here 77 1: rotrv({{ Rd = (Rt.uw << (32 - Rs<4:0>)) | (Rt.uw >> Rs<4:0>);}}); 78 } 79 80 0x7: srav({{ 81 int shift_amt = Rs<4:0>; 82 83 uint32_t temp = Rt >> shift_amt; 84 85 if ( (Rt & 0x80000000) > 0 ) { 86 uint32_t mask = 0x80000000; 87 for(int i=0; i < shift_amt; i++) { 88 temp |= mask; 89 mask = mask >> 1; 90 } 91 } 92 93 Rd = temp; 94 }}); 95 } 96 } 97 98 0x1: decode FUNCTION_LO { 99 100 //Table A-3 Note: "Specific encodings of the hint field are used 101 //to distinguish JR from JR.HB and JALR from JALR.HB" 102 format Jump { 103 0x0: decode HINT { 104 0:jr({{ NNPC = Rs & ~1; }},IsReturn); 105 106 1:jr_hb({{ NNPC = Rs & ~1; clear_exe_inst_hazards(); }},IsReturn); 107 } 108 109 0x1: decode HINT { 110 0: jalr({{ Rd = NNPC; NNPC = Rs; }},IsCall,IsReturn); 111 112 1: jalr_hb({{ Rd = NNPC; NNPC = Rs; clear_exe_inst_hazards();}},IsCall,IsReturn); 113 } 114 } 115 116 format BasicOp { 117 0x2: movz({{ if (Rt == 0) Rd = Rs; }}); 118 0x3: movn({{ if (Rt != 0) Rd = Rs; }}); 119 } 120 121 format BasicOp { 122 0x4: syscall({{ xc->syscall(R2); }},IsNonSpeculative); 123 0x5: break({{ panic("Not implemented break yet"); }},IsNonSpeculative); 124 0x7: sync({{ panic("Not implemented sync yet"); }},IsNonSpeculative); 125 } 126 } 127 128 0x2: decode FUNCTION_LO { 129 format BasicOp { 130 0x0: mfhi({{ Rd = xc->readMiscReg(Hi); }}); 131 0x1: mthi({{ xc->setMiscReg(Hi,Rs); }}); 132 0x2: mflo({{ Rd = xc->readMiscReg(Lo); }}); 133 0x3: mtlo({{ xc->setMiscReg(Lo,Rs); }}); 134 } 135 } 136 137 0x3: decode FUNCTION_LO { 138 format IntOp { 139 0x0: mult({{ 140 int64_t temp1 = Rs.sd * Rt.sd; 141 xc->setMiscReg(Hi,temp1<63:32>); 142 xc->setMiscReg(Lo,temp1<31:0>); 143 }}); 144 145 0x1: multu({{ 146 uint64_t temp1 = Rs.ud * Rt.ud; 147 xc->setMiscReg(Hi,temp1<63:32>); 148 xc->setMiscReg(Lo,temp1<31:0>); 149 }}); 150 151 0x2: div({{ 152 xc->setMiscReg(Hi,Rs.sd % Rt.sd); 153 xc->setMiscReg(Lo,Rs.sd / Rt.sd); 154 }}); 155 156 0x3: divu({{ 157 xc->setMiscReg(Hi,Rs.ud % Rt.ud); 158 xc->setMiscReg(Lo,Rs.ud / Rt.ud); 159 }}); 160 } 161 } 162 163 0x4: decode HINT { 164 0x0: decode FUNCTION_LO { 165 format IntOp { 166 0x0: add({{ Rd.sw = Rs.sw + Rt.sw;/*Trap on Overflow*/}}); 167 0x1: addu({{ Rd.sw = Rs.sw + Rt.sw;}}); 168 0x2: sub({{ Rd.sw = Rs.sw - Rt.sw; /*Trap on Overflow*/}}); 169 0x3: subu({{ Rd.sw = Rs.sw - Rt.sw;}}); 170 0x4: and({{ Rd = Rs & Rt;}}); 171 0x5: or({{ Rd = Rs | Rt;}}); 172 0x6: xor({{ Rd = Rs ^ Rt;}}); 173 0x7: nor({{ Rd = ~(Rs | Rt);}}); 174 } 175 } 176 } 177 178 0x5: decode HINT { 179 0x0: decode FUNCTION_LO { 180 format IntOp{ 181 0x2: slt({{ Rd.sw = ( Rs.sw < Rt.sw ) ? 1 : 0}}); 182 0x3: sltu({{ Rd.uw = ( Rs.uw < Rt.uw ) ? 1 : 0}}); 183 } 184 } 185 } 186 187 0x6: decode FUNCTION_LO { 188 format Trap { 189 0x0: tge({{ cond = (Rs.sw >= Rt.sw); }}); 190 0x1: tgeu({{ cond = (Rs.uw >= Rt.uw); }}); 191 0x2: tlt({{ cond = (Rs.sw < Rt.sw); }}); 192 0x3: tltu({{ cond = (Rs.uw >= Rt.uw); }}); 193 0x4: teq({{ cond = (Rs.sw == Rt.sw); }}); 194 0x6: tne({{ cond = (Rs.sw != Rt.sw); }}); 195 } 196 } 197 } 198 199 0x1: decode REGIMM_HI { 200 0x0: decode REGIMM_LO { 201 format Branch { 202 0x0: bltz({{ cond = (Rs.sw < 0); }}); 203 0x1: bgez({{ cond = (Rs.sw >= 0); }}); 204 } 205 206 format BranchLikely { 207 0x2: bltzl({{ cond = (Rs.sw < 0); }}); 208 0x3: bgezl({{ cond = (Rs.sw >= 0); }}); 209 } 210 } 211 212 0x1: decode REGIMM_LO { 213 format Trap { 214 0x0: tgei( {{ cond = (Rs.sw >= INTIMM); }}); 215 0x1: tgeiu({{ cond = (Rs.uw >= INTIMM); }}); 216 0x2: tlti( {{ cond = (Rs.sw < INTIMM); }}); 217 0x3: tltiu({{ cond = (Rs.uw < INTIMM); }}); 218 0x4: teqi( {{ cond = (Rs.sw == INTIMM);}}); 219 0x6: tnei( {{ cond = (Rs.sw != INTIMM);}}); 220 } 221 } 222 223 0x2: decode REGIMM_LO { 224 format Branch { 225 0x0: bltzal({{ cond = (Rs.sw < 0); }}, IsCall,IsReturn); 226 0x1: bgezal({{ cond = (Rs.sw >= 0); }}, IsCall,IsReturn); 227 } 228 229 format BranchLikely { 230 0x2: bltzall({{ cond = (Rs.sw < 0); }}, IsCall, IsReturn); 231 0x3: bgezall({{ cond = (Rs.sw >= 0); }}, IsCall, IsReturn); 232 } 233 } 234 235 0x3: decode REGIMM_LO { 236 format WarnUnimpl { 237 0x7: synci(); 238 } 239 } 240 } 241 242 format Jump { 243 0x2: j({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2);}}); 244 245 0x3: jal({{ NNPC = (NPC & 0xF0000000) | (JMPTARG << 2); }},IsCall,IsReturn); 246 } 247 248 format Branch { 249 0x4: beq({{ cond = (Rs.sw == Rt.sw); }}); 250 0x5: bne({{ cond = (Rs.sw != Rt.sw); }}); 251 0x6: decode RT { 252 0x0: blez({{ cond = (Rs.sw <= 0); }}); 253 } 254 255 0x7: decode RT { 256 0x0: bgtz({{ cond = (Rs.sw > 0); }}); 257 } 258 } 259 } 260 261 0x1: decode OPCODE_LO { 262 format IntOp { 263 0x0: addi({{ Rt.sw = Rs.sw + imm; /*Trap If Overflow*/}}); 264 0x1: addiu({{ Rt.sw = Rs.sw + imm;}}); 265 0x2: slti({{ Rt.sw = ( Rs.sw < imm) ? 1 : 0 }}); 266 0x3: sltiu({{ Rt.uw = ( Rs.uw < (uint32_t)sextImm ) ? 1 : 0 }}); 267 0x4: andi({{ Rt.sw = Rs.sw & zextImm;}}); 268 0x5: ori({{ Rt.sw = Rs.sw | zextImm;}}); 269 0x6: xori({{ Rt.sw = Rs.sw ^ zextImm;}}); 270 271 0x7: decode RS { 272 0x0: lui({{ Rt = imm << 16}}); 273 } 274 } 275 } 276 277 0x2: decode OPCODE_LO { 278 279 //Table A-11 MIPS32 COP0 Encoding of rs Field 280 0x0: decode RS_MSB { 281 0x0: decode RS { 282 format System { 283 0x0: mfc0({{ 284 //uint64_t reg_num = Rd.uw; 285 286 Rt = xc->readMiscReg(RD << 5 | SEL); 287 }}); 288 289 0x4: mtc0({{ 290 //uint64_t reg_num = Rd.uw; 291 292 xc->setMiscReg(RD << 5 | SEL,Rt); 293 }}); 294 295 0x8: mftr({{ 296 //The contents of the coprocessor 0 register specified by the 297 //combination of rd and sel are loaded into general register 298 //rt. Note that not all coprocessor 0 registers support the 299 //sel field. In those instances, the sel field must be zero. 300 301 //MT Code Needed Here 302 }}); 303 304 0xC: mttr({{ 305 //The contents of the coprocessor 0 register specified by the 306 //combination of rd and sel are loaded into general register 307 //rt. Note that not all coprocessor 0 registers support the 308 //sel field. In those instances, the sel field must be zero. 309 310 //MT Code Needed Here 311 }}); 312 313 314 0xA: rdpgpr({{ 315 //Accessing Previous Shadow Set Register Number 316 //uint64_t prev = xc->readMiscReg(SRSCtl)/*[PSS]*/; 317 //uint64_t reg_num = Rt.uw; 318 319 //Rd = xc->regs.IntRegFile[prev]; 320 //Rd = xc->shadowIntRegFile[prev][reg_num]; 321 }}); 322 323 0xB: decode RD { 324 325 0x0: decode SC { 326 0x0: dvpe({{ 327 Rt.sw = xc->readMiscReg(MVPControl); 328 xc->setMiscReg(MVPControl,0); 329 }}); 330 331 0x1: evpe({{ 332 Rt.sw = xc->readMiscReg(MVPControl); 333 xc->setMiscReg(MVPControl,1); 334 }}); 335 } 336 337 0x1: decode SC { 338 0x0: dmt({{ 339 Rt.sw = xc->readMiscReg(VPEControl); 340 xc->setMiscReg(VPEControl,0); 341 }}); 342 343 0x1: emt({{ 344 Rt.sw = xc->readMiscReg(VPEControl); 345 xc->setMiscReg(VPEControl,1); 346 }}); 347 } 348 349 0xC: decode SC { 350 0x0: di({{ 351 Rt.sw = xc->readMiscReg(Status); 352 xc->setMiscReg(Status,0); 353 }}); 354 355 0x1: ei({{ 356 Rt.sw = xc->readMiscReg(Status); 357 xc->setMiscReg(Status,1); 358 }}); 359 } 360 } 361 362 0xE: wrpgpr({{ 363 //Accessing Previous Shadow Set Register Number 364 //uint64_t prev = xc->readMiscReg(SRSCtl/*[PSS]*/); 365 //uint64_t reg_num = Rd.uw; 366 367 //xc->regs.IntRegFile[prev]; 368 //xc->shadowIntRegFile[prev][reg_num] = Rt; 369 }}); 370 } 371 } 372 373 //Table A-12 MIPS32 COP0 Encoding of Function Field When rs=CO 374 0x1: decode FUNCTION { 375 format System { 376 0x01: tlbr({{ }}); 377 0x02: tlbwi({{ }}); 378 0x06: tlbwr({{ }}); 379 0x08: tlbp({{ }}); 380 } 381 382 format WarnUnimpl { 383 0x18: eret(); 384 0x1F: deret(); 385 0x20: wait(); 386 } 387 } 388 } 389 390 //Table A-13 MIPS32 COP1 Encoding of rs Field 391 0x1: decode RS_MSB { 392 393 0x0: decode RS_HI { 394 0x0: decode RS_LO { 395 format FloatOp { 396 0x0: mfc1 ({{ Rt.uw = Fs.uw<31:0>; }}); 397 0x3: mfhc1({{ Rt.uw = Fs.ud<63:32>;}}); 398 0x4: mtc1 ({{ Fs.uw = Rt.uw; }}); 399 0x7: mthc1({{ 400 uint64_t fs_hi = Rt.ud << 32; 401 uint64_t fs_lo = Fs.ud & 0x0000FFFF; 402 Fs.ud = fs_hi & fs_lo; 403 }}); 404 } 405 406 format System { 407 0x2: cfc1({{ 408 uint32_t fcsr_reg = xc->readMiscReg(FCSR); 409 410 switch (FS) 411 { 412 case 0: 413 Rt = xc->readMiscReg(FIR); 414 break; 415 case 25: 416 Rt = 0 | (fcsr_reg & 0xFE000000) >> 24 | (fcsr_reg & 0x00800000) >> 23; 417 break; 418 case 26: 419 Rt = 0 | (fcsr_reg & 0x0003F07C); 420 break; 421 case 28: 422 Rt = 0 | (fcsr_reg); 423 break; 424 case 31: 425 Rt = fcsr_reg; 426 break; 427 default: 428 panic("FP Control Value (%d) Not Available. Ignoring Access to" 429 "Floating Control Status Register",fcsr_reg); 430 } 431 }}); 432 433 0x6: ctc1({{ 434 uint32_t fcsr_reg = xc->readMiscReg(FCSR); 435 uint32_t temp; 436 437 switch (FS) 438 { 439 case 25: 440 temp = 0 | (Rt.uw<7:1> << 25) // move 31...25 441 | (fcsr_reg & 0x01000000) // bit 24 442 | (fcsr_reg & 0x004FFFFF);// bit 22...0 443 break; 444 445 case 26: 446 temp = 0 | (fcsr_reg & 0xFFFC0000) // move 31...18 447 | Rt.uw<17:12> << 12 // bit 17...12 448 | (fcsr_reg & 0x00000F80) << 7// bit 11...7 449 | Rt.uw<6:2> << 2 // bit 6...2 450 | (fcsr_reg & 0x00000002); // bit 1...0 451 break; 452 453 case 28: 454 temp = 0 | (fcsr_reg & 0xFE000000) // move 31...25 455 | Rt.uw<2:2> << 24 // bit 24 456 | (fcsr_reg & 0x00FFF000) << 23// bit 23...12 457 | Rt.uw<11:7> << 7 // bit 24 458 | (fcsr_reg & 0x000007E) 459 | Rt.uw<1:0>;// bit 22...0 460 break; 461 462 case 31: 463 temp = Rt.uw; 464 break; 465 466 default: 467 panic("FP Control Value (%d) Not Available. Ignoring Access to" 468 "Floating Control Status Register",fcsr_reg); 469 } 470 471 xc->setMiscReg(FCSR,temp); 472 }}); 473 } 474 } 475 476 0x1: decode ND { 477 0x0: decode TF { 478 format Branch { 479 0x0: bc1f({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 480 0x1: bc1t({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 481 } 482 } 483 484 0x1: decode TF { 485 format BranchLikely { 486 0x0: bc1fl({{ cond = (xc->readMiscReg(FPCR) == 0); }}); 487 0x1: bc1tl({{ cond = (xc->readMiscReg(FPCR) == 1); }}); 488 } 489 } 490 } 491 } 492 493 0x1: decode RS_HI { 494 0x2: decode RS_LO { 495 496 //Table A-14 MIPS32 COP1 Encoding of Function Field When rs=S 497 //(( single-word )) 498 0x0: decode FUNCTION_HI { 499 0x0: decode FUNCTION_LO { 500 format FloatOp { 501 0x0: add_s({{ Fd.sf = Fs.sf + Ft.sf;}}); 502 0x1: sub_s({{ Fd.sf = Fs.sf - Ft.sf;}}); 503 0x2: mul_s({{ Fd.sf = Fs.sf * Ft.sf;}}); 504 0x3: div_s({{ Fd.sf = Fs.sf / Ft.sf;}}); 505 0x4: sqrt_s({{ Fd.sf = sqrt(Fs.sf);}}); 506 0x5: abs_s({{ Fd.sf = fabs(Fs.sf);}}); 507 0x6: mov_s({{ Fd.sf = Fs.sf;}}); 508 0x7: neg_s({{ Fd.sf = -1 * Fs.sf;}}); 509 } 510 } 511 512 0x1: decode FUNCTION_LO { 513 format Float64Op { 514 0x0: round_l_s({{ 515 Fd.ud = fpConvert(roundFP(Fs.sf), SINGLE_TO_LONG); 516 }}); 517 518 0x1: trunc_l_s({{ 519 Fd.ud = fpConvert(truncFP(Fs.sf), SINGLE_TO_LONG); 520 }}); 521 522 0x2: ceil_l_s({{ 523 Fd.ud = fpConvert(ceil(Fs.sf), SINGLE_TO_LONG); 524 }}); 525 526 0x3: floor_l_s({{ 527 Fd.ud = fpConvert(floor(Fs.sf), SINGLE_TO_LONG); 528 }}); 529 } 530 531 format FloatOp { 532 0x4: round_w_s({{ 533 Fd.uw = fpConvert(roundFP(Fs.sf), SINGLE_TO_WORD); 534 }}); 535 536 0x5: trunc_w_s({{ 537 Fd.uw = fpConvert(truncFP(Fs.sf), SINGLE_TO_WORD); 538 }}); 539 540 0x6: ceil_w_s({{ 541 Fd.uw = fpConvert(ceil(Fs.sf), SINGLE_TO_WORD); 542 }}); 543 544 0x7: floor_w_s({{ 545 Fd.uw = fpConvert(floor(Fs.sf), SINGLE_TO_WORD); 546 }}); 547 } 548 } 549 550 0x2: decode FUNCTION_LO { 551 0x1: decode MOVCF { 552 format FloatOp { 553 0x0: movf_s({{if (getFPConditionCode(CC) == 0) Fd = Fs;}}); 554 0x1: movt_s({{if (getFPConditionCode(CC) == 1) Fd = Fs;}}); 555 } 556 } 557 558 format FloatOp { 559 0x2: movz_s({{ if (Rt == 0) Fd = Fs; }}); 560 0x3: movn_s({{ if (Rt != 0) Fd = Fs; }}); 561 0x5: recip_s({{ Fd = 1 / Fs; }}); 562 0x6: rsqrt_s({{ Fd = 1 / sqrt(Fs);}}); 563 } 564 } 565 566 0x4: decode FUNCTION_LO { 567 568 format FloatConvertOp { 569 0x1: cvt_d_s({{ 570 Fd.ud = fpConvert(Fs.sf, SINGLE_TO_DOUBLE); 571 }}); 572 573 0x4: cvt_w_s({{ 574 Fd.uw = fpConvert(Fs.sf, SINGLE_TO_WORD); 575 }}); 576 } 577 578 format FloatConvertOp { 579 0x5: cvt_l_s({{ 580 Fd.ud = fpConvert(Fs.sf, SINGLE_TO_LONG); 581 }}); 582 583 0x6: cvt_ps_st({{ 584 Fd.ud = (uint64_t)Fs.uw << 32 | (uint64_t)Ft.uw; 585 }}); 586 } 587 } 588 589 0x6: decode FUNCTION_LO { 590 format FloatCompareOp { 591 0x0: c_f_s({{ cond = 0; }}); 592 0x1: c_un_s({{ 593 if (unordered(Rs) || unordered(Rt)) 594 cond = 1; 595 else 596 cond = 0; 597 }}); 598 0x2: c_eq_s({{ 599 if (unordered(Rs) || unordered(Rt)) 600 cond = 0; 601 else 602 cond = (Fs == Ft); 603 }}); 604 0x3: c_ueq_s({{ 605 if (unordered(Rs) || unordered(Rt)) 606 cond = 1; 607 else 608 cond = (Fs == Ft); 609 }}); 610 0x4: c_olt_s({{ 611 if (unordered(Rs) || unordered(Rt)) 612 cond = 0; 613 else 614 cond = ; 615 ; 616 }}); 617 0x5: c_ult_s({{ 618 if (unordered(Rs) || unordered(Rt)) 619 cond = 1; 620 else 621 cond = ; 622 ; 623 }}); 624 0x6: c_ole_s({{ 625 if (unordered(Rs) || unordered(Rt)) 626 cond = 0; 627 else 628 cond = ; 629 }}); 630 0x7: c_ule_s({{ 631 if (unordered(Rs) || unordered(Rt)) 632 cond = 1; 633 else 634 cond = ; 635 }}); 636 } 637 } 638 639 0x7: decode FUNCTION_LO { 640 format FloatCompareWithXcptOp { 641 0x0: c_sf_s({{ cond = 0; }}); 642 0x1: c_ngle_s({{ 643 if (unordered(Rs) || unordered(Rt)) 644 cond = 1; 645 else 646 cond = ; 647 }}); 648 0x2: c_seq_s({{ 649 if (unordered(Rs) || unordered(Rt)) 650 cond = 1; 651 else 652 cond = ; 653 }}); 654 0x3: c_ngl_s({{ 655 if (unordered(Rs) || unordered(Rt)) 656 cond = 1; 657 else 658 cond = ; 659 }}); 660 0x4: c_lt_s({{ 661 if (unordered(Rs) || unordered(Rt)) 662 cond = 1; 663 else 664 cond = ; 665 }}); 666 0x5: c_nge_s({{ 667 if (unordered(Rs) || unordered(Rt)) 668 cond = 1; 669 else 670 cond = ; 671 }}); 672 0x6: c_le_s({{ 673 if (unordered(Rs) || unordered(Rt)) 674 cond = 1; 675 else 676 cond = ; 677 }}); 678 0x7: c_ngt_s({{ 679 if (unordered(Rs) || unordered(Rt)) 680 cond = 1; 681 else 682 cond = ; 683 }}); 684 } 685 } 686 } 687 688 //Table A-15 MIPS32 COP1 Encoding of Function Field When rs=D 689 0x1: decode FUNCTION_HI { 690 0x0: decode FUNCTION_LO { 691 format FloatOp { 692 0x0: addd({{ Fd.df = Fs.df + Ft.df;}}); 693 0x1: subd({{ Fd.df = Fs.df - Ft.df;}}); 694 0x2: muld({{ Fd.df = Fs.df * Ft.df;}}); 695 0x3: divd({{ Fd.df = Fs.df / Ft.df;}}); 696 0x4: sqrtd({{ Fd.df = sqrt(Fs.df);}}); 697 0x5: absd({{ Fd.df = fabs(Fs.df);}}); 698 0x6: movd({{ Fd.ud = Fs.ud;}}); 699 0x7: negd({{ Fd.df = -1 * Fs.df;}}); 700 } 701 } 702 703 0x1: decode FUNCTION_LO { 704 format Float64Op { 705 0x0: round_l_d({{ 706 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_NEAREST); 707 }}); 708 709 0x1: trunc_l_d({{ 710 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_ZERO); 711 }}); 712 713 0x2: ceil_l_d({{ 714 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_UP); 715 }}); 716 717 0x3: floor_l_d({{ 718 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, RND_DOWN); 719 }}); 720 } 721 722 format FloatOp { 723 0x4: round_w_d({{ 724 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_NEAREST); 725 }}); 726 727 0x5: trunc_w_d({{ 728 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_ZERO); 729 }}); 730 731 0x6: ceil_w_d({{ 732 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_UP); 733 }}); 734 735 0x7: floor_w_d({{ 736 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, RND_DOWN); 737 }}); 738 } 739 } 740 741 0x2: decode FUNCTION_LO { 742 0x1: decode MOVCF { 743 format FloatOp { 744 0x0: movfd({{if (xc->readMiscReg(FPCR) != CC) Fd.df = Fs.df; }}); 745 0x1: movtd({{if (xc->readMiscReg(FPCR) == CC) Fd.df = Fs.df; }}); 746 } 747 } 748 749 format BasicOp { 750 0x2: movzd({{ if (Rt == 0) Fd.df = Fs.df; }}); 751 0x3: movnd({{ if (Rt != 0) Fd.df = Fs.df; }}); 752 } 753 754 format Float64Op { 755 0x5: recipd({{ Fd.df = 1 / Fs.df}}); 756 0x6: rsqrtd({{ Fd.df = 1 / sqrt(Fs.df) }}); 757 } 758 } 759 760 0x4: decode FUNCTION_LO { 761 format FloatOp { 762 0x0: cvt_s_d({{ 763 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 764 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_SINGLE, rnd_mode); 765 }}); 766 767 0x4: cvt_w_d({{ 768 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 769 Fd.uw = convert_and_round(Fs.ud, DOUBLE_TO_WORD, rnd_mode); 770 }}); 771 } 772 773 //only legal for 64 bit 774 format Float64Op { 775 0x5: cvt_l_d({{ 776 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 777 Fd.ud = convert_and_round(Fs.ud, DOUBLE_TO_LONG, rnd_mode); 778 }}); 779 } 780 } 781 782 0x6: decode FUNCTION_LO { 783 format FloatOp { 784 0x0: c_f_d({{ ; }}); 785 0x1: c_un_d({{ ; }}); 786 0x2: c_eq_d({{ ; }}); 787 0x3: c_ueq_d({{ ; }}); 788 0x4: c_olt_d({{ ; }}); 789 0x5: c_ult_d({{ ; }}); 790 0x6: c_ole_d({{ ; }}); 791 0x7: c_ule_d({{ ; }}); 792 } 793 } 794 795 0x7: decode FUNCTION_LO { 796 format FloatOp { 797 0x0: c_sf_d({{ ; }}); 798 0x1: c_ngle_d({{ ; }}); 799 0x2: c_seq_d({{ ; }}); 800 0x3: c_ngl_d({{ ; }}); 801 0x4: c_lt_d({{ ; }}); 802 0x5: c_nge_d({{ ; }}); 803 0x6: c_le_d({{ ; }}); 804 0x7: c_ngt_d({{ ; }}); 805 } 806 } 807 } 808 809 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=W 810 0x4: decode FUNCTION { 811 format FloatOp { 812 0x20: cvt_s_w({{ 813 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 814 Fd.uw = convert_and_round(Fs.sf, WORD_TO_SINGLE, rnd_mode); 815 }}); 816 817 0x21: cvt_d_w({{ 818 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 819 Fd.ud = convert_and_round(Fs.sf, WORD_TO_DOUBLE, rnd_mode); 820 }}); 821 } 822 } 823 824 //Table A-16 MIPS32 COP1 Encoding of Function Field When rs=L1 825 //Note: "1. Format type L is legal only if 64-bit floating point operations 826 //are enabled." 827 0x5: decode FUNCTION_HI { 828 format Float64Op { 829 0x10: cvt_s_l({{ 830 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 831 Fd.uw = convert_and_round(Fs.ud, LONG_TO_SINGLE, rnd_mode); 832 }}); 833 834 0x11: cvt_d_l({{ 835 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 836 Fd.ud = convert_and_round(Fs.ud, LONG_TO_DOUBLE, rnd_mode); 837 }}); 838 } 839 } 840 841 //Table A-17 MIPS64 COP1 Encoding of Function Field When rs=PS1 842 //Note: "1. Format type PS is legal only if 64-bit floating point operations 843 //are enabled. " 844 0x6: decode FUNCTION_HI { 845 0x0: decode FUNCTION_LO { 846 format Float64Op { 847 0x0: addps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 848 //Lower Halves Independently but we take simulator shortcut 849 Fd.df = Fs.df + Ft.df; 850 }}); 851 852 0x1: subps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 853 //Lower Halves Independently but we take simulator shortcut 854 Fd.df = Fs.df - Ft.df; 855 }}); 856 857 0x2: mulps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 858 //Lower Halves Independently but we take simulator shortcut 859 Fd.df = Fs.df * Ft.df; 860 }}); 861 862 0x5: absps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 863 //Lower Halves Independently but we take simulator shortcut 864 Fd.df = fabs(Fs.df); 865 }}); 866 867 0x6: movps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 868 //Lower Halves Independently but we take simulator shortcut 869 //Fd.df = Fs<31:0> | Ft<31:0>; 870 }}); 871 872 0x7: negps({{ //Must Check for Exception Here... Supposed to Operate on Upper and 873 //Lower Halves Independently but we take simulator shortcut 874 Fd.df = -1 * Fs.df; 875 }}); 876 } 877 } 878 879 0x2: decode FUNCTION_LO { 880 0x1: decode MOVCF { 881 format Float64Op { 882 0x0: movfps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs;}}); 883 0x1: movtps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs;}}); 884 } 885 } 886 887 format BasicOp { 888 0x2: movzps({{if (xc->readMiscReg(FPCR) != CC) Fd = Fs; }}); 889 0x3: movnps({{if (xc->readMiscReg(FPCR) == CC) Fd = Fs; }}); 890 } 891 892 } 893 894 0x4: decode FUNCTION_LO { 895 0x0: Float64Op::cvt_s_pu({{ 896 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 897 Fd.uw = convert_and_round(Fs.ud, PUPPER_TO_SINGLE, rnd_mode); 898 }}); 899 } 900 901 0x5: decode FUNCTION_LO { 902 format Float64Op { 903 0x0: cvt_s_pl({{ 904 int rnd_mode = xc->readMiscReg(FCSR) & 0x03; 905 Fd.uw = convert_and_round(Fs.ud, PLOWER_TO_SINGLE, 906 rnd_mode); 907 }}); 908 909 0x4: pll({{ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<31:0>; }}); 910 0x5: plu({{ Fd.ud = Fs.ud<31:0> << 32 | Ft.ud<63:32>;}}); 911 0x6: pul({{ Fd.ud = Fs.ud<63:32> << 32 | Ft.ud<31:0>; }}); 912 0x7: puu({{ Fd.ud = Fs.ud<63:32> << 32 | Ft.ud<63:32>;}}); 913 } 914 } 915 916 0x6: decode FUNCTION_LO { 917 format FloatOp { 918 0x0: c_f_ps({{ ; }}); 919 0x1: c_un_ps({{ ; }}); 920 0x2: c_eq_ps({{ ; }}); 921 0x3: c_ueq_ps({{ ; }}); 922 0x4: c_olt_ps({{ ; }}); 923 0x5: c_ult_ps({{ ; }}); 924 0x6: c_ole_ps({{ ; }}); 925 0x7: c_ule_ps({{ ; }}); 926 } 927 } 928 929 0x7: decode FUNCTION_LO { 930 format FloatOp { 931 0x0: c_sf_ps({{ ; }}); 932 0x1: c_ngle_ps({{ ; }}); 933 0x2: c_seq_ps({{ ; }}); 934 0x3: c_ngl_ps({{ ; }}); 935 0x4: c_lt_ps({{ ; }}); 936 0x5: c_nge_ps({{ ; }}); 937 0x6: c_le_ps({{ ; }}); 938 0x7: c_ngt_ps({{ ; }}); 939 } 940 } 941 942 } 943 } 944 } 945 } 946 947 //Table A-19 MIPS32 COP2 Encoding of rs Field 948 0x2: decode RS_MSB { 949 0x0: decode RS_HI { 950 0x0: decode RS_LO { 951 format WarnUnimpl { 952 0x0: mfc2(); 953 0x2: cfc2(); 954 0x3: mfhc2(); 955 0x4: mtc2(); 956 0x6: ctc2(); 957 0x7: mftc2(); 958 } 959 } 960 961 0x1: decode ND { 962 0x0: decode TF { 963 format WarnUnimpl { 964 0x0: bc2f(); 965 0x1: bc2t(); 966 } 967 } 968 969 0x1: decode TF { 970 format WarnUnimpl { 971 0x0: bc2fl(); 972 0x1: bc2tl(); 973 } 974 } 975 } 976 } 977 } 978 979 //Table A-20 MIPS64 COP1X Encoding of Function Field 1 980 //Note: "COP1X instructions are legal only if 64-bit floating point 981 //operations are enabled." 982 0x3: decode FUNCTION_HI { 983 0x0: decode FUNCTION_LO { 984 format LoadFloatMemory { 985 0x0: lwxc1({{ Ft.uw = Mem.uw;}}, {{ EA = Rs + Rt; }}); 986 0x1: ldxc1({{ Ft.ud = Mem.ud;}}, {{ EA = Rs + Rt; }}); 987 0x5: luxc1({{ Ft.uw = Mem.ud;}}, {{ EA = Rs + Rt; }}); 988 } 989 } 990 991 0x1: decode FUNCTION_LO { 992 format StoreFloatMemory { 993 0x0: swxc1({{ Mem.uw = Ft.uw;}}, {{ EA = Rs + Rt; }}); 994 0x1: sdxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }}); 995 0x5: suxc1({{ Mem.ud = Ft.ud;}}, {{ EA = Rs + Rt; }}); 996 } 997 998 0x7: WarnUnimpl::prefx(); 999 } 1000 1001 format FloatOp { 1002 0x3: WarnUnimpl::alnv_ps(); 1003 1004 format BasicOp { 1005 0x4: decode FUNCTION_LO { 1006 0x0: madd_s({{ Fd.sf = (Fs.sf * Fs.sf) + Fr.sf; }}); 1007 0x1: madd_d({{ Fd.df = (Fs.df * Fs.df) + Fr.df; }}); 1008 0x6: madd_ps({{ 1009 //Must Check for Exception Here... Supposed to Operate on Upper and 1010 //Lower Halves Independently but we take simulator shortcut 1011 Fd.df = (Fs.df * Fs.df) + Fr.df; 1012 }}); 1013 } 1014 1015 0x5: decode FUNCTION_LO { 1016 0x0: msub_s({{ Fd.sf = (Fs.sf * Fs.sf) - Fr.sf; }}); 1017 0x1: msub_d({{ Fd.df = (Fs.df * Fs.df) - Fr.df; }}); 1018 0x6: msub_ps({{ 1019 //Must Check for Exception Here... Supposed to Operate on Upper and 1020 //Lower Halves Independently but we take simulator shortcut 1021 Fd.df = (Fs.df * Fs.df) - Fr.df; 1022 }}); 1023 } 1024 1025 0x6: decode FUNCTION_LO { 1026 0x0: nmadd_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 1027 0x1: nmadd_d({{ Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; }}); 1028 0x6: nmadd_ps({{ 1029 //Must Check for Exception Here... Supposed to Operate on Upper and 1030 //Lower Halves Independently but we take simulator shortcut 1031 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 1032 }}); 1033 } 1034 1035 0x7: decode FUNCTION_LO { 1036 0x0: nmsub_s({{ Fd.sf = (-1 * Fs.sf * Fs.sf) - Fr.sf; }}); 1037 0x1: nmsub_d({{ Fd.df = (-1 * Fs.df * Fs.df) - Fr.df; }}); 1038 0x6: nmsub_ps({{ 1039 //Must Check for Exception Here... Supposed to Operate on Upper and 1040 //Lower Halves Independently but we take simulator shortcut 1041 Fd.df = (-1 * Fs.df * Fs.df) + Fr.df; 1042 }}); 1043 } 1044 } 1045 } 1046 } 1047 1048 //MIPS obsolete instructions 1049 format BranchLikely { 1050 0x4: beql({{ cond = (Rs.sw == 0); }}); 1051 0x5: bnel({{ cond = (Rs.sw != 0); }}); 1052 0x6: blezl({{ cond = (Rs.sw <= 0); }}); 1053 0x7: bgtzl({{ cond = (Rs.sw > 0); }}); 1054 } 1055 } 1056 1057 0x3: decode OPCODE_LO default FailUnimpl::reserved() { 1058 1059 //Table A-5 MIPS32 SPECIAL2 Encoding of Function Field 1060 0x4: decode FUNCTION_HI { 1061 1062 0x0: decode FUNCTION_LO { 1063 format IntOp { 1064 0x0: madd({{ 1065 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1066 temp1 = temp1 + (Rs.sw * Rt.sw); 1067 xc->setMiscReg(Hi,temp1<63:32>); 1068 xc->setMiscReg(Lo,temp1<31:0>); 1069 }}); 1070 1071 0x1: maddu({{ 1072 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1073 temp1 = temp1 + (Rs.uw * Rt.uw); 1074 xc->setMiscReg(Hi,temp1<63:32>); 1075 xc->setMiscReg(Lo,temp1<31:0>); 1076 }}); 1077 1078 0x2: mul({{ Rd.sw = Rs.sw * Rt.sw; }}); 1079 1080 0x4: msub({{ 1081 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1082 temp1 = temp1 - (Rs.sw * Rt.sw); 1083 xc->setMiscReg(Hi,temp1<63:32>); 1084 xc->setMiscReg(Lo,temp1<31:0>); 1085 }}); 1086 1087 0x5: msubu({{ 1088 int64_t temp1 = xc->readMiscReg(Hi) << 32 | xc->readMiscReg(Lo) >> 32; 1089 temp1 = temp1 - (Rs.uw * Rt.uw); 1090 xc->setMiscReg(Hi,temp1<63:32>); 1091 xc->setMiscReg(Lo,temp1<31:0>); 1092 }}); 1093 } 1094 } 1095 1096 0x4: decode FUNCTION_LO { 1097 format BasicOp { 1098 0x0: clz({{ 1099 int cnt = 0; 1100 uint32_t mask = 0x80000000; 1101 for (int i=0; i < 32; i++) 1102 if( (Rs & mask) == 0) { 1103 cnt++; 1104 } else { 1105 break; 1106 } 1107 } 1108 Rd.uw = cnt; 1109 }}); 1110 1111 0x1: clo({{ 1112 int cnt = 0; 1113 uint32_t mask = 0x80000000; 1114 for (int i=0; i < 32; i++) 1115 if( (Rs & mask) != 0) { 1116 cnt++; 1117 } else { 1118 break; 1119 } 1120 } 1121 Rd.uw = cnt; 1122 }}); 1123 } 1124 } 1125 1126 0x7: decode FUNCTION_LO { 1127 0x7: WarnUnimpl::sdbbp(); 1128 } 1129 } 1130 1131 //Table A-6 MIPS32 SPECIAL3 Encoding of Function Field for Release 2 of the Architecture 1132 0x7: decode FUNCTION_HI { 1133 1134 0x0: decode FUNCTION_LO { 1135 format FailUnimpl { 1136 0x1: ext(); 1137 0x4: ins(); 1138 } 1139 } 1140 1141 0x1: decode FUNCTION_LO { 1142 format FailUnimpl { 1143 0x0: fork(); 1144 0x1: yield(); 1145 } 1146 } 1147 1148 1149 //Table A-10 MIPS32 BSHFL Encoding of sa Field 1150 0x4: decode SA { 1151 1152 0x02: FailUnimpl::wsbh(); 1153 1154 format BasicOp { 1155 0x10: seb({{ Rd.sw = Rt<7:0>}}); 1156 0x18: seh({{ Rd.sw = Rt<15:0>}}); 1157 } 1158 } 1159 1160 0x6: decode FUNCTION_LO { 1161 0x7: FailUnimpl::rdhwr();//{{ /*Rt = xc->hwRegs[RD];*/ }} 1162 } 1163 } 1164 } 1165 1166 0x4: decode OPCODE_LO default FailUnimpl::reserved() { 1167 format LoadMemory { 1168 0x0: lb({{ Rt.sw = Mem.sb; }}); 1169 0x1: lh({{ Rt.sw = Mem.sh; }}); 1170 1171 0x2: lwl({{ 1172 uint32_t mem_word = Mem.uw; 1173 uint32_t unalign_addr = Rs + disp; 1174 uint32_t offset = unalign_addr & 0x00000003; 1175#if BYTE_ORDER == BIG_ENDIAN 1176 switch(offset) 1177 { 1178 case 0: 1179 Rt = mem_word; 1180 break; 1181 1182 case 1: 1183 Rt &= 0x000F; 1184 Rt |= (mem_word << 4); 1185 break; 1186 1187 case 2: 1188 Rt &= 0x00FF; 1189 Rt |= (mem_word << 8); 1190 break; 1191 1192 case 3: 1193 Rt &= 0x0FFF; 1194 Rt |= (mem_word << 12); 1195 break; 1196 1197 default: 1198 panic("lwl: bad offset"); 1199 } 1200#elif BYTE_ORDER == LITTLE_ENDIAN 1201 switch(offset) 1202 { 1203 case 0: 1204 Rt &= 0x0FFF; 1205 Rt |= (mem_word << 12); 1206 break; 1207 1208 case 1: 1209 Rt &= 0x00FF; 1210 Rt |= (mem_word << 8); 1211 break; 1212 1213 case 2: 1214 Rt &= 0x000F; 1215 Rt |= (mem_word << 4); 1216 break; 1217 1218 case 3: 1219 Rt = mem_word; 1220 break; 1221 1222 default: 1223 panic("lwl: bad offset"); 1224 } 1225#endif 1226 }}, {{ EA = (Rs + disp) & ~3; }}); 1227 1228 0x3: lw({{ Rt.sw = Mem.sw; }}); 1229 0x4: lbu({{ Rt.uw = Mem.ub; }}); 1230 0x5: lhu({{ Rt.uw = Mem.uh; }}); 1231 0x6: lwr({{ 1232 uint32_t mem_word = Mem.uw; 1233 uint32_t unalign_addr = Rs + disp; 1234 uint32_t offset = unalign_addr & 0x00000003; 1235 1236#if BYTE_ORDER == BIG_ENDIAN 1237 switch(offset) 1238 { 1239 case 0: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; 1240 case 1: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; 1241 case 2: Rt &= 0xF000; Rt |= (mem_word >> 4); break; 1242 case 3: Rt = mem_word; break; 1243 default: panic("lwr: bad offset"); 1244 } 1245#elif BYTE_ORDER == LITTLE_ENDIAN 1246 switch(offset) 1247 { 1248 case 0: Rt = mem_word; break; 1249 case 1: Rt &= 0xF000; Rt |= (mem_word >> 4); break; 1250 case 2: Rt &= 0xFF00; Rt |= (mem_word >> 8); break; 1251 case 3: Rt &= 0xFFF0; Rt |= (mem_word >> 12); break; 1252 default: panic("lwr: bad offset"); 1253 } 1254#endif 1255 }}, 1256 {{ EA = (Rs + disp) & ~3; }}); 1257 } 1258 1259 0x7: FailUnimpl::reserved(); 1260 } 1261 1262 0x5: decode OPCODE_LO default FailUnimpl::reserved() { 1263 format StoreMemory { 1264 0x0: sb({{ Mem.ub = Rt<7:0>; }}); 1265 0x1: sh({{ Mem.uh = Rt<15:0>; }}); 1266 0x2: swl({{ 1267 uint32_t mem_word = 0; 1268 uint32_t aligned_addr = (Rs + disp) & ~3; 1269 uint32_t unalign_addr = Rs + disp; 1270 uint32_t offset = unalign_addr & 0x00000003; 1271 1272 DPRINTF(IEW,"Execute: aligned=0x%x unaligned=0x%x\n offset=0x%x", 1273 aligned_addr,unalign_addr,offset); 1274 1275 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); 1276 1277#if BYTE_ORDER == BIG_ENDIAN 1278 switch(offset) 1279 { 1280 case 0: 1281 Mem = Rt; 1282 break; 1283 1284 case 1: 1285 mem_word &= 0xF000; 1286 mem_word |= (Rt >> 4); 1287 Mem = mem_word; 1288 break; 1289 1290 case 2: 1291 mem_word &= 0xFF00; 1292 mem_word |= (Rt >> 8); 1293 Mem = mem_word; 1294 break; 1295 1296 case 3: 1297 mem_word &= 0xFFF0; 1298 mem_word |= (Rt >> 12); 1299 Mem = mem_word; 1300 break; 1301 1302 default: 1303 panic("swl: bad offset"); 1304 } 1305#elif BYTE_ORDER == LITTLE_ENDIAN 1306 switch(offset) 1307 { 1308 case 0: 1309 mem_word &= 0xFFF0; 1310 mem_word |= (Rt >> 12); 1311 Mem = mem_word; 1312 break; 1313 1314 case 1: 1315 mem_word &= 0xFF00; 1316 mem_word |= (Rt >> 8); 1317 Mem = mem_word; 1318 break; 1319 1320 case 2: 1321 mem_word &= 0xF000; 1322 mem_word |= (Rt >> 4); 1323 Mem = mem_word; 1324 break; 1325 1326 case 3: 1327 Mem = Rt; 1328 break; 1329 1330 default: 1331 panic("swl: bad offset"); 1332 } 1333#endif 1334 }},{{ EA = (Rs + disp) & ~3; }},mem_flags = NO_ALIGN_FAULT); 1335 1336 0x3: sw({{ Mem.uw = Rt<31:0>; }}); 1337 1338 0x6: swr({{ 1339 uint32_t mem_word = 0; 1340 uint32_t aligned_addr = (Rs + disp) & ~3; 1341 uint32_t unalign_addr = Rs + disp; 1342 uint32_t offset = unalign_addr & 0x00000003; 1343 1344 fault = xc->read(aligned_addr, (uint32_t&)mem_word, memAccessFlags); 1345 1346#if BYTE_ORDER == BIG_ENDIAN 1347 switch(offset) 1348 { 1349 case 0: 1350 mem_word &= 0x0FFF; 1351 mem_word |= (Rt << 12); 1352 Mem = mem_word; 1353 break; 1354 1355 case 1: 1356 mem_word &= 0x00FF; 1357 mem_word |= (Rt << 8); 1358 Mem = mem_word; 1359 break; 1360 1361 case 2: 1362 mem_word &= 0x000F; 1363 mem_word |= (Rt << 4); 1364 Mem = mem_word; 1365 break; 1366 1367 case 3: 1368 Mem = Rt; 1369 break; 1370 1371 default: 1372 panic("swr: bad offset"); 1373 } 1374#elif BYTE_ORDER == LITTLE_ENDIAN 1375 switch(offset) 1376 { 1377 case 0: 1378 Mem = Rt; 1379 break; 1380 1381 case 1: 1382 mem_word &= 0x000F; 1383 mem_word |= (Rt << 4); 1384 Mem = mem_word; 1385 break; 1386 1387 case 2: 1388 mem_word &= 0x00FF; 1389 mem_word |= (Rt << 8); 1390 Mem = mem_word; 1391 break; 1392 1393 case 3: 1394 mem_word &= 0x0FFF; 1395 mem_word |= (Rt << 12); 1396 Mem = mem_word; 1397 break; 1398 1399 default: 1400 panic("swr: bad offset"); 1401 } 1402#endif 1403 }},{{ EA = (Rs + disp) & ~3;}},mem_flags = NO_ALIGN_FAULT); 1404 } 1405 1406 format WarnUnimpl { 1407 0x7: cache(); 1408 } 1409 1410 } 1411 1412 0x6: decode OPCODE_LO default FailUnimpl::reserved() { 1413 0x0: LoadMemory::ll({{Rt.uw = Mem.uw}},mem_flags=LOCKED); 1414 1415 format LoadFloatMemory { 1416 0x1: lwc1({{ Ft.uw = Mem.uw; }}); 1417 0x5: ldc1({{ Ft.ud = Mem.ud; }}); 1418 } 1419 } 1420 1421 1422 0x7: decode OPCODE_LO default FailUnimpl::reserved() { 1423 0x0: StoreMemory::sc({{ Mem.uw = Rt.uw; Rt.uw = 1; }}); 1424 1425 format StoreFloatMemory { 1426 0x1: swc1({{ Mem.uw = Ft.uw; }}); 1427 0x5: sdc1({{ Mem.ud = Ft.ud; }}); 1428 } 1429 } 1430} 1431 1432 1433